Processor Architecture II! Sequential! Implementation!
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1 Processor Architecture II! Sequential! Implementation! Lecture 6, April 14 th 2011 Alexandre David Slides by Randal E. Bryant! Carnegie Mellon University!
2 Y86 Instruction Set! Byte! nop 0 0 halt 1 0 rrmovl ra, rb! 2 0 ra! rb! irmovl V, rb! rb! V! rmmovl ra, D(rB) 4 0 ra! rb! D! mrmovl D(rB), ra! 5 0 ra! rb! D! OPl ra, rb! 6 fn! ra! rb! jxx Dest! 7 fn! Dest! call Dest! 8 0 Dest! ret 9 0 pushl ra! A 0 ra! 8 popl ra! B 0 ra! 8 2! addl 6 0 subl 6 1 andl 6 2 xorl 6 3 jmp 7 0 jle 7 1 jl 7 2 je 7 3 jne 7 4 jge 7 5 jg 7 6
3 Building Blocks! fun! Combinational Logic! n Compute Boolean functions of inputs! n Continuously respond to input changes! A! B! A! L! U! 0! MUX! =! n Operate on data and implement control! 1!! Storage Elements! n Store bits! n Addressable memories! vala! srca! valb! A! Register! file! W! valw! dstw! n Non-addressable registers! srcb! B! Clock! n Loaded only as clock rises! Clock! 3!
4 Hardware Control Language! (reminder)! n Very simple hardware description language! n Can only express limited aspects of hardware operation! l Parts we want to explore and modify! Data Types! n n bool: Boolean! l a, b, c,! int: words! l A, B, C,! Statements! l Does not specify word size---bytes, 32-bit words,! n bool a = bool-expr ; n int A = int-expr ; 4!
5 HCL Operations! (reminder)! 5! n Classify by type of value returned! Boolean Expressions! n Logic Operations! l a && b, a b,!a n Word Comparisons! l A == B, A!= B, A < B, A <= B, A >= B, A > B n Set Membership! l A in { B, C, D }» Same as A == B A == C A == D Word Expressions! n Case expressions! l [ a : A; b : B; c : C ] l Evaluate test expressions a, b, c, in sequence! l Return word expression A, B, C, for first successful test!
6 SEQ Hardware Structure! State! n Program counter register (PC)! n Condition code register (CC)! n Register File! n Memories! l Access same memory space! l Data: for reading/writing program data! l Instruction: for reading instructions! Instruction Flow! n Read instruction at address specified by PC! n Process through stages! n Update program counter! PC! Write back! Memory! Fetch! icode!, ifun! ra!,!!rb! valc! Instruction! memory! PC! newpc! vale!,!valm! Addr!, Data! srca!,!srcb! dsta!,!dstb! valm! Bch! CC! alua!,!alub! Data! memory! valp! vale! ALU! vala!,!valb! PC! increment! A! B! M! E! Register! file! 6!
7 SEQ Stages! PC! Write back! newpc! vale!,!valm! valm! Fetch! n Read instruction from instruction memory! n Read program registers! n Compute value or address! Memory! n Read or write data! Write Back! PC! n Write program registers! n Update program counter! Memory! Fetch! icode!, ifun! ra!,!!rb! valc! Instruction! memory! PC! Addr!, Data! Bch! CC! alua!,!alub! srca!,!srcb! dsta!,!dstb! Data! memory! valp! vale! ALU! vala!,!valb! PC! increment! A! B! M! E! Register! file! 7!
8 Instruction Decoding! Optional! Optional! 5 0 ra! rb! D! icode! ifun! ra! rb! valc! Instruction Format! n Instruction byte n Optional register byte!icode:ifun!!ra:rb! n Optional constant word!valc! 8!
9 Executing Arith./Logical Operation! OPl ra, rb! 6 fn! ra!rb! Fetch! n Read 2 bytes! n Read operand registers! n Perform operation! n Set condition codes! Memory! n Do nothing! Write back! n Update register! PC Update! n Increment PC by 2! 9!
10 Stage Computation: Arith/Log. Ops! Fetch! OPl ra, rb! icode:ifun M 1 [PC]! ra:rb M 1 [PC+1]!! valp PC+2! vala R[rA]! valb R[rB]! vale valb OP vala! Set CC! Read instruction byte! Read register byte! n Formulate instruction execution as sequence of simple steps! n Use same general form for all instructions!! Compute next PC! Read operand A! Read operand B! Perform ALU operation! Set condition code register! Memory!!! Write! R[rB] vale! Write back result! back! PC update!! PC valp!! Update PC! 10!
11 Executing rmmovl rmmovl ra, D(rB)! 4 0 ra!rb! D! Fetch! n Read 6 bytes! n Read operand registers! n Compute effective address! Memory! n Write to memory! Write back! n Do nothing! PC Update! n Increment PC by 6! 11!
12 Stage Computation: rmmovl rmmovl ra, D(rB)! icode:ifun M 1 [PC]! Read instruction byte! ra:rb M 1 [PC+1]! Read register byte! Fetch! valc M 4 [PC+2]! Read displacement D! valp PC+6! Compute next PC! vala R[rA]! Read operand A! valb R[rB]! Read operand B! vale valb + valc! Compute effective address! PP 4.11! Memory! M 4 [vale] vala! Write value to memory! Write! back!!! PC update! PC valp! Update PC! n Use ALU for address computation! 12!
13 Executing popl popl ra! b 0 ra! 8 Fetch! n Read 2 bytes! n Read stack pointer! n Increment stack pointer by 4! Memory! n Read from old stack pointer! Write back! n Update stack pointer! n Write result to register! PC Update! n Increment PC by 2! 13!
14 Stage Computation: popl popl ra! icode:ifun M 1 [PC]! Read instruction byte! ra:rb M 1 [PC+1]! Read register byte! Fetch!!! valp PC+2! Compute next PC! vala R[%esp]! Read stack pointer! valb R [%esp]! Read stack pointer! vale valb + 4! Increment stack pointer! PP 4.12! PP 4.13! Memory! valm M 4 [vala]! Read from stack! Write! R[%esp] vale! Update stack pointer! back! PC update! R[rA] valm! PC valp! Write back result! Update PC! 14! n Use ALU to increment stack pointer! n Must update two registers! l Popped value! l New stack pointer!
15 Executing Jumps! jxx Dest! 7 fn! Dest! fall thru:! XX XX Not taken! target:! XX XX Taken! Fetch! 15! n Read 5 bytes! n Increment PC by 5! n Do nothing! n Determine whether to take branch based on jump condition and condition codes! Memory! n Do nothing! Write back! n Do nothing! PC Update! n Set PC to Dest if branch taken or to incremented PC if not branch!
16 Stage Computation: Jumps! jxx Dest! icode:ifun M 1 [PC]! Read instruction byte! Fetch! valc M 4 [PC+1]! valp PC+5! Read destination address! Fall through address! Bch Cond(CC,ifun)! Memory!!! Write! Take branch?! back!!! PC update! PC Bch? valc : valp! Update PC! 16! n Compute both addresses! n Choose based on setting of condition codes and branch condition!
17 Executing call call Dest! 8 0 Dest! return:! XX XX target:! XX XX Fetch! n Read 5 bytes! n Increment PC by 5! n Read stack pointer! n Decrement stack pointer by 4! Memory! n Write incremented PC to new value of stack pointer! Write back! n Update stack pointer! PC Update! n Set PC to Dest! 17!
18 Stage Computation: call call Dest! icode:ifun M 1 [PC]! Read instruction byte! PP 4.16! Fetch! valc M 4 [PC+1]! valp PC+5! valb R[%esp]! vale valb + 4! Read destination address! Compute return point! Read stack pointer! Decrement stack pointer! Memory! M 4 [vale] valp! Write return value on stack! Write! R[%esp] vale! Update stack pointer! back! PC update!! PC valc!! Set PC to destination! n Use ALU to decrement stack pointer! n Store incremented PC! 18!
19 Executing ret ret! 9 0 return:! XX XX Fetch! n Read 1 byte! n Read stack pointer! n Increment stack pointer by 4! Memory! n Read return address from old stack pointer! Write back! n Update stack pointer! PC Update! n Set PC to return address! 19!
20 Stage Computation: ret ret Fetch! icode:ifun M 1 [PC]!! Read instruction byte!! Memory! Write! back! PC update! vala R[%esp]! valb R[%esp]! vale valb + 4! valm M 4 [vala]! R[%esp] vale!! PC valm! Read operand stack pointer! Read operand stack pointer! Increment stack pointer! Read return address! Update stack pointer!! Set PC to return address! n Use ALU to increment stack pointer! n Read return address from memory! 20!
21 Computation Steps! OPl ra, rb! icode,ifun! icode:ifun M 1 [PC]! Read instruction byte! Fetch! ra,rb! valc! ra:rb M 1 [PC+1]!! Read register byte! [Read constant word]! valp! valp PC+2! Compute next PC! vala, srca! valb, srcb! vala R[rA]! valb R[rB]! Read operand A! Read operand B! vale! Cond code! vale valb OP vala! Set CC! Perform ALU operation! Set condition code register! Memory! valm!! [Memory read/write]! Write! dste! R[rB] vale! Write back ALU result! back! dstm!! [Write back memory result]! PC update! PC! PC valp! Update PC! n All instructions follow same general pattern! n Differ in what gets computed on each step! 21!
22 Computation Steps! call Dest! icode,ifun! icode:ifun M 1 [PC]! Read instruction byte! Fetch! ra,rb! valc! valc M 4 [PC+1]! [Read register byte]! Read constant word! valp! valp PC+5! Compute next PC! vala, srca! valb, srcb! valb R[%esp]! [Read operand A]! Read operand B! vale! Cond code! vale valb + 4! Perform ALU operation! [Set condition code reg.]! Memory! Write! valm! dste! M 4 [vale] valp! R[%esp] vale! [Memory read/write]! [Write back ALU result]! back! PC update! dstm! PC!! PC valc! Write back memory result! Update PC! n All instructions follow same general pattern! n Differ in what gets computed on each step! 22!
23 Computed Values! Fetch! icode!instruction code! ifun!instruction function! ra!instr. Register A! rb!instr. Register B! valc!instruction constant! valp!incremented PC! n vale!alu result! n Bch!Branch flag! Memory!! n valm!value from memory! srca!register ID A! srcb!register ID B! dste!destination Register E! dstm!destination Register M! vala!register value A! valb!register value B! 23!!
24 SEQ Stages! PC! Write back! newpc! vale!,!valm! valm! Fetch! n Read instruction from instruction memory! n Read program registers! n Compute value or address! Memory! n Read or write data! Write Back! PC! n Write program registers! n Update program counter! Memory! Fetch! icode!, ifun! ra!,!!rb! valc! Instruction! memory! PC! Addr!, Data! Bch! CC! alua!,!alub! srca!,!srcb! dsta!,!dstb! Data! memory! valp! vale! ALU! vala!,!valb! PC! increment! A! B! M! E! Register! file! 24!
25 SEQ Hardware! Key! n Blue boxes: predesigned hardware blocks! l E.g., memories, ALU! n Gray boxes: control logic! l Describe in HCL! n White ovals: labels for signals! n Thick lines: 32-bit word values! n Thin lines: 4-8 bit values! n Dotted lines: 1-bit values! PC Memory Execute Decode Fetch Bch CC icode ifun ra Mem. control ALU A Instruction memory PC newpc New PC rb read write vale ALU valc Data memory Addr ALU B valm data out Data valp vala PC increment ALU fun. valb A B M Register file E dste dstm srca srcb dste dstm srca srcb Write back 25!
26 Fetch Logic! icode ifun ra rb valc valp Instr valid Need valc Need regids PC increment Split Byte 0 Align Bytes 1-5 Instruction memory Predefined Blocks! n PC: Register containing PC! n Instruction memory: Read 6 bytes (PC to PC+5)! n Split: Divide instruction byte into icode and ifun! n Align: Get fields for ra, rb, and valc! PC 26!
27 Fetch Logic! icode ifun ra rb valc valp Instr valid Need valc Need regids PC increment Split Byte 0 Align Bytes 1-5 Instruction memory Control Logic! n Instr. Valid: Is this instruction valid?! n Need regids: Does this instruction have a register bytes?! n Need valc: Does this instruction have a constant word?! PC 27!
28 Fetch Control Logic! nop 0 0 halt 1 0 rrmovl ra, rb 2 0 ra rb irmovl V, rb rb V rmmovl ra, D(rB) 4 0 ra rb D mrmovl D(rB), ra 5 0 ra rb D OPl ra, rb 6 fn ra rb jxx Dest 7 fn Dest call Dest 8 0 Dest ret 9 0 pushl ra A 0 ra 8 popl ra B 0 ra 8 bool need_regids = icode in { IRRMOVL, IOPL, IPUSHL, IPOPL, IIRMOVL, IRMMOVL, IMRMOVL }; bool instr_valid = icode in { INOP, IHALT, IRRMOVL, IIRMOVL, IRMMOVL, IMRMOVL, IOPL, IJXX, ICALL, IRET, IPUSHL, IPOPL }; 28!
29 Decode Logic! Register File! n Read ports A, B! n Write ports E, M! n Addresses are register IDs or 8 (no access)! vala valb A B M Register file E dste dstm srca srcb dste dstm srca srcb valm vale Control Logic! n srca, srcb: read port addresses! icode ra rb n dsta, dstb: write port addresses! 29!
30 A Source! OPl ra, rb! vala R[rA]! Read operand A! rmmovl ra, D(rB)! vala R[rA]! Read operand A! popl ra! vala R[%esp]! jxx Dest! call Dest! ret vala R[%esp]! Read stack pointer! No operand! No operand! Read stack pointer! int srca = [ icode in { IRRMOVL, IRMMOVL, IOPL, IPUSHL } : ra; icode in { IPOPL, IRET } : RESP; 1 : RNONE; # Don't need register ]; 30!
31 E Destination! Write-back! Write-back! Write-back! Write-back! Write-back! Write-back! OPl ra, rb! R[rB] vale! rmmovl ra, D(rB)! popl ra! R[%esp] vale! jxx Dest! call Dest! R[%esp] vale! ret R[%esp] vale! Write back result! None! Update stack pointer! None! Update stack pointer! Update stack pointer! int dste = [ icode in { IRRMOVL, IIRMOVL, IOPL} : rb; icode in { IPUSHL, IPOPL, ICALL, IRET } : RESP; 1 : RNONE; # Don't need register ]; 31!
32 Execute Logic! Units! 32! n ALU! n CC! l Implements 4 required functions! l Generates condition code values! l Register with 3 condition code bits! n bcond! Control Logic! l Computes branch flag! n Set CC: Should condition code register be loaded?! n ALU A: Input A to ALU! n ALU B: Input B to ALU! n ALU fun: What function should ALU compute?! Bch bcond CC Set CC ALU A vale ALU ALU B icode ifun valc vala valb ALU fun.
33 ALU A Input! OPl ra, rb! vale valb OP vala! rmmovl ra, D(rB)! vale valb + valc! popl ra! vale valb + 4! jxx Dest! call Dest! vale valb + 4! Perform ALU operation! Compute effective address! Increment stack pointer! No operation! Decrement stack pointer! 33! ret vale valb + 4! Increment stack pointer! int alua = [ icode in { IRRMOVL, IOPL } : vala; icode in { IIRMOVL, IRMMOVL, IMRMOVL } : valc; icode in { ICALL, IPUSHL } : -4; icode in { IRET, IPOPL } : 4; # Other instructions don't need ALU ];
34 ALU Operation! OPl ra, rb! vale valb OP vala! Perform ALU operation! rmmovl ra, D(rB)! vale valb + valc! popl ra! vale valb + 4! jxx Dest! call Dest! vale valb + 4! Compute effective address! Increment stack pointer! No operation! Decrement stack pointer! ret vale valb + 4! Increment stack pointer! 34! int alufun = [ icode == IOPL : ifun; 1 : ALUADD; ];
35 Memory Logic! Memory! valm n Reads or writes memory word! Control Logic! n Mem. read: should word be read?! n Mem. write: should word be written?! n Mem. addr.: Select address! icode Mem. read Mem. write read write Data memory Mem addr vale data out Mem data data in vala valp n Mem. data.: Select data! 35!
36 Memory Address! Memory! OPl ra, rb!! No operation! rmmovl ra, D(rB)! Memory! M 4 [vale] vala! Write value to memory! popl ra! Memory! valm M 4 [vala]! Read from stack! jxx Dest! Memory!! No operation! call Dest! Memory! M 4 [vale] valp! Write return value on stack! Memory! ret valm M 4 [vala]! Read return address! 36! int mem_addr = [ icode in { IRMMOVL, IPUSHL, ICALL, IMRMOVL } : vale; icode in { IPOPL, IRET } : vala; # Other instructions don't need address ];
37 Memory Read! Memory! OPl ra, rb!! No operation! rmmovl ra, D(rB)! Memory! M 4 [vale] vala! Write value to memory! popl ra! Memory! valm M 4 [vala]! Read from stack! jxx Dest! Memory!! No operation! call Dest! Memory! M 4 [vale] valp! Write return value on stack! Memory! ret valm M 4 [vala]! Read return address! bool mem_read = icode in { IMRMOVL, IPOPL, IRET }; 37!
38 PC Update Logic! PC New PC! n Select next value of PC! New PC icode Bch valc valm valp 38!
39 PC Update! PC update! OPl ra, rb! PC valp! Update PC! rmmovl ra, D(rB)! PC update! PC valp! Update PC! popl ra! PC update! PC valp! Update PC! jxx Dest! PC update! PC Bch? valc : valp! Update PC! call Dest! PC update! PC valc! Set PC to destination! ret PC update! PC valm! Set PC to return address! 39! int new_pc = [ icode == ICALL : valc; icode == IJXX && Bch : valc; icode == IRET : valm; 1 : valp; ];
40 SEQ Operation! State! n PC register! Combinational Logic CC Read Read Ports Data memory Register file Write Write Ports n Cond. Code register! n Data memory! n Register file! All updated as clock rises! Combinational Logic! n ALU! n Control logic! PC 0x00c n Memory reads! l Instruction memory! l Register file! l Data memory! 40!
41 SEQ Operation #2! Clock Cycle 1: Cycle 2: Cycle 3: Cycle 4: Cycle 1 Cycle 2 Cycle 3 Cycle 4 0x000: irmovl $0x100,%ebx # %ebx <-- 0x100 0x006: irmovl $0x200,%edx # %edx <-- 0x200 0x00c: addl %edx,%ebx # %ebx <-- 0x300 CC < x00e: je dest # Not taken Combinational Logic CC 100 Read Read Ports Data memory Register file %ebx = 0x100 Write Write Ports n state set according to second irmovl instruction! n combinational logic starting to react to state changes! 41! PC 0x00c
42 SEQ Operation #3! Clock Cycle 1: Cycle 2: Cycle 3: Cycle 4: Cycle 1 Cycle 2 Cycle 3 Cycle 4 0x000: irmovl $0x100,%ebx # %ebx <-- 0x100 0x006: irmovl $0x200,%edx # %edx <-- 0x200 0x00c: addl %edx,%ebx # %ebx <-- 0x300 CC < x00e: je dest # Not taken Combinational Logic CC Read Read Ports Data memory Register file %ebx = 0x100 Write Write Ports n state set according to second irmovl instruction! n combinational logic generates results for addl instruction! 42! PC 0x00c 0x00e
43 SEQ Operation #4! Clock Cycle 1: Cycle 2: Cycle 3: Cycle 4: Cycle 1 Cycle 2 Cycle 3 Cycle 4 0x000: irmovl $0x100,%ebx # %ebx <-- 0x100 0x006: irmovl $0x200,%edx # %edx <-- 0x200 0x00c: addl %edx,%ebx # %ebx <-- 0x300 CC < x00e: je dest # Not taken Combinational Logic CC 000 Read Read Ports Data memory Register file %ebx = 0x300 Write Write Ports n state set according to addl instruction! n combinational logic starting to react to state changes! 43! PC 0x00e
44 SEQ Operation #5! Clock Cycle 1: Cycle 2: Cycle 3: Cycle 4: Cycle 1 Cycle 2 Cycle 3 Cycle 4 0x000: irmovl $0x100,%ebx # %ebx <-- 0x100 0x006: irmovl $0x200,%edx # %edx <-- 0x200 0x00c: addl %edx,%ebx # %ebx <-- 0x300 CC < x00e: je dest # Not taken Combinational Logic CC 000 Read Write Data memory Read Write Ports Ports Register file %ebx = 0x300 n state set according to addl instruction! n combinational logic generates results for je instruction! 44! PC 0x00e 0x013
45 SEQ Summary! Implementation! n Express every instruction as series of simple steps! n Follow same general flow for each instruction type! n Assemble registers, memories, predesigned combinational blocks! n Connect with control logic! Limitations! n Too slow to be practical! n In one cycle, must propagate through instruction memory, register file, ALU, and data memory! n Would need to run clock very slowly! n Hardware units only active for fraction of clock cycle! 45!
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