CS/EE 5740/6740: Computer Aided Design of Digital Circuits
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1 CS/EE 5740/6740: Computer Aided Design of Digital Circuits Chris J. Myers Lecture 2: Graph algorithms and a quick tour of logic synthesis Reading: Chapters 1 and 2 Delay Optimization First step is to identify the Critical Path Simplest delay model: number of logic levels Here the critical path is marked with black lines.
2 Critical Path Analysers Static Delay Models: Levels of Logic Delay function of size, load Worst, best case models Dynamic Delay Models Simpified device models Full Spice analysis VLSI => Scalable Algorithms In the 70s IBM found that 75% of all its cpu cycles went to critical path algorithms Scalable algorithms required, for which cpu time and space increase: linearly in problem size n (O(n)) log-linearly (O(nlog(n))) even quadratic (O(n 2 )) too expensive
3 Computing Critical Path Length This problem is modeled as that of finding the longest path in a DAG (Directed Acyclic Graph) Thus we digress for a while, and introduce the notions of sets and graphs Then we discuss a scalable (linear) complexity algorithm for finding the longest path in a DAG Graph Terminology Graph: ordered set of two sets 4 G = ( V, E) : a set of vertices or nodes : a set of edges or arcs : the successors (fanouts) of node 4 : the 4 predecessors = { 1, 3} (fanins) of node = { 1, 2}
4 Evaluating Algorithm Complexity- p28 Describing Logic Gates in BLIF OR3 (3-input OR gate) XOR3 (3-input XOR gate) z az1 b z az1 b c c.names az1 b c z names az1 b c z
5 Hierarchy and Subcircuits.model circuit.inputs x y.output zo1 zo2.subckt sub xi=x yi=y zi1=x2 zi2=y2.subckt sub xi=x2 yi=y2 zi1=zo1 zi2=zo2.model sub.inputs xi yi.outputs zi1 zi2.names xi yi zi1 x 1-1 sub -1 1 y.names xi yi zi end x2 y2 sub zo1 zo2 The Bit-Serial Adder UC Berkeley, sis> read_blif bsaddr.blif sis> print {zi} = cin e' + cin' e {cout} = c + f a = xi yi b = xi' yi' e = a' b' f = xi yi d = xi + yi c = cin d sis>
6 Shell Scripts (csh, tcsh) > script session Script started, file is session > sis sis> read_blif bsaddr.blif sis> print_stats bsaddr pi= 2 po= 1 nodes= 8 latches= 1 lits(sop)= 18 lits(fac)= 18 sis> quit > exit Here I typed ^d Script done, file is session SIS SCRIPTS > cat simul8 print_stats simplify Create with your favorite editor print_stats simulate > sis sis> read_blif bsaddr4.blif sis> source simul8 bsaddr4 pi= 8 po= 5 nodes= 32 latches= 1 lits(sop)= 72 lits(fac)= 72 bsaddr4 pi= 8 po= 5 nodes= 32 latches= 1 lits(sop)= 64 lits(fac)= 64 Network simulation: Outputs: Next state: 0 sis> quit
7 The LUNC Circuit LUNC = Lower case, Upper case, No change, or Change case case conversion circuit reset ck 8 8 LUNC LUNC Interface Input: 8-bit ASCII code of an alphanumeric character Output: Case conversion of the input character: ^[L => convert to Lower case ^[U => convert to Upper case ^[N => No conversion ^[C => Change case reset ck 8 8 LUNC
8 LUNC Specification Input string: a b C d E f ^[ U a b C D Output string: Latency = 2?? a b C d E f?? A B C D ^[L => convert to Lower case ^[U => convert to Upper case ^[N => No conversion ^[C => Change case? => don t care LUNC Block Diagram 2 registers in datapath, so latency is 2 cycles Controller FSM (Finite State Machine)
9 The Transform Block Behavioral Description of combinational logic: Procedure TRANSFORM (Rin,Lcmd,Ucmd,Ncmd,Ccmd) { if (Lcmd) {mux = TOLOWER(Rin)} else if (Ucmd) {mux = TOUPPER(Rin)} else if (Ncmd) {mux} = Rin} else if (Ccmd) {mux} = CHANGECASE(Rin) return(mux) } The Transform Block Diagram This implementation is clearly correct, but inelegant, since LC, UC, CC done every cycle We first show that SIS reduces the chip area from 606 literals to 12 literals, if the don t care conditions are specified Then we show that a clever, but not so obviously correct, design can implement this function in 12 literals directly.
10 .search tolower.blif.search toupper.blif.search changecase.blif.model transform.inputs L U N C i0 i1 i2 i3 i4 i5 i6 i7.outputs o0 o1 o2 o3 o4 o5 o6 o7.subckt tolower \ i0=i0 i1=i1 i2=i2 i3=i3 i4=i4 i5=i5 i6=i6 i7=i7 \ o0=l0 o1=l1 o2=l2 o3=l3 o4=l4 o5=l5 o6=l6 o7=l7.subckt toupper \ i0=i0 i1=i1 i2=i2 i3=i3 i4=i4 i5=i5 i6=i6 i7=i7 \ o0=u0 o1=u1 o2=u2 o3=u3 o4=u4 o5=u5 o6=u6 o7=u7.subckt changecase \ i0=i0 i1=i1 i2=i2 i3=i3 i4=i4 i5=i5 i6=i6 i7=i7 \ o0=c0 o1=c1 o2=c2 o3=c3 o4=c4 o5=c5 o6=c6 o7=c7.names L U N C l0 u0 i0 c0 o Transform.blif Tells SIS to read files (from same directory) First output bit of TRANSFORM: bits 1-7 similar. NOTE DEFAULT IS 0..exdc.names L U N C o Μ.names L U N C o end 2 or more 1 s No 1s Transform Block Don t Cares Exdc= Complement of Don t cares are all inputs such that 2 or more of {L,U,N,C} are 1, or none of them are Example of 1-hot encoding
11 The ChangeCase Block Procedure CHANGECASE(Rin) { if (isuc(rin)) {res = Rin + 32} else {res = Rin - 32} return (res) } Rin 32 / 8 isuc +/- / 8 res The ChangeCase Block If in5=1 bits of word 32 are complemented to do 2sComplement subtraction.model changecase.inputs in0 in1 in2 in3 in4 in5 in6 in7.outputs o0 o1 o2 o3 o4 o5 o6 o7.names zero.names one 1.subckt addsub8 addsub=in5 \ a0=in0 a1=in1 a2=in2 a3=in3 a4=in4 a5=in5 a6=in6 a7=in7 \ b0=zero b1=zero b2=zero b3=zero b4=zero b5=one b6=zero b7=zero \ s0=o0 s1=o1 s2=o2 s3=o3 s4=o4 s5=o5 s6=o6 s7=o7 s8=dummy.end Rin 32 / 8 Note blif constant constructs isuc +/- / 8 res
12 Transform Block SIS Commands Ignore these warnings sis> read_blif transform.blif Warning: network `tolower', node "dummy" does not fanout sis> ps transform pi=12 po= 8 nodes= 94 latches= 0 lits(sop)= 700 Don t worry--type source script.rugged SIS Optimization sis> source script.rugged sis> print_stats transform pi=12 po= 8 nodes= 9 latches= 0 lits(sop)= 12 sis> p {o0} = in0 {o1} = in1 {o2} = in2 {o3} = in3 {o4} = in4 {o5} = C in5' + L + N in5 {o6} = in6 {o7} = in7 [168] = -0- Used to be 700! Feedthrough Buffers, 1 literal each Simple Mux gate (5 lits)
13 ASCII Codes (p523) Hex Μ A=0x41=65= B=0x42=66= a=0x61=97= b=0x62=98= Note Only change is in bit 5, so Code(a) = Code(A) +32 The Optimized Transform Block Out 0-00 => 0 (UC) 1-00 => Rin => Rin => 1 (LC) Modulo the 1-hot don t cares, script.rugged gets Out = NcmdRin5+L+CcmdRin5, costing 5 lts (+7 feedthrough buffer lits makes 12) Note Ucmd is implicit 0-00 => Ucmd=1
14 Decoder The Command Interpreter Register LUNC? isesc load Latches Lcmd Ucmd Ncmd Ccmd Decoder: If previous character is escape, and if Current input character is L,U,N, or C, then the outputs Lcmd, Ucmd,Ncmd, and Ccmd are reset. Else they are Don t Cares The Command Interpreter Procedure lunc? (Rin) { if (Rin = L) Lcmd=1, Ucmd=Ncmd=Ccmd=0 else if (Rin = U) Ucmd=1, Lcmd=Ncmd=Ccmd=0 else if (Rin = N) Ncmd=1, Lcmd=Ucmd=Ccmd=0 else if (Rin = C) Ccmd=1, Lcmd=Ucmd=Ccmd=0 else Lcmd=Ucmd=Ncmd=Ccmd=Don't~Care return (Lcmd, Ucmd, Ncmd, Ccmd) }
15 Comparison For Equality A=B A 7 B 7 A=escape=0x1b=27 A 7 A 0 A 0 B 0 Distinguishing L,U,N,C (and everything else) L = 0x4C = = 74 U = 0x55 = = 85 N = 0x4E = = 78 C = 0x43 = = 67 The last2 bits are sufficient for distinguishing L,U,N,C Everything else is don t care Two Least significant bits A1 A0 isl isn isc Note isu not needed because of the One Hot assumption
16 Optimized Command Interpreter in7,,in1,in0 0 > Delay of 1 MUXs choose between current isl, isn, isc and previous state isl isesc > ol isn > on isc > oc Overall LUNC Circuit i7 x7 o7 b5 i0 x0 reg8 x7, x1,x0 CI Only isesc is delayed x5 Lcmd Ncmd Ccmd TB reg8 o0 Overall Latency of 2
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