ESE534 Computer Organization. Previously. Today. Spatial Programmable. Spatially Programmable. Needs?

Transcription

1 ESE534 Computer Organization Previously Universal building blocks Computations with gates Day 7: September 26, 2016 Interconnect Introduction 1 2 Today Universal Spatially Programmable Crossbar Programmable compute blocks Spatial Programmable LUT, ALU Start thinking about optimizing interconnect 3 4 Spatially Programmable Needs? Program up any function Not sequentialize in time Need a collection of gates. What else will we need? E.g. Want to build any FSM or any arithmetic operation 5 6 1

2 Needs Need some registers Need way to programmably wire gates together Multiplexer Interconnect Use a multiplexer for programmable interconnect Can select any source to be an input for a gate How big is an N-input multiplexer? 7 8 Sources? What are potential sources? Inputs to circuit -- I Outputs of gates -- G Outputs of registers R N=I+G+R Sinks Which things need programmable inputs? (and how many?) Circuit outputs -- O Gate needs one per input -- kg Assuming k-input gates Registers R M = O+R+kG 9 10 N-input, M-output Multiplexing Area? Bits to control the multiplexers? Data input switching Capacitance Switched? Delay? Mux Programmable Interconnect Area M N = (I+G+R) (O+kG+R) = kg 2 + Scales faster than gates!

3 Interconnect Costs Dominant Time We can do better than this Touch on a little later in lecture Dig into details later in term Even when we do better Interconnect can be dominate Area, delay, energy Particularly for Spatial Architectures 13 LUT is the gate. Definition coming soon 14 Dominant Power [Energy] Crossbar XC4003A data from Eric Kusse (UCB MS 1997) [Virtex II, Shang et al., FPGA 2002] [Tuan et al./fpga 2006] Crossbar Allows us to connect any of a set of inputs to any of the outputs. This is functionality provided with our muxes Crossbar Structure Can be more efficient

4 Crossbar Costs Crossbar Notation Area still goes as M N Delay proportional to M + N More realistic even for mux implementation Energy still goes as M N Gates with Crossbar Interconnect Programmable, Universal Program to any function of N gates Limitation we only use nand2 gates? What can we say about functions of arbitrary 2-input gates? Universal Computation with Fixed Compute Operator Being minimalists, this shows: do not need programmable compute to be universally programmable Just use fixed nor2 or nand2 Programmable Functions

5 Mux can be a programmable gate bool mux4(bool a, b, c, d, s0, s1) { return(mux2( mux2(a,b,s0), mux2(c,d,s0), } s1)); Program AND2? How do we program to behave as and2? Mux as Logic bool and2(bool x, y) {return (mux4(false,false,false,true,x,y));} bool or2(bool x, y) {return (mux4(false,true,true,true,x,y));} Just by routing data into this mux4, Can select any two input function LUT LookUp Table When use a mux as programmable gate Call it a LookUp Table (LUT) Implementing the Truth Table for small # of inputs # of inputs =k (need mux-2 k ) Just lookup the output result in the table Programmable Compute Programmable Compute Can use programmable gate in place of nor gate How do we program to perform a particular function?

6 Instructions Set of bits that tell the programmable units how to behave Is an Adder Universal? Assuming interconnect: (big assumption as we have just seen) Consider: What s c? A: 001a B: 000b S: 00cd Practically Arithmetic Logic Unit (ALU) To reduce (some) interconnect, and to reduce number of operations, do tend to build a bit more general universal computing function Observe: with small tweaks can get many functions with basic adder components Arithmetic and Logic Unit ALU Functions A+B w/ Carry B-A A xor B (squash carry) A*B (squash carry) /A

7 Programmable Functions Now seen 3 options: Use NAND gates what gate arrays did Not actually programmable gates Use LUTs what FPGAs do Use ALUs what Processor do Later in term we ll try to understand why might select one over other Costs and benefits Interconnect Optimization and Design Space Locality Compare Switches Maybe we don t need to connect everything to everything? Cluster groups of C things at leaves CG gates, CR registers Limit cluster I/O CI, CO Crossbar within cluster Crossbar among clusters Comparing Full Crossbar needs: kg 2 switches How many switches needed for: CG gates per cluster CI inputs to cluster CO outputs from cluster (ignore registers and circuit input/output) 8 16= =

8 Costs Cluster Input Crossbar: Inputs: CI+CG Outputs: kcg Cluster Output Crossbar: Input: CG Output: CO Master Crossbar: Inputs: (G/CG) CO Outputs: (G/CG) CI (G/CG) CO (G/CG) CI +(G/CG) (k CG 2 +k CG CI+CG CO) 43 Costs Cluster: G 2 (CI CO/CG 2 )+k G (CG+CI+CO) Full Crossbar: kg 2 Compare at: CG=8, CI=CO=2, G=256, k=2 Cluster case? Full crossbar case? 44 More? Can we do it again? Discuss Generalization? Issues? Optimizing Interconnect What other interconnect optimizations/ structures might we use? Interconnect Design Space Big Ideas Large interconnect design space We will be exploring systematically Day Can build universal, programmable spatial architecture Interconnect can be programmable Only programmability necessary Interconnect area/delay/energy can dominate compute area Exploiting structure can reduce area Locality

9 HW2 graded HW3 Wednesday HW4 out Admin Reading for Wed. on Web 49 9