CAEN Tools for Discovery

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1 Applicatio Note AN2086 Sychroizatio of CAEN Digitizers i Multiple Board Acquisitio Systems Viareggio 9 May 2013 Itroductio High speed digitizers fid applicatios i several fields ragig from the idustry to the study of uclear ad particle properties. I may cases complex measuremet systems are implemeted, which are composed by segmeted or multiple detectors. These systems may require several acquisitio chaels ad electroics to process all the iformatio. Digitizers implemet multiple iput chaels (e.g. CAEN V1720 cotais 8 chaels, while V1740 cotais 64 of them), but it may happe that more boards are eeded to acquire all the iformatio. The CAEN digitizers are desiged also to have logic iputs ad outputs which allow to create systems where boards operate as a all oe board with sychroous sigal samplig ad same time referece. To obtai this, boards eed to be sychroized, that is board iteral clocks are set sychroously ad the time referece is set the same. The sychroizatio, i geeral, allows the user to acquire from N boards with Y chael each, like if they were just oe board with (N x Y) chaels. The aim of the preset ote is to show how to sychroize two or more homogeeous 1 CAEN digitizers i a multi-board acquisitio system. We describe the steps eeded to sychroize a simple system, composed by two V1720 (i the preset ote we geerally refer to the properties of this digitizer board) ad we are goig ow to illustrate a hardware ad software setup which ca be easily geeralized to more complex cases. What does sychroize differet boards mea? It is possible to obtai the sychroizatio of a multiboard system with four mai system settigs. I. Same clock propagated to all boards. II. III. The CAEN digitizers have iput ad output coectors which receive ad distribute the clock sigal. This allows to sychroize the boards by mea of the fa-out of a clock sigal or the propagatio through the board daisy chai. I the secod case, oe digitizer board geerates its iteral clock ad distributes it by the use of exteral clock output coectors. Such board represets the master board of the acquisitio system. The remaiig boards through their iput coectors are liked to the master board clock sigal ad act as clock slaves. Each board cotais a Phase Lock Loop (PLL) which sythetizes the board clock either from a iteral oscillator or from a exteral clock referece. Together with a programmable phase adjust it is possible to compesate for the delay i the propagatio of the clock sigal from a board to the other. I this way it is possible to alig the clock of each board. Same time referece for all boards. I ormal applicatios, all boards belogig to a acquisitio system have to start with the same time referece. For this reaso iput ad output coectors are used to sychroize the start of the data takig ad the time referece. The start logic sigal ca be propagated i daisy chai to all boards belogig to the acquisitio system. The propagatio of the start sigal itroduced a delay alog the digitizer chai. This ca be compesated itroducig time offsets i the data acquisitio start. Trigger propagatio ad/or correlatio. Digitizers are able to receive exteral trigger sigals ad propagate them outside. This allows e.g. to propagate a global trigger sigal i daisy chai whe evets of iterest have to be recorded. Moreover the evet selectio ca be either due to a iput sigal crossig the threshold set o its acquisitio chael (chael auto-trigger) or to the output of logic 2 algorithms: e.g. the FPGA ca be programmed to require that more tha oe chael registered sigals over the threshold (majority operator). This feature allows to implemet more complex trigger selectios which ca be used i case of more complex detector systems where the correlatio betwee differet subuits has to be cosidered. IV. Readout sychroizatio ad evet aligmet 3 For most of applicatios, all the digitizers of a acquisitio system have to keep their memory buffers available for the storage of ew iformatio at the same time. The CAEN digitizers ca implemet a mechaism that prevets a asychroous data takig, which may happe whe at least oe of the boards eters i a busy coditio. The digitizer boards have BUSY IN/OUT ad VETO IN/OUT coectors, which allow to stop the data acquisitio ad restore the system sychroizatio. The coectors are available with LVDS stadard. 1 This applicatio ote does ot show how to sychroize a umber of o-homogeeous set of CAEN digitizers (V V1720 for istace). Eve if o-homogeeous cofiguratio ca be i priciple implemeted, it has issues due to differet clock speed that are ot tackled i this documet. 2 The curret firmware release allows to the require the majority logic operatio. 3 New firmware curretly uder test, the matter is ot described i this documet. 1

2 Applicatio Note AN2086 Sychroizatio of CAEN Digitizers i Multiple Board Acquisitio Systems Board Clock, Trigger Logic ad Samplig The samplig clock of the CAEN digitizer V1720 is either locked to a iteral oscillator or to a exteral clock source. We will later see that this clock sigal is geerated ad distributed to the differet compoets of the digitizer. The couter which gives the evet time tag, the trigger logic ad the ADC samplig work with differet frequecies. The evet time tag, also called trigger time tag (TTT) is give by a couter which marks the arrival time of a exteral trigger sigal or the time whe a sigal crosses the relative threshold set. For digitizers V1720 it is expressed i uits of its clock cycles, 8 s, correspodig to a frequecy of 125 MHz. However, whe the acquired data is writte ito the board iteral memory, the TTT couter is read every 2 trigger logic clock cycles, which meas that the trigger time stamp has a effective resolutio of 16 s. The trigger logic algorithms operates at a frequecy that is 125 MHz, while the ADC samplig frequecy is 250 MHz. Boards other tha the V1720 have differet characteristic clock frequecies for their iteral operatios; please refer to the correspodig techical maual. Table 1 summarizes the clock frequecies of the digitizers CAEN V1720, V1751, V1724 ad V1740. Digitizer Model Trigger Time Tag Resolutio (s) Trigger Logic Cycle (s) Samplig Cycle (s) V V V V Table 1. Characteristic clocks of CAEN digitizer V1720, V1751, V1724 ad V1740. Outlie This ote describes first the steps eeded to obtai the sychroizatio of the board clocks. This operatio is ecessary to proceed with the rest of the applicatio which wats achieve a simplified sychroizatio of the data acquisitio system. I the ext chapters three hardware setups are give as examples. We briefly describe them here: 1. The first example cosiders a case where all boards acquire evets whe a exteral trigger source is provided. The trigger is set to the master board which the propagates the trigger sigal i daisy chai. 2. I the secod example boards acquire evets idepedetly through their chael auto-triggers (waveforms crossig the thresholds set) or sigals from a exteral trigger source. 3. I the third example boards acquire oly o a exteral global trigger. The chael auto-triggers are ot cosidered for the evet selectio, but their logic states are propagated to the board trigger output coector. The trigger sigals from each digitizer reach the a exteral logic uit, which the provides the system global trigger. A more comprehesive descriptio of the hardware setup is give i the ext chapters. Requiremets The preset ote is based o the sychroizatio of digitizers CAEN model V1720. With differet digitizers, time settig may vary accordigly with the boards hardware properties. The followig hardware ad software tools are used. Hardware 2 V Chael 12bit 250 MS/s Digitizers 1 V1718 USB VME Bridge 1 A317 Clock Distributio cable 1 Oscilloscope 1 Programmable Fuctio Geerator 1 V976 VME Logic Uit (used i the third example) 1 V993B VME Dual Timer (optioal for the third example) 4 Clock coditios uder PLL mode acquisitio, see Techical Iformatio Maual of the V

3 Applicatio Note AN2086 Sychroizatio of CAEN Digitizers i Multiple Board Acquisitio Systems Software CAENUpgrader Release SycTest Board Firmware Firmware Release or successive for digitizers V1720/x51/x24 CAENUpgrader is a software composed of commad lie tools together with a Java Graphical User Iterface (for Widows ad Liux OS). CAENUpgrader allows i few easy steps to upload differet firmware versios o CAEN boards ad bridges, to upgrade the VME digitizers PLL, to get the board iformatio ad bridge firmware revisio ad to maage the firmware licese. CAEN SycTest is a simple software writte specifically for this applicatio ote. It cotais the most relevat commads to adjust the cofiguratio parameters of the boards ad read the acquired evet data. It represets a example for settig sychroizatio ad trigger distributio. It is provided as a archive of ANSI C source ad header files. Clock Sythesis ad Distributio Figure 1 reports a simplified sketch of the digitizers clock sythesis ad distributio. We report here a brief descriptio of the hardware compoets ad their operatios. We will see i the ext pages how CAENUpgrader modifies the clock cofiguratio. - I CAEN digitizers the clock maagemet is provided by a PLL (Phase-locked Loop) ad a Clock Distributor. The PLL ca receive a referece clock from either a iteral oscillator or a exteral clock source through the clock iput (CLK-IN) coector. A mechaic switch o the board allows to select the clock geerator. - The role of the PLL is therefore to alig the phase of a Voltage Cotrolled Crystal Oscillator (VCXO) of the digitizers to the referece oe. - The clock geerated by the VCXO is passed to the Clock Distributor, which splits the clock sigal i differet braches. Each brach but oe is set to board subsystems: the mai board FPGA ad the mezzaies (which cotai ADC s, FPGA s ad memory buffers). The remaiig brach is coected to the clock output (CLK OUT) coector. The Clock Distributor ca sed a differet sub multiple of the VCXO frequecy to each brach. - The Clock Distributor ca also apply a delay to the CLK OUT coector. This is a key feature of the sychroizatio sice it ca compesate the effect of the clock shift due to the clock daisy chai betwee differet boards. 5 I this Applicatio Note we used maiboard FPGA firmware Release 4.0 ad mezzaie FPGA firmware Release

4 Applicatio Note AN2086 Sychroizatio of CAEN Digitizers i Multiple Board Acquisitio Systems Figure 1: Represetatio of the clock sigal sythesis ad distributio i the digitizer boards. Clock Sychroizatio As we already wrote above, the first actio to be performed to obtai the sychroizatio of the acquisitio system is the sychroizatio of the clock ad its phase aligmet. - I the multi-board acquisitio system, the master board (hereafter Master), will act as clock master providig a referece clock to the other oe, that therefore will be a clock slave (hereafter Slave). - The CLK OUT of the Master is coected to the CLK IN of Slave through the A317 cable. - With CAENUpgrader software we cofigure the Master PLL i order to eable the output of the clock (62.5 MHz) ad cofigure the Slave PLL i order to accept the exteral clock. - The TRG OUT of both boards ca be programmed usig SycTest, to deliver the clock sigal. This will allow through the use of a oscilloscope to observe the aligmet of the clock sigals. - The we use the CAENUpgrader program to set a delay o the Master clock output i order to obtai the aligmet of the clock sigals produced by TRG OUT of each board. We report i the ext pages a step-by-step example of clock sychroizatio procedure. NOTE: this ote describes a hardware setup with digitizers cotrolled by a PC coected to a USB VME Bridge Mod. V1718. With appropriate drivers it is possible to use the coectios through Optical Lik. It requires the use of PCI/PCIe optical cotroller A2818/A3818 directly coected to the Digitizers or via the V2718 VME/PCI Bridge. 4

5 Applicatio Note AN2086 Sychroizatio of CAEN Digitizers i Multiple Board Acquisitio Systems Step 1 Hardware Setup (a): Set VME address The VME addresses used i this example are: Master: 0x Slave: 0x VME Address Step 2 Exteral clock Iteral clock Hardware Setup (b): Set board clock sources Master clock source: iteral Slave clock source: exteral CLK SOURCE 5

6 Applicatio Note AN2086 Sychroizatio of CAEN Digitizers i Multiple Board Acquisitio Systems Step 3 Master clock board Clk source: Iteral CLK OUT Slave board Clk source: Exteral CL KIN Hardware Setup (c): coect boards ad oscilloscope - Coect Master CLK OUT to Slave CLK IN usig A317 cable - Coect the TRG OUT outputs of both the boards to a oscilloscope with cables of equal legth (50 Ω termiatio required) TRG OUT TRG OUT A317 Clock distributio cable Step 4 #iclude "syctest.h" USB coectio void SetUserParams(UserParams_t *Params) { // CONNECTION PARAMETERS: // CoectioType: ca be CAEN_DGTZ_USB, //CAEN_DGTZ_PCI_OpticalLik (A2818) or CAEN_DGTZ_PCIE_OpticalLik (A3818) // LikNum: USB or PCI/PCIe eumeratio (typ=0) // CoetNode: positio i the optical daisy chai // BaseAddress: oly for VME access (otherwise 0) Set SycTest operatioal parameter i userparam.c source Params->CoectioType[0] = CAEN_DGTZ_USB;//CAEN_DGTZ_PCI_OpticalLik; // Params->LikNum[0] = 0; Params->CoetNode[0] = 0; Params->BaseAddress[0] = 0x ; //Master board VME address Slave Params->CoectioType[1] = CAEN_DGTZ_USB;//CAEN_DGTZ_PCI_OpticalLik; // Params->LikNum[1] = 0; Params->CoetNode[1] = 0; Params->BaseAddress[1] = 0x ; //Slave board VME address Master 6

7 Applicatio Note AN2086 Sychroizatio of CAEN Digitizers i Multiple Board Acquisitio Systems Step 5 Ru CAENUpgrader to program Master PLL (a) From the Board Upgrade tab, perform the followig steps. - Select the Upgrade PLL optio i the Available actios scroll meu: the Board s Model box will appear right below. - Select your board model i the Board s Model scroll meu; i our example we selected a V Coectio Type cotrol box will let you select the type of coectio you are usig (i our example, USB). - LINK umber allows for choosig betwee differet boards/bridges liked to your computer, if you are usig more tha oe coectio lik. I our example we leave this field set to 0, which is the default value. - Type i the appropriate box the VME Base Address of the Master VME Board. - Click New butto to ope PLL cofiguratio widow. Step 6 Ru CAENUpgrader to program Master PLL (b) I the PLL cofiguratio widow perform the followig steps. - Set the VCXO frequecy. You ca click o the Read from Board butto. - A ew widow will appear which reports all the coectio iformatio already etered i Coectio Type. - Click o the Read from Board butto o the widow Step 7 Ru CAENUpgrader to program Master PLL (c) I the PLL cofiguratio widow perform the followig steps. - Eable the output clock ad set its frequecy. Differet frequecies ca be chose ad i this example we choose 62.5 MHz. - At first stage we set Delay = <Disabled>. - Oce the PLL cofiguratio has bee set accordig to your purposes, you have to save the cofiguratio file o your computer by clickig o the Save butto. 7

8 Applicatio Note AN2086 Sychroizatio of CAEN Digitizers i Multiple Board Acquisitio Systems Step 8 Ru CAENUpgrader to program Master PLL (d) - Automatically the PLL settigs widow disappears ad the file ame ad locatio is loaded i the PLL upgrade file box. - Click Upgrade butto. Step 9 Ru CAENUpgrader to program Master PLL (e) If the Master PLL upgrade is OK, the PLL upgrade success message is displayed. - Do ot reboot ow the Master, but proceed with the upgrade the Slave PLL. - Click New butto to ope PLL cofiguratio widow. Step 10 Ru CAENUpgrader to program Slave PLL (a) - Repeat the step P6 settig i the appropriate box the VME Base Address of the Slave VME Board. - Set the VCXO frequecy (click the Read from Board butto). - Set the iput clock at MHz frequecy. - The output clock ca be set for the slave board. This cofiguratio is ecessary i case the slave must provide the clock to the ext slave board i the daisy chai. I the figure 62.5 MHz output clock is set. - We set Delay = <Disabled>. 8

9 Applicatio Note AN2086 Sychroizatio of CAEN Digitizers i Multiple Board Acquisitio Systems Step 11 Ru CAENUpgrader to program Slave PLL (b) I the PLL cofiguratio widow perform the followig steps. - Oce the PLL cofiguratio has bee set accordig to your purposes, you ca save the cofiguratio file o your computer by clickig o the Save butto. - Automatically the PLL settigs widow disappears ad the file is loaded i the PLL upgrade file box. - Click Upgrade butto. - If the Slave PLL upgrade is OK, the PLL Upgrade success message is displayed Step 12 Reboot the boards, compile ad ru SycTest - Reboot the boards. - Compile SycTest. For this procedure 3 CAEN libraries are required: CAENDigitizer, CAENComm (rel. 1.0 or later), CAENVMELib. Step 13 Compile ad ru SycTest - Compile SycTest. - Lauch SycTest ad press c to eable the clock sigals o the TRG OUT coectors. - Sigals o the scope should appear. 9

10 Applicatio Note AN2086 Sychroizatio of CAEN Digitizers i Multiple Board Acquisitio Systems Step 14 Master Slave Delay Scope display The two clock sigals o the TRG OUT coectors have the same frequecy, i.e. the delay betwee the edges of the two sigals is kept costat. This behavior is esured by the Slave PLL that is locked o the clock output by the Master. However the two sigals are ot i phase. The digitizers allow to set a delay to the clock output. We ca set a delay o the Master clock output so that the risig edge of the Slave is retarded ad locked the master risig edge. We ca use the CAENUpgrader to set the proper delay. - Frequecy of Master ad Slave clock o the TRG OUT coectors = 125 MHz (period T= 8 s ). - Delay betwee Master ad Slave clocks o the TRG OUT coectors: = 2.82 s. - Delay to be applied at Master CLK OUT = 2.82s. Step 15 Ru CAENUpgrader to program Master PLL (a) - Repeat the Step 5 - Set the VCXO frequecy (click the Read from Board butto). - Eable the Output clock at MHz frequecy. - The Delay meu allows to set the delay value which is the closest to the desired oe. The possible choices rage from 570 ps to 9870 ps i 31 steps of 300 ps. - I this example the delay set = ps. - Oce the PLL cofiguratio has bee set accordig to your purposes, you ca save the cofiguratio file o your computer by clickig o the Save butto. - Automatically the PLL settigs widow disappears ad the file is loaded i the PLL upgrade file box. - Click Upgrade butto. - If the Master PLL upgrade is OK, the PLL Upgrade success message is displayed. Step 16 Ru SycTest - Lauch SycTest ad press c to eable the clock sigals o the TRG OUT coectors. - Sigals o the scope should appear - Press r i the SycTest widow to reload the PLL cofiguratio. Sigals o the scope should be ow sychroized. 10

11 Applicatio Note AN2086 Sychroizatio of CAEN Digitizers i Multiple Board Acquisitio Systems Step 17 Scope display The two clock sigals are time aliged. Master Slave 11

12 Applicatio Note AN2086 Sychroizatio of CAEN Digitizers i Multiple Board Acquisitio Systems Example 1: Exteral Trigger Propagatio This sectio will describe how to sychroize differet boards where the trigger comes from a exteral source ad is propagated alog the system through a daisy chai. The aim is to show how to coect all the boards to propagate the trigger sigal i daisy chai. A exteral trigger source geerates the trigger sigal to be fed i the Master iput. The hardware setup is show i Figure 2. The boards are coected as i the follows. - Coect Master CLK OUT to Slave CLK IN usig A317 cable. - Coect the TRG OUT of the Master to TRG IN of the Slave. - Coect Fuctio Geerator CH1 output to a 50 Ω passive splitter. - Coect both chaels (#6 i this example) of each digitizer to the splitter with idetical legth cables. Tektroix AFG3252 Fuctio Geerator A317 Clock distributio cable Master clock board Clk source: Iteral CLK OUT TRG OUT Slave board Clk source: Exteral CL KIN TRG OUT 50 Ω Splitter Global Trigger TRG IN TRG IN Sigal Source: Fa out of two of a pulser sigal, sychroized with the Trigger Source, set to ay chael of each board with cables of equal legth. Figure 2: Hardware setup. Coectio of boards ad fuctio geerator. The setup is such that: the exteral trigger goes to TRG IN of the Master; the daisy chai TRG IN/TRG OUT propagates the trigger ad the start of the data acquisitio; the sigal source is the fa out of two of a fuctio geerator, sychroized with the trigger source, set to oe chael of each board with cables of equal legth. The start of the evet acquisitio happes i the followig way: all Slave boards armed to start with TRG IN edge; a software (SW) trigger is set to the Master (with the use of SycTest 6, described i Step 21); the SW trigger is propagated through the daisy chai TRG IN/TRG OUT ad starts all the boards (i this way a delay is itroduced ad is described ext); at this poit Master is programmed i order to accept trigger o the TRG IN coector. The exteral trigger sigals go through the daisy chai ad trigger all the boards. I case oe of the boards is i a busy state the acquisitio ca loose the evet aligmet. To veto this possibility a busy sigal ca be propagated to last board (with LVDS I/Os) ad set through the TRG OUT of the last board (NIM or TTL) to ihibit either the exteral trigger source or the Master trigger iput through the S IN programmed as trigger VETO 7. 6 The ru ca also start with the 1st hardware trigger, the software has to be cofigure for this purpose. 12

13 Applicatio Note AN2086 Sychroizatio of CAEN Digitizers i Multiple Board Acquisitio Systems The daisy chai propagates the trigger sigal from the Master to the Slave. The SW trigger that starts the acquisitio arrives to the Slave with a delay proper of this hardware cofiguratio. To esure that all digitizers start the acquisitio at the same time a delay i the start of the evet acquisitio ca set for the Master. This feature ca be geeralized to a hardware system with multiple boards. Figure 3 represets the timig of the SW trigger ad the acquisitio start of a system with 2 or 3 boards. MASTER Acquisitio State Acquisitio stopped Acquisitio active Ru Delay * 2 Trigger Time Tag ACQUISITION START Digitizers do ot acquire ad store ADC data Digitizers start acquirig ad storig ADC data TRG OUT SLAVE(1) SLAVE(2) Acquisitio State Acquisitio stopped Acquisitio active Ru Delay Trigger Time Tag TRG OUT Trigger Time Tag Acquisitio State Acquisitio stopped Acquisitio active Figure 3: Timig diagram of the start of ru sequece I SycTest (see 0) you ca set the correct delay to obtai the time aligmet of the board acquisitio start: this will esure that they will have the same time referece. Note i Figure 3, that the trigger time tag (TTT) couters start at the same time; this will the allow to require temporal correlatios betwee evets acquired from differet digitizers. I this hardware setup the digitizers are cofigured such that the sigals from the exteral global trigger, received after the SW trigger start, are cosidered valid for the evet acquisitio. The trigger sigal set to the Master is propagated to the Slave i daisy chai, so the latter will receive the trigger sigal with a fixed delay compared to the Master. All boards start the acquisitio sychroously, so the trigger propagatio itroduces a delay also i the TTT of the evets acquired by the Slave. Figure 4 represets the resultig TTT recorded by the boards. Master TRG-IN Master Trigger Time Tag Master Acquisitio State Master Trigger Time Couter T T+1 T+2 Acquisitio active DeltaT Time Tag T+3 T+4 T+5 Slave TRG-IN Slave(1) Acquisitio State Acquisitio active Slave(1)Trigger Time Couter T T+1 T+2 T+3 T+4 T+5 Slave Trigger Time Tag Figure 4: Sychroous Master ad Slave acquisitio (ote that the Trigger Time Tags are differet) 7 New firmware curretly uder test, ot described i this documet 13

14 Applicatio Note AN2086 Sychroizatio of CAEN Digitizers i Multiple Board Acquisitio Systems The memory buffer of the digitizers record the evets with a timig that is give by the arrival of the trigger sigal. The delay i the TTT of the Slave implies that its memory buffer cotais the samplig iformatio that is out of phase compared to the oe of the Master. Figure 5 better explais the delay itroduced i the memory buffer of the Slave. Master TRG-IN Slave TRG-IN Iput Sigal Recorded (Master ad Slave) Recorded (Slave oly) Recorded (Master oly) Acquisitio widow Master PRE POST Not Recorded Acquisitio widow Slave PRE POST T a T b T c T d T0 Master Trigger Time Tag Slave Trigger Time Tag Figure 5: Master ad Slave acquisitio widows (time frame) The SycTest software is set i a way that waveforms ca be observed both with the represetatio i the buffer referece frame ad the time referece frame (see Step 27 ad Step 28). The represetatio i the time referece is show i Figure 6, where T a ad T b are the arrival times of the trigger sigal mius a fixed offset (see also Figure 5). The represetatio i the buffer frame is show i Figure 7. We ow describe the step ecessary to obtai the sychroizatio of the boards i this hardware cofiguratio. Master Slave T a T b T c T d Time Figure 6: SycTest plot of the Master ad Slave acquisitio widows (time frame). 14

15 Applicatio Note AN2086 Sychroizatio of CAEN Digitizers i Multiple Board Acquisitio Systems Master Slave Sample 0 of the Acquistio widow Samples Sample N of the Acquistio widow Figure 7: SycTest plot of the Master ad Slave acquisitio widows (buffer frame). Step 18 Digitizer clock sychroizatio - Perform the Step 1-17 to sychroize ad alig the clock - Oce clocks are sychroized, it is possible to cofigure the start of acquisitio i order to have the same time referece for both boards. Step 19 Fuctio Geerator CH1 output Hardware setup (B): set sigal parameter of pulse geerator - The program SycTest operates a fit o the fallig (or risig) edge of the pulse to compute time iformatio. If multiple poits are available to fit the waveform the result may be more reliable. - Set rise time > 5 x samplig period. I this example rise time is set to 50 s. - Set width = 300 s. Fuctio Geerator Trigger Output 15

16 Applicatio Note AN2086 Sychroizatio of CAEN Digitizers i Multiple Board Acquisitio Systems Step 20 Set SycTest operatioal parameter i userparam.c source // *************************************************************************************************** // Start Mode: // *************************************************************************************************** // Optios: START_SW_CONTROLLED, START_HW_CONTROLLED Params->StartMode = START_SW_CONTROLLED; propagate this start sigal to the Slave board through the TRG OUT // *************************************************************************************************** TRG IN daisy chai // Syc Mode: // *************************************************************************************************** // Optios: COMMONT_EXTERNAL_TRIGGER_TRGIN_TRGOUT, INDIVIDUAL_TRIGGER_SIN_TRGOUT, TRIGGER_ONE2ALL_EXTOR Params->SycMode = COMMONT_EXTERNAL_TRIGGER_TRGIN_TRGOUT; Set Syc Mode accordig to this Sychroizatio setup // CHANNEL SETTINGS Params->RefChael[0] = 6; // Chael of the Master used for the acquisitio Params->TriggerThreshold[0] = 2000; // Trigger threshold (for self triggerig) Params->PostTrigger[0] = 50; // Post trigger i percet of the acquisitio widow Params->DCoffset[0] = 0x8000; // iput DC offset adjust (DAC value) Params->RefChael[1] = 6; // Chael of the Slave used for the acquisitio Params->TriggerThreshold[1] = 2000; // Trigger threshold (for self triggerig) Params->PostTrigger[1] = 50; // Post trigger i percet of the acquisitio widow Params->DCoffset[1] = 0x8000; // iput DC offset adjust (DAC value) // Trigger edge (CAEN_DGTZ_TriggerORisigEdge, CAEN_DGTZ_TriggerOFalligEdge) Params->TriggerEdge = CAEN_DGTZ_TriggerOFalligEdge; Set Start Mode software cotrolled. I this way the Master Board will wait for a software sigal to start the acquisitio ad will // Number of samples i the acquisitio widows Params->RecordLegth = 500; Set acquisitio chael Master ad Slave // Max. distace betwee the trigger time tags i order to cosider a valid coicidece Params->MatchigWidow = 10; // Frot Pael LEMO I/O level (NIM or TTL). Optios: CAEN_DGTZ_IOLevel_NIM, CAEN_DGTZ_IOLevel_TTL Params->IOlevel = CAEN_DGTZ_IOLevel_TTL; Set Frot Pael I/O level Step 21 Compile ad Ru SycTest - Compile SycTest - Lauch SycTest ad press s to start ru - Oce the acquisitio is started, the SycTest widow should show some parameter as below 16

17 Applicatio Note AN2086 Sychroizatio of CAEN Digitizers i Multiple Board Acquisitio Systems Step 22 ADC Chaels T0 DeltaT Edge Board 0 Board 1 T1 Time SycTest acquisitio parameters (1) The program output o the shell should appear i the format represeted i the figure o the left. If the cofiguratio parameters are successfully set all fields appear complete. If some iformatio is missig it is ecessary to modify the chael DC offsets (see Step 27) or the trigger thresholds (see Step 30). - Readout Rate shows the amout of data trasferred from the board. - TrgRate shows the Trigger rate felt by the two boards. It must obviously be the same for both the boards ad equal to the frequecy of the exteral trigger source. - Matchig Evets value shows the percetage of evets withi the coicidece widow. The width of this coicidece widow ca be set i the Userparams.c Sice sigals to the board are sychroous with the exteral trigger a 100% value is expected. - Missig Edge value shows the umber of evets i which sigals are ot i the coicidece widow. - DeltaT Edge value is the measuremet of the differece i time betwee the two sigals i s. It is calculated makig a iterpolatio of two samples before ad after the threshold ad the calculatig the differece betwee the two resultig poits o the threshold. The ru start is propagated i daisy chai, so at the preset time, without ay correctio, the time refereces are ot sychroized. - DeltaT Time tag value is the differece i s betwee the 2 trigger time tag (TTT) withi the coicidece widow. Step 23 Syctest acquisitio parameters (2) - DeltaT Edge = 58.1 s is about four times the cycle of the trigger time tag (4 x 16 s for the V1720 module). - The firmware allows to add a delay to the start of the acquisitio, so we proceed with the adjustmet of RUN delay parameter i syctest.c source (see Step 26). - The delay is expressed i uit of trigger time tags (16 s for the V1720 module). 17

18 Applicatio Note AN2086 Sychroizatio of CAEN Digitizers i Multiple Board Acquisitio Systems Step 24 it SetSycMode(it hadle[2], UserParams_t Params) { it i, ret=0; uit32_t reg; for(i=0; i<2; i++) { switch (Params.SycMode) { case COMMONT_EXTERNAL_TRIGGER_TRGIN_TRGOUT : if (i == 0) } } retur ret; } Set SycTest operatioal parameter i syctest.c source // ihibit TRGIN o board 0 i order // to avoid start of ru with exteral triggers ret = CAEN_DGTZ_WriteRegister(hadle[i], ADDR_EXT_TRG_INHIBIT, 1); ret = CAEN_DGTZ_WriteRegister(hadle[i], ADDR_GLOBAL_TRG_MASK, 0xC ); // accept EXT TRGIN or SW trg ret = CAEN_DGTZ_WriteRegister(hadle[i], ADDR_TRG_OUT_MASK, 0xC ); // propagate both EXT ad SW TRG to TRGOUT ret = CAEN_DGTZ_WriteRegister(hadle[i], ADDR_ACQUISITION_MODE, RUN_START_ON_TRGIN_RISING_EDGE); // Ru starts with 1st trigger edge ret = CAEN_DGTZ_WriteRegister(hadle[i], ADDR_RUN_DELAY, 4*(1-i)); // Ru Delay decreases with the positio // (to compesate for ru the propagatio delay) break; case INDIVIDUAL_TRIGGER_SIN_TRGOUT: if (i > 0) // Ru starts with S-IN o the 2d board ret = CAEN_DGTZ_WriteRegister(hadle[i], ADDR_ACQUISITION_MODE, RUN_START_ON_SIN_LEVEL); ret = CAEN_DGTZ_WriteRegister(hadle[i], ADDR_GLOBAL_TRG_MASK, 1<<Params.RefChael[i]); // accept oly trg from selected chael ret = CAEN_DGTZ_WriteRegister(hadle[i], ADDR_TRG_OUT_MASK, 0); // o tigger propagatio to TRGOUT ret = CAEN_DGTZ_WriteRegister(hadle[i], ADDR_RUN_DELAY, 2*(1-i)); // Ru Delay decreases with the positio // (to compesate for ru the propagatio delay) // Set TRGOUT=RUN to propagate ru through S-IN => TRGOUT daisy chai ret = CAEN_DGTZ_ReadRegister(hadle[i], ADDR_FRONT_PANEL_IO_SET, &reg); reg = reg & 0xFFF0FFFF 0x ; ret = CAEN_DGTZ_WriteRegister(hadle[i], ADDR_FRONT_PANEL_IO_SET, reg); break; case TRIGGER_ONE2ALL_EXTOR: ret = CAEN_DGTZ_WriteRegister(hadle[i], ADDR_GLOBAL_TRG_MASK, 0x ); // accept ext trg_i (from trg OR) ret = CAEN_DGTZ_WriteRegister(hadle[i],ADDR_TRG_OUT_MASK,0x (1<<Params.RefChael[i])); // propagate auto trg ad SW trg to TRGOUT ret = CAEN_DGTZ_WriteRegister(hadle[i], ADDR_ACQUISITION_MODE, RUN_START_ON_TRGIN_RISING_EDGE); // Arm acquisitio (Ru will start with 1st trigger) ret = CAEN_DGTZ_WriteRegister(hadle[i], ADDR_RUN_DELAY, 0); // Ru Delay = 0 for all break; default: retur -1; break; Sychroizatio setup chose Set start delay to sychroize the digitizers, so that they start the acquisitio at the same time. I our example set start delay = 4 x 16 s for the Master (multiple of the memory clock cycles). Step 25 Compile ad Ru SycTest - Compile SycTest - Lauch SycTest ad press s to start ru - The DeltaT Edge average value is at the order of the samplig clock cycle, 4 s. By pressig t durig the acquisitio is possible to take a look at the sigals i the time frame (see step 26). SycTest corrects for the delay i the Trigger Time Tag. - The DeltaT Time Tag shows a 48 s (a multiple of 16 s, which is trigger time stamp cycle, sice it s sampled at 62.5 MHz). This 48 s delay is ot a issue, the iput trigger sigals just set the waveform widow of the Master ad the Slave at differet times. 18

19 Applicatio Note AN2086 Sychroizatio of CAEN Digitizers i Multiple Board Acquisitio Systems Step 26 Sigal Plot i the Time Referece ( t plot optio) - This plot shows the sigals i the same time frame. The sigals are aliged. - It is possible to see that the DC value of the baselie is ot equal i the two boards, so the sigals will cross the thresholds at differet times. This represet the reaso of the differece i the edge time visible i the figure i the previous Step The program SycTest ca correct for the DC offset ad Step 27 ad Step 28 will explai how to adjust it. Step 27 Set SycTest operatioal parameter i userparam.c source // CHANNEL SETTINGS Params->RefChael[0] = 6; // Chael of the Master used for the acquisitio Params->TriggerThreshold[0] = 2000; // Trigger threshold (for self triggerig) Params->PostTrigger[0] = 50; // Post trigger i percet of the acquisitio widow Params->DCoffset[0] = 0x7c30; // iput DC offset adjust (DAC value) Params->RefChael[1] = 6; // Chael of the Slave used for the acquisitio Params->TriggerThreshold[1] = 2000; // Trigger threshold (for self triggerig) Params->PostTrigger[1] = 50; // Post trigger i percet of the acquisitio widow Params->DCoffset[1] = 0x8000; // iput DC offset adjust (DAC value) // Trigger edge (CAEN_DGTZ_TriggerORisigEdge, CAEN_DGTZ_TriggerOFalligEdge) Params->TriggerEdge = CAEN_DGTZ_TriggerOFalligEdge; Set DC offset Step 28 Compile ad Ru SycTest - Compile SycTest. - Lauch SycTest ad press s to start ru. - Press t : the graphic shows that the DC offset is adjusted. 19

20 Applicatio Note AN2086 Sychroizatio of CAEN Digitizers i Multiple Board Acquisitio Systems Step 29 Trigger Threshold Tuig - SycTest allows to adjust the trigger threshold. - I this example we set the thresholds for DeltaT Edge calculatio to 1750 DC. Step 30 Set SycTest operatioal parameter i userparam.c source // CHANNEL SETTINGS Params->RefChael[0] = 6; // Chael of the Master used for the acquisitio Params->TriggerThreshold[0] = 1750; // Trigger threshold (for self triggerig) Params->PostTrigger[0] = 50; // Post trigger i percet of the acquisitio widow Params->DCoffset[0] = 0x8000; // iput DC offset adjust (DAC value) Params->RefChael[1] = 6; // Chael of the Slave used for the acquisitio Params->TriggerThreshold[1] = 1750; // Trigger threshold (for self triggerig) Params->PostTrigger[1] = 50; // Post trigger i percet of the acquisitio widow Params->DCoffset[1] = 0x8000; // iput DC offset adjust (DAC value) // Trigger edge (CAEN_DGTZ_TriggerORisigEdge, CAEN_DGTZ_TriggerOFalligEdge) Params->TriggerEdge = CAEN_DGTZ_TriggerOFalligEdge; Set thresholds for DeltaT Edge calculatio Step 31 Compile ad Ru SycTest - Compile SycTest. - Lauch SycTest ad press s to start ru. - The DeltaT Edge mea value is sub-aosecod ad, cosiderig the the 4 s samplig clock of the board (V1720), we could say that the boards are sychroized. The sigma is very small ad this meas that there are small variatios of this value. 20

21 DeltaT Edge (ps) CAEN Applicatio Note AN2086 Sychroizatio of CAEN Digitizers i Multiple Board Acquisitio Systems Step 32 Time differece distributio ( H plot optio) - By pressig H durig the acquisitio, the distributio of DeltaT Edge is show. - I case of good sychroizatio, the distace of the distributio average from the time referece should be of the order of the distributio stadard deviatio. Sychroizatio Time Stability The followig Figure 8 shows the DeltaT Edge variatio durig a 1 hour measuremet i a eviromet with o temperature cotrol usig the setup described above. The figure shows the average per secod of the DeltaT Edge i fuctio of the system ru time. The i our setup the digitizers recorded about 7300 evets per secod. It is possible to observe a slight drift of the time differece of about 50 ps, which is of the order of 1% of the samplig cycle Average DeltaT Edge Acquisitio Time (s) Figure 8: DeltaT Edge variatio durig 1 hour measuremet i a ucotrolled eviromet. CAEN 21

22 Applicatio Note AN2086 Sychroizatio of CAEN Digitizers i Multiple Board Acquisitio Systems Example 2: Idepedet Chael Triggers This sectio will describe the sychroizatio of two boards with idepedet chael triggers (logic OR of the chael autotriggers ad idepedet exteral triggers). The aim is to alig the start commad ad the let the boards trigger idepedetly. Triggers wo t be propagated, but the ru start will be propagated through the daisy chai TRG OUT ad the start iput (S IN). The hardware setup is show i Figure 9. The boards are coected as i the follows. - Coect Master CLK OUT to Slave CLK IN usig A317 cable. - Coect the TRG OUT of the Master to S-IN of the Slave. - Coect Fuctio Geerator CH1 output to a 50 Ω passive splitter. - Coect both chaels (#6 i this example) of each digitizer to the splitter with idetical legth cables. Figure 9: Hardware setup. Coectio of boards ad fuctio geerator. The Setup is such that: the daisy chai TRG OUT/S IN propagates the start of the acquisitio; the sigal source comes from the fa out of two of a fuctio geerator, set to each board with cables of equal legth. The start of the evet acquisitio happes i the followig way: the boards are programmed to start whe a sigal is fed i the S IN ad to propagate the S IN iput to the TRG OUT; the SW trigger is propagated through the daisy chai TRG OUT/S IN ad start all the boards; each board triggers by the logic OR of the chael auto-triggers ad the exteral TRG IN. the acquisitio starts sedig a SW trigger to the Master board by clickig s i the SycTest program. Optioal: a HW trigger ca be issued with a timer uit (i.e. CAEN V993) coected to the S-IN of the Master board. The Master board is tured i ru mode with a logic high state ad the data acquisitio stops with the logic low state. I case oe of the boards is i a busy state the acquisitio ca lose the evet aligmet. To veto this possibility a busy sigal ca be propagated to last board (o LVDS I/Os), fed ito veto iput of the Master Board ad propagated to all the boards i daisy chai (o LVDS I/Os) 8 8 New firmware curretly ucer test, ot described i this documet 22

23 Applicatio Note AN2086 Sychroizatio of CAEN Digitizers i Multiple Board Acquisitio Systems As i the previous case there is a delay i the acquisitio start sigal which propagates through the daisy chai from the Master to the Slave. The sketch i Figure 3 represets the issue of the board start timig. The SycTest program should set the correct start delay to sychroize digitizers i case a SW trigger is issued to start the acquisitio. This sets the same time stamp i all digitizers. We ow describe the step ecessary to obtai the sychroizatio of the boards i this hardware cofiguratio. Step 33 Digitizer clock Sychroizatio - Perform the step P1-P17 to sychroize ad alig the clock - Oce clocks are sychroized, it is possible to cofigure the start of acquisitio i order to have the same time referece for both boards. Step 34 Hardware setup (B): Set sigal parameter of fuctio geerator - Set rise time ad fall time= 50 s. - Set width = 300 s. Step 35 Set SycTest operatioal parameter i userparam.c source // *************************************************************************************************** // Start Mode: // *************************************************************************************************** // Optios: START_SW_CONTROLLED, START_HW_CONTROLLED Params->StartMode = START_SW_CONTROLLED; // *************************************************************************************************** propagate this start sigal to the Slave board through the TRG OUT // Syc Mode: S IN daisy chai // *************************************************************************************************** // Optios: COMMONT_EXTERNAL_TRIGGER_TRGIN_TRGOUT, INDIVIDUAL_TRIGGER_SIN_TRGOUT, TRIGGER_ONE2ALL_EXTOR Params->SycMode = INDIVIDUAL_TRIGGER_SIN_TRGOUT; Set Sy Mode accordig to this Sychroizatio setup // CHANNEL SETTINGS Params->RefChael[0] = 6; // Chael of the Master used for the acquisitio Params->TriggerThreshold[0] = 2000; // Trigger threshold (for self triggerig) Params->PostTrigger[0] = 50; // Post trigger i percet of the acquisitio widow Params->DCoffset[0] = 0x8000; // iput DC offset adjust (DAC value) Params->RefChael[1] = 6; // Chael of the Slave used for the acquisitio Params->TriggerThreshold[1] = 2000; // Trigger threshold (for self triggerig) Params->PostTrigger[1] = 50; // Post trigger i percet of the acquisitio widow Params->DCoffset[1] = 0x8000; // iput DC offset adjust (DAC value) // Trigger edge (CAEN_DGTZ_TriggerORisigEdge, CAEN_DGTZ_TriggerOFalligEdge) Params->TriggerEdge = CAEN_DGTZ_TriggerOFalligEdge; Set Start Mode software cotrolled. I this way the Master Board will wait for a software sigal to start the acquisitio ad will // Number of samples i the acquisitio widows Params->RecordLegth = 500; Set acquisitio chael Master ad Slave // Max. distace betwee the trigger time tags i order to cosider a valid coicidece Params->MatchigWidow = 10; // Frot Pael LEMO I/O level (NIM or TTL). Optios: CAEN_DGTZ_IOLevel_NIM, CAEN_DGTZ_IOLevel_TTL Params->IOlevel = CAEN_DGTZ_IOLevel_TTL; Set Frot Pael I/O level 23

24 Applicatio Note AN2086 Sychroizatio of CAEN Digitizers i Multiple Board Acquisitio Systems Step 36 Compile ad Ru SycTest - Compile SycTest - Lauch SycTest ad press s to start ru - Oce the acquisitio is started, the SycTest widow should show some parameter as below Step 37 Syctest acquisitio parameters - You ca fid the descriptio of the acquisitio parameter i Step DeltaT Edge = 32.0 s is about two times the cycle of the trigger time tag (2 x 16 s for the V1720 module). - The firmware allows to add a delay to the start of the acquisitio, so we proceed with the adjustmet of RUN delay parameter i syctest.c source (see Step 41). - The delay is expressed i uit of trigger time tags (16 s for the V1720 module). 24

25 Applicatio Note AN2086 Sychroizatio of CAEN Digitizers i Multiple Board Acquisitio Systems Step 38 it SetSycMode(it hadle[2], UserParams_t Params) { it i, ret=0; uit32_t reg; for(i=0; i<2; i++) { switch (Params.SycMode) { case COMMONT_EXTERNAL_TRIGGER_TRGIN_TRGOUT : if (i == 0) } } retur ret; } Set Syctest operatioal parameter i syctest.c source // ihibit TRGIN o board 0 i order // to avoid start of ru with exteral triggers ret = CAEN_DGTZ_WriteRegister(hadle[i], ADDR_EXT_TRG_INHIBIT, 1); ret = CAEN_DGTZ_WriteRegister(hadle[i], ADDR_GLOBAL_TRG_MASK, 0xC ); // accept EXT TRGIN or SW trg ret = CAEN_DGTZ_WriteRegister(hadle[i], ADDR_TRG_OUT_MASK, 0xC ); // propagate both EXT ad SW TRG to TRGOUT ret = CAEN_DGTZ_WriteRegister(hadle[i], ADDR_ACQUISITION_MODE, RUN_START_ON_TRGIN_RISING_EDGE); // Ru starts with 1st trigger edge ret = CAEN_DGTZ_WriteRegister(hadle[i], ADDR_RUN_DELAY, 4*(1-i)); // Ru Delay decreases with the positio // (to compesate for ru the propagatio delay) break; case INDIVIDUAL_TRIGGER_SIN_TRGOUT: if (i > 0) // Ru starts with S-IN o the 2d board ret = CAEN_DGTZ_WriteRegister(hadle[i], ADDR_ACQUISITION_MODE, RUN_START_ON_SIN_LEVEL); ret = CAEN_DGTZ_WriteRegister(hadle[i], ADDR_GLOBAL_TRG_MASK, 1<<Params.RefChael[i]); // accept oly trg from selected chael ret = CAEN_DGTZ_WriteRegister(hadle[i], ADDR_TRG_OUT_MASK, 0); // o tigger propagatio to TRGOUT ret = CAEN_DGTZ_WriteRegister(hadle[i], ADDR_RUN_DELAY, 2*(1-i)); // Ru Delay decreases with the positio // (to compesate for ru the propagatio delay) // Set TRGOUT=RUN to propagate ru through S-IN => TRGOUT daisy chai ret = CAEN_DGTZ_ReadRegister(hadle[i], ADDR_FRONT_PANEL_IO_SET, &reg); reg = reg & 0xFFF0FFFF 0x ; ret = CAEN_DGTZ_WriteRegister(hadle[i], ADDR_FRONT_PANEL_IO_SET, reg); break; case TRIGGER_ONE2ALL_EXTOR: ret = CAEN_DGTZ_WriteRegister(hadle[i], ADDR_GLOBAL_TRG_MASK, 0x ); // accept ext trg_i (from trg OR) ret = CAEN_DGTZ_WriteRegister(hadle[i],ADDR_TRG_OUT_MASK,0x (1<<Params.RefChael[i])); // propagate auto trg ad SW trg to TRGOUT ret = CAEN_DGTZ_WriteRegister(hadle[i], ADDR_ACQUISITION_MODE, RUN_START_ON_TRGIN_RISING_EDGE); // Arm acquisitio (Ru will start with 1st trigger) ret = CAEN_DGTZ_WriteRegister(hadle[i], ADDR_RUN_DELAY, 0); // Ru Delay = 0 for all break; default: retur -1; break; Sychroizatio setup chose Set start delay to sychroize the digitizers, so that they start the acquisitio at the same time. I our example set start delay = 4 x 16 s for the Master (multiple of the memory clock cycles). Step 39 Compile ad Ru SycTest - Compile SycTest. - Lauch SycTest ad press s to start ru. - The DeltaT Edge mea value is sub-aosecod, so the boards are well sychroized. By pressig t durig the acquisitio is possible to take a look at the sigals. - The DeltaT Time Tag shows a value that is subaosecod ad the average is slightly differet from 0. This result comes from the fact that this time the trigger are ot sychroous, but geerated idepedetly by the two board iput chaels. This ca cause a jitter i the trigger time stamp that ca be see sometimes by clickig p i the SycTest shell. - By pressig H durig the acquisitio the dyamic time distributio of the triggered evets is show. 25

26 Applicatio Note AN2086 Sychroizatio of CAEN Digitizers i Multiple Board Acquisitio Systems Step 40 DC offset tuig - The baselie of the digitizer chaels may differ for several DC values. - You ca adjust the chael offset as explaied i Step 27 ad Step 28. Step 41 Trigger Threshold Tuig - I the SycTest program you ca adjust the thresholds of the chael auto-trigger. - You ca adjust the trigger threshold as explaied i Step 29 ad Step

27 Applicatio Note AN2086 Sychroizatio of CAEN Digitizers i Multiple Board Acquisitio Systems Example 3: Trigger from Exteral Logic Uit This sectio will show how to sychroize the acquisitio of two or more boards whe oe of their chaels satisfies the trigger coditio. This is obtaied through the use of the logic OR of all chaels auto-triggers give as trigger iput to all boards. The hardware setup is show i Figure 10. The boards are coected as i the follows. - Coect Master CLK OUT to Slave CLK IN usig A317 cable. - Coect the TRG OUT of each board to the iput of the CAEN V976 uit with cables of equal legth. - Coect the output of the CAEN V976 uit to the TRG IN of each board with cables of equal legth. - Coect Fuctio Geerator CH1 output to a 50 Ω passive splitter. - Coect both chaels (#6 i this example) of each digitizer to the splitter with cables of equal legth. - Coect the output of the timer uit V993 to the iput of the logic uit CAEN V976 to geerate the HW trigger. The Setup is such that: Figure 9: Hardware setup. Coectio of boards ad fuctio geerator. the TRG OUT of each board is coected with cables of equal legth to the iput of a logic uit (i.e. CAEN V976); the fa out of two of the logic uit output is coected to the TRG IN of each board with cables of equal legth; sigal source comes from the fa out of two of a fuctio geerator ad is set to each board with cables of equal legth. The start of the evet acquisitio happes i the followig way: all boards are armed to start the acquisitio whe a sigal is fed ito TRG IN; all boards are programmed to propagate the chael auto-trigger to the TRG OUT without triggerig the evet acquisitio; all boards are programmed to trigger whe a exteral trigger sigal is received through the TRG IN; a HW trigger ca be issued with a timer uit (CAEN V993 i our case) coected to the exteral logic uit. I this hardware setup the trigger which starts the data acquisitio is propagated to all the boards with the approximately the same time delay. With cables of equal legth the board acquisitio start is ormally sychroous. However the start the ru mode could start asychroously, i particular whe the trigger sigal is close to trigger clock edges. Optioal: a SW trigger ca be issued through the SycTest program as i the previous examples. I this cofiguratio the Master board propagates the SW trigger to the TRG OUT ad gives a logic sigal high as iput i the logic OR. All boards tur i ru mode at the same time whe the output of the logic uit is received i the TRG IN. 27

28 Applicatio Note AN2086 Sychroizatio of CAEN Digitizers i Multiple Board Acquisitio Systems I case oe of the boards is i a busy state the acquisitio ca lose the evet aligmet. To veto this possibility a busy sigal ca be propagated to last board (o LVDS I/Os) ad fed ito veto iput of the Master Board ad propagated to all the boards i daisy chai (o LVDS I/Os) 9 I this example, differetly from the previous oes, it is ot ecessary to set the RUN delay for the sychroizatio betwee digitizers. All digitizers start acquisitio at the same time. We ow describe the step ecessary to obtai the sychroizatio of the boards i this hardware cofiguratio. Step 42 Digitizer clock Sychroizatio - Perform the step P1-P17 to sychroize ad alig the clock - Oce clocks are sychroized ad locked, it s time to Sychroize the start/stop of acquisitio i order to have the same T0 o both the boards. Step 43 Hardware setup (B): Set sigal parameter of fuctio geerator - Set rise time ad fall time= 50 s. - Set width = 300 s. 9 New firmware curretly uder test, ot described i this documet 28