Engr 303 Digital Logic Design Fall 2018
|
|
- Tabitha Glenn
- 5 years ago
- Views:
Transcription
1 Engr 303 Digital Logic Design Fall 2018 LAB 14 Single Cycle Computer You will implement the single cycle computer given in Figure 8-15 of the Chapter 8 handout. Implement these designs, compile, simulate, assign pins, download to hardware and test. Include all the design files and waveforms in your final report. Deliverables: 0) Instruction Memory 1) Single Cycle Computer Demonstration Requirement: Demonstrate Part 1, the final computer executing the given multiplication algorithm on the DE2 board. Part 0 Instruction Memory Implement the Instruction Memory verilog module shown below. This module outputs an instruction on IR bus for each corresponding Address input from the Program Counter (PC). This particular module simulates an assembly language program to perform multiplication. In a real system, such a program would be stored in RAM. Here, we are using verilog to implement the instruction memory as "hard-wired" gates. We would have to recompile the module to run a different "simulated assembly langauge" program. // A simulated assembly language program implemented as a hard-wired circuit. module InstructionMemory ( Address, IR ); input [7:0] Address; output [15:0] IR; reg [15:0] IR; // parameters rename things for readability // this makes it easier to write new programs parameter // See p469 // Register Instructions, Opcode, DR, SA, SB MOVA = 7'b , INC = 7'b , ADD = 7'b , SUB = 7'b , DEC = 7'b , AND = 7'b , OR = 7'b , XOR = 7'b , NOT = 7'b , MOVB = 7'b , SFTR = 7'b , SFTL = 7'b , LOAD = 7'b , ST = 7'b , // Immediate Instructions, Opcode, DR, SA, OP LDI = 7'b , Engineering 303 Lab 14 Folsom Lake College Page 1 of 8
2 ADI = 7'b , // Jump Branch Instructions, Opcode, AD, SA, AD BRZ = 7'b , BRN = 7'b , JMP = 7'b , // Registers R0 = 3'b000, R1 = 3'b001, R2 = 3'b010, R3 = 3'b011, // Numbers ZERO = 3'b000, ONE = 3'b001, TWO = 3'b010, THREE = 3'b011, FOUR = 3'b100, // NULL NULL = 3'b000; // The actual simulated assembly language "program" starts here // This program multiplies two given inputs A * B = P always@(address) begin case(address) 0: IR <= {LOAD, R0, NULL, NULL}; // load A 1: IR <= {LOAD, R1, NULL, NULL}; // load B 2: IR <= {LDI, R2, NULL, ZERO}; // set P to 0 3: IR <= {LDI, R3, NULL, FOUR}; // load jump address // Loop // if A = 0 then branch to done (binary 8) 4: IR <= {BRZ, 3'b001, R0, 3'b000}; 5: IR <= {ADD, R2, R2, R1}; // add B to P 6: IR <= {DEC, R0, R0, NULL}; // decrement A 7: IR <= {JMP, NULL, R3, NULL}; // jump to loop // Done 8: IR <= {ST, NULL, NULL, R2}; // output answer default IR <= 255; endcase end endmodule Waveform Testing. Use Table 8-8 and Figure 8-14 from the Chapter 8 handout to check the instructions. The first few are Load to R0, Load to R1, LoadImmediate the value 0 to R2, LoadImmediate the value 4 to R3... and so forth. You need to check the rest against the instruction memory "program". ENGR303 Engineering 303 Lab 14 Folsom Lake College Page 2 of 8
3 Part 1 Single Cycle Computer Implement the Single Cycle computer design shown at the end of this document. There will be no Data Memory. Instead, connect the signals that would go to the memory module to switches and LEDs instead. These signals will be our primary interface to the system. But we need more signals for testing. Because this is a complex design, we need to pull out some of the internal signals to verify that the system is functioning properly while testing. We call these testing signals "hooks". Pull out the signals using the following pin assignments: Signal Name BusA BusASS BusB BusBSS BusD BusDSS PCout PCoutSS IR K1 K0 MW DataIn ResetN Clock DE2 Connection none 2 seven segment displays HEX1 PIN_AB24,_AA23,_AA24,_Y22,_W21,_V21,_V20 HEX0 PIN_V13,_V14,_AE11,_AD11,_AC12,_AB12,_AF10 None 2 seven segment displays HEX3 PIN_W24,_U22,_Y25,_Y26,_AA26,_AA25,_Y23 HEX2 PIN_Y24,_AB25,_AB26,_AC26,_AC25,_V22,_AB23 None 2 seven segment displays HEX5 PIN_R3,_R4,_R5,_T9,_P7,_P6,_T2 HEX4 PIN_T3,_R6,_R7,_T4,_U2,_U1,_U9 None 2 seven segment displays HEX7 PIN_N9,_P9,_L7,_L6,_L9,_L2,_L3 HEX6 PIN_M4,_M5,_M3,M2,_P3,_P4,_R2 RED LEDs 15:0 _PIN_AE13,_AF13,_AE15,_AD15,_AC14,_AA13,_Y13,_AA14, _AC21, _AD21, _AD23, _AD22, _AC22, _AB21, _AF23, _AE23 GREEN LED 3 - PIN_V18 GREEN LED 2 PIN_W19 GREEN LED 0 PIN_AE22 Toggle switches 7:0 - PIN_C13, _AC13, _AD13, _AF14, _AE14, _P25, _N26, _N25 BLUE button 1 PIN_N23 BLUE button 0 PIN_G26 Waveform Testing 2 x 2 = 4. 2 times 2 is 4. The answer (4) shows up on the B bus and is indicated by MW going high. MS goes high for the STORE operation which would write the answer to Data Memory if we had one. Don't forget to make ResetN high or nothing will happen. The seven seg signals are not helpful for the simulation, but are VERY helpful for running on the DE2 board. Engineering 303 Lab 14 Folsom Lake College Page 3 of 8
4 Engineering 303 Lab 14 Folsom Lake College Page 4 of 8
5 Single Cycle Computer (see detail the following views, as well as Mano text Figures 8-14, 8-15, 8-16) Engineering 303 Lab 14 Folsom Lake College Page 5 of 8
6 Single Cycle Computer Detail 1 Engineering 303 Lab 14 Folsom Lake College Page 6 of 8
7 Single Cycle Computer Detail 2 Engineering 303 Lab 14 Folsom Lake College Page 7 of 8
8 Single Cycle Computer Detail 3 Engineering 303 Lab 14 Folsom Lake College Page 8 of 8
Engineering 303 Digital Logic Design Fall 2018
Engineering 303 Digital Logic Design Fall 2018 LAB 4: Seven Seg, Full Adder, Ripple Adder, Heirarchical Design Build the following designs and verify correct operation. This lab uses hierarchical design.
More informationLAB 4: Seven Seg, Full Adder, Ripple Adder, Heirarchical Design
Engineering 303 Digital Logic Design LAB 4: Seven Seg, Full Adder, Ripple Adder, Heirarchical Design Build the following designs and verify correct operation. This lab uses hierarchical design. Review
More informationChapter 10 Computer Design Basics
Logic and Computer Design Fundamentals Chapter 10 Computer Design Basics Part 2 A Simple Computer Charles Kime & Thomas Kaminski 2004 Pearson Education, Inc. Terms of Use (Hyperlinks are active in View
More informationChapter 9 Computer Design Basics
Logic and Computer Design Fundamentals Chapter 9 Computer Design asics Part 2 A Simple Computer Charles Kime & Thomas Kaminski 2008 Pearson Education, Inc. (Hyperlinks are active in View Show mode) Overview
More information8-1. Fig. 8-1 ASM Chart Elements 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
8-1 Name Binary code IDLE 000 Register operation or output R 0 RUN 0 1 Condition (a) State box (b) Example of state box (c) Decision box IDLE R 0 From decision box 0 1 START Register operation or output
More informationCOSC 122 Computer Fluency. Computer Organization. Dr. Ramon Lawrence University of British Columbia Okanagan
COSC 122 Computer Fluency Computer Organization Dr. Ramon Lawrence University of British Columbia Okanagan ramon.lawrence@ubc.ca Key Points 1) The standard computer (von Neumann) architecture consists
More information8-1. Fig. 8-1 ASM Chart Elements 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
8-1 Name Binary code IDLE 000 Register operation or output R 0 RUN Condition (a) State box (b) Example of state box (c) Decision box IDLE R 0 From decision box START Register operation or output PC 0 (d)
More informationENGR 2031 Digital Design Laboratory Lab 7 Background
ENGR 2031 Digital Design Laboratory Lab 7 Background What we will cover Overview of the Simple Computer (scomp) Architecture Register Flow Diagrams VHDL Implementation of scomp Lab 7 scomp Architecture
More informationCSE 141L Computer Architecture Lab Fall Lecture 3
CSE 141L Computer Architecture Lab Fall 2005 Lecture 3 Pramod V. Argade November 1, 2005 Fall 2005 CSE 141L Course Schedule Lecture # Date Day Lecture Topic Lab Due 1 9/27 Tuesday No Class 2 10/4 Tuesday
More informationLab 3: Standard Combinational Components
Lab 3: Standard Combinational Components Purpose In this lab you will implement several combinational circuits on the DE1 development board to test and verify their operations. Introduction Using a high-level
More informationEECE 340 Introduction to Microprocessors w/lab Section A. Term Project Parking Visitor Counter
Section A Term Project Parking Visitor Counter Group Members: Instructor: Dr. Jinane Biri Due date: Sunday, Dec. 16, 2012 1 Table of Contents 1. Objective... 2 2. Introduction and Problem Description...
More informationDigital Design with FPGAs. By Neeraj Kulkarni
Digital Design with FPGAs By Neeraj Kulkarni Some Basic Electronics Basic Elements: Gates: And, Or, Nor, Nand, Xor.. Memory elements: Flip Flops, Registers.. Techniques to design a circuit using basic
More informationEMT1250 LABORATORY EXPERIMENT. EXPERIMENT # 10: Implementing Binary Adders. Name: Date:
EXPERIMENT # 10: Implementing Binary Adders Name: Date: Equipment/Parts Needed: PC (Altera Quartus II V9.1 installed) DE-2 board Objective: Design a half adder by extracting the Boolean equation from a
More informationENGG3380: Computer Organization and Design Lab5: Microprogrammed Control
ENGG330: Computer Organization and Design Lab5: Microprogrammed Control School of Engineering, University of Guelph Winter 201 1 Objectives: The objectives of this lab are to: Start Date: Week #5 201 Due
More informationEE 231 Fall EE 231 Lab 3
EE 231 Lab 3 Decoders and Multiplexers Decoders and multiplexers are important combinational circuits in many logic designs. Decoders convert n inputs to a maximum of unique 2 n outputs. A special case
More informationREGISTER TRANSFER LANGUAGE
REGISTER TRANSFER LANGUAGE The operations executed on the data stored in the registers are called micro operations. Classifications of micro operations Register transfer micro operations Arithmetic micro
More informationComputer architecture Assignment 3
Computer architecture Assignment 3 1- An instruction at address 14E in the basic computer has I=0, an operation code of the AND instruction, and an address part equal to 109(all numbers are in hexadecimal).
More informationTESTING ON THE DE2 BOARD
TESTING ON THE DE2 BOARD September 18 th, 2007 CSC343 Fall 2007 Prepared by: Steven Medina PURPOSE The DE2 board is a programmable board with an FPGA chip attached. FPGA stands for Field Programmable Gate
More informationPSIM: Processor SIMulator (version 4.2)
PSIM: Processor SIMulator (version 4.2) by Charles E. Stroud, Professor Dept. of Electrical & Computer Engineering Auburn University July 23, 2003 ABSTRACT A simulator for a basic stored program computer
More informationChapter 3 : Control Unit
3.1 Control Memory Chapter 3 Control Unit The function of the control unit in a digital computer is to initiate sequences of microoperations. When the control signals are generated by hardware using conventional
More informationLaboratory Exercise 3
Laboratory Exercise 3 Latches, Flip-flops, and egisters The purpose of this exercise is to investigate latches, flip-flops, and registers. Part I Altera FPGAs include flip-flops that are available for
More informationASSIGNMENT ECE514 (COMPUTER ORGANIZATION) ASSIGNMENT NO. 3
ASSIGNMENT ECE514 (COMPUTER ORGANIZATION) ASSIGNMENT NO. 3 This is an individual assignment for ECE514. It carries a mark of 10%. The rubric of marks is given in Appendix 3. This assignment is about designing
More informationMICROPROGRAMMED CONTROL
MICROPROGRAMMED CONTROL Hardwired Control Unit: When the control signals are generated by hardware using conventional logic design techniques, the control unit is said to be hardwired. Micro programmed
More informationPRELAB! Read the entire lab, and complete the prelab questions (Q1-Q3) on the answer sheet before coming to the laboratory.
PRELAB! Read the entire lab, and complete the prelab questions (Q1-Q3) on the answer sheet before coming to the laboratory. 1.0 Objectives In the last lab we learned that Verilog is a fast and easy way
More informationCSE140: Components and Design Techniques for Digital Systems
CSE4: Components and Design Techniques for Digital Systems Tajana Simunic Rosing Announcements and Outline Check webct grades, make sure everything is there and is correct Pick up graded d homework at
More informationLab 4: Register File and Memory 50 points Instructor: Yifeng Zhu Due: One week
Objectives: Lab 4: Register File and Memory 50 points Instructor: Yifeng Zhu Due: One week Build Register File Build Instruction Memory and Data Memory 1. Overview A combinational circuit neither contains
More informationDatasheet for Nios II Processor (nios2_r1c) v.3, July Processor Details GENERATION SYSID
Processor Details NAME "cpu_r1" FREQ 50000000 RESET_ADDR 0x0 EXCEPTION_ADDR 0x20 IMPLEMENTATION "small" ARCHITECTURE "altera_nios2" Instruction cache Data cache Little Endian HARDWARE_DIVIDE_PRESENT HARDWARE_MULTIPLY_PRESENT
More informationQUARTUS II Altera Corporation
QUARTUS II Quartus II Design Flow Design Entry Timing Constraints Synthesis Placement and Routing Timing, Area, Power Optimization Timing and Power Analyzer Optimized Design 2 Can I still use a Processor?
More informationECE241 - Digital Systems. University of Toronto. Lab #2 - Fall Introduction Computer-Aided Design Software, the DE2 Board and Simple Logic
ECE24 - Digital Sstems Universit of Toronto Lab #2 - Fall 28 Introduction Computer-Aided Design Software, the DE2 Board and Simple Logic. Introduction The purpose of this eercise is to introduce ou to
More informationLaboratory Exercise 1
Laboratory Exercise 1 Switches, Lights, and Multiplexers The purpose of this exercise is to learn how to connect simple input and output devices to an FPGA chip and implement a circuit that uses these
More informationOne and a half hours. Section A is COMPULSORY UNIVERSITY OF MANCHESTER SCHOOL OF COMPUTER SCIENCE
COMP 12111 One and a half hours Section A is COMPULSORY UNIVERSITY OF MANCHESTER SCHOOL OF COMPUTER SCIENCE Fundamentals of Computer Engineering Date: Monday 23rd January 2017 Time: 09:45-11:15 Answer
More informationDepartment of Computer and Mathematical Sciences. Lab 4: Introduction to MARIE
Department of Computer and Mathematical Sciences CS 3401 Assembly Language 4 Lab 4: Introduction to MARIE Objectives: The main objective of this lab is to get you familiarized with MARIE a simple computer
More informationLaboratory Exercise 7
Laboratory Exercise 7 Finite State Machines This is an exercise in using finite state machines. Part I We wish to implement a finite state machine (FSM) that recognizes two specific sequences of applied
More informationComputer Architecture 2/26/01 Lecture #
Computer Architecture 2/26/01 Lecture #9 16.070 On a previous lecture, we discussed the software development process and in particular, the development of a software architecture Recall the output of the
More informationHardware Description Languages (HDLs) Verilog
Hardware Description Languages (HDLs) Verilog Material from Mano & Ciletti book By Kurtulus KULLU Ankara University What are HDLs? A Hardware Description Language resembles a programming language specifically
More informationTABLE 8-1. Control Signals for Binary Multiplier. Load. MUL0 Q 0 CAQ sr CAQ. Shift_dec. C out. Load LOADQ. CAQ sr CAQ. Shift_dec P P 1.
T-192 Control Signals for Binary Multiplier TABLE 8-1 Control Signals for Binary Multiplier Block Diagram Module Microoperation Control Signal Name Control Expression Register A: A 0 Initialize IDLE G
More informationCPEN 230L: Introduction to Digital Logic Laboratory Lab 7: Multiplexers, Decoders, and Seven Segment Displays
CPEN 230L: Introduction to Digital Logic Laboratory Lab 7: Multiplexers, Decoders, and Seven Segment Displays Purpose Learn about multiplexers (MUXs), decoders and seven segment displays. Learn about hierarchical
More informationAssembly Language Programming of 8085
Assembly Language Programming of 8085 Topics 1. Introduction 2. Programming model of 8085 3. Instruction set of 8085 4. Example Programs 5. Addressing modes of 8085 6. Instruction & Data Formats of 8085
More informationCS 2461: Computer Architecture I
Computer Architecture is... CS 2461: Computer Architecture I Instructor: Prof. Bhagi Narahari Dept. of Computer Science Course URL: www.seas.gwu.edu/~bhagiweb/cs2461/ Instruction Set Architecture Organization
More informationComputer Logic II CCE 2010
Computer Logic II CCE 2010 Dr. Owen Casha Computer Logic II 1 The Processing Unit Computer Logic II 2 The Processing Unit In its simplest form, a computer has one unit that executes program instructions.
More informationUniversity of Hawaii EE 361L. Getting Started with Spartan 3E Digilent Basys2 Board. Lab 4.1
University of Hawaii EE 361L Getting Started with Spartan 3E Digilent Basys2 Board Lab 4.1 I. Test Basys2 Board Attach the Basys2 board to the PC or laptop with the USB connector. Make sure the blue jumper
More informationSCRAM Introduction. Philipp Koehn. 19 February 2018
SCRAM Introduction Philipp Koehn 19 February 2018 This eek 1 Fully work through a computer circuit assembly code Simple but Complete Random Access Machine (SCRAM) every instruction is 8 bit 4 bit for op-code:
More informationUnit II Basic Computer Organization
1. Define the term. Internal Organization-The internal organization of a digital system is defined by the sequence of microoperations it performs on data stored in its registers. Program- A program is
More informationCS222: Processor Design
CS222: Processor Design Dr. A. Sahu Dept of Comp. Sc. & Engg. Indian Institute of Technology Guwahati Processor Design building blocks Outline A simple implementation: Single Cycle Data pathandcontrol
More informationLC-3 Instruction Processing
LC-3 Instruction Processing (Textbookʼs Chapter 4)# Next set of Slides:# Textbook Chapter 10-10.2# Instruction Processing# It is impossible to do all of an instruction in one clock cycle.# Processors break
More informationVerilog Hardware Description Language ROOM: B405
Verilog Hardware Description Language HONG@IS.NAIST.JP ROOM: B405 Content Lecture 1: Computer organization and performance evaluation metrics Lecture 2: Processor architecture and memory system Lecture
More information16.1. Unit 16. Computer Organization Design of a Simple Processor
6. Unit 6 Computer Organization Design of a Simple Processor HW SW 6.2 You Can Do That Cloud & Distributed Computing (CyberPhysical, Databases, Data Mining,etc.) Applications (AI, Robotics, Graphics, Mobile)
More informationEE431 April 6, 2009 Midterm Material on Assignments 6 to 10
EE431 April 6, 2009 midterm 1 EE431 April 6, 2009 Midterm Material on Assignments 6 to 10 Date: Monday April 6, 2009 Time = 2 hours Text Books, Notes and Computer Files Only NO CELL PHONES or LAPTOPS Preamble
More informationAdvanced Computer Architecture
Advanced Computer Architecture Lecture No. 22 Reading Material Vincent P. Heuring&Harry F. Jordan Chapter 5 Computer Systems Design and Architecture 5.3 Summary Microprogramming Working of a General Microcoded
More informationDigital Systems Laboratory
2014 Fall CSE140L Digital Systems Laboratory Lecture #8910 by Dr. Choon Kim CSE Department, UCSD Lecture #9 1 Practical Sequential Logic Design (Small computer/cpu example) LAB4_tinycpu.pdf Lecture #9
More informationDigital Circuit Design and Language. Datapath Design. Chang, Ik Joon Kyunghee University
Digital Circuit Design and Language Datapath Design Chang, Ik Joon Kyunghee University Typical Synchronous Design + Control Section : Finite State Machine + Data Section: Adder, Multiplier, Shift Register
More informationModule 5 - CPU Design
Module 5 - CPU Design Lecture 1 - Introduction to CPU The operation or task that must perform by CPU is: Fetch Instruction: The CPU reads an instruction from memory. Interpret Instruction: The instruction
More informationBlog - https://anilkumarprathipati.wordpress.com/
Control Memory 1. Introduction The function of the control unit in a digital computer is to initiate sequences of microoperations. When the control signals are generated by hardware using conventional
More informationproblem maximum score 1 10pts 2 8pts 3 10pts 4 12pts 5 7pts 6 7pts 7 7pts 8 17pts 9 22pts total 100pts
University of California at Berkeley College of Engineering epartment of Electrical Engineering and Computer Sciences EECS150 J. Wawrzynek Spring 2003 2/21/03 Exam I Solutions Name: I number: This is a
More informationIn this lecture, we will focus on two very important digital building blocks: counters which can either count events or keep time information, and
In this lecture, we will focus on two very important digital building blocks: counters which can either count events or keep time information, and shift registers, which is most useful in conversion between
More informationRyerson Polytechnic University Department of Electrical Engineering COE328 Digital Systems. (2 Weeks) FORMAL REPORT - 30 Marks Due Date: Week 13
Ryerson Polytechnic University Department of Electrical Engineering COE328 Digital Systems Lab 7 - Programmable Processor Module - PPM (2 Weeks) FORMAL REPORT - 3 Marks Due Date: Week 3 Objectives: To
More informationENEE245 Digital Circuits and Systems Lab Manual
ENEE245 Digital Circuits and Systems Lab Manual Department of Engineering, Physical & Computer Sciences Montgomery College Version 1.1 Copyright Prof. Lan Xiang (Do not distribute without permission) 1
More informationAsynchronous FIFO Design
Asynchronous FIFO Design 2.1 Introduction: An Asynchronous FIFO Design refers to a FIFO Design where in the data values are written to the FIFO memory from one clock domain and the data values are read
More informationENEE245 Digital Circuits and Systems Lab Manual
ENEE245 Digital Circuits and Systems Lab Manual Department of Engineering, Physical & Computer Sciences Montgomery College Modified Fall 2017 Copyright Prof. Lan Xiang (Do not distribute without permission)
More informationDIGITAL SYSTEM DESIGN
DIGITAL SYSTEM DESIGN Prepared By: Engr. Yousaf Hameed Lab Engineer BASIC ELECTRICAL & DIGITAL SYSTEMS LAB DEPARTMENT OF ELECTRICAL ENGINEERING Digital System Design 1 Name: Registration No: Roll No: Semester:
More informationUniversity of California, Davis Department of Electrical and Computer Engineering. Lab 1: Implementing Combinational Logic in the MAX10 FPGA
1 University of California, Davis Department of Electrical and Computer Engineering EEC180B DIGITAL SYSTEMS II Winter Quarter 2018 Lab 1: Implementing Combinational Logic in the MAX10 FPGA Objective: This
More informationFPGA Design Challenge :Techkriti 14 Digital Design using Verilog Part 1
FPGA Design Challenge :Techkriti 14 Digital Design using Verilog Part 1 Anurag Dwivedi Digital Design : Bottom Up Approach Basic Block - Gates Digital Design : Bottom Up Approach Gates -> Flip Flops Digital
More informationCS 31: Intro to Systems Digital Logic. Kevin Webb Swarthmore College February 2, 2016
CS 31: Intro to Systems Digital Logic Kevin Webb Swarthmore College February 2, 2016 Reading Quiz Today Hardware basics Machine memory models Digital signals Logic gates Circuits: Borrow some paper if
More informationAppendix C: DE2 Pin Assignments
Appendix C: DE2 Pin Assignments The most commonly used DE2 pin assignments are given in tables that follow, both for the standard DE2 board (with the EP2C35 FPGA) and the DE2-70 (with the EP2C70 FPGA).
More informationECE 473 Computer Architecture and Organization Project: Design of a Five Stage Pipelined MIPS-like Processor Project Team TWO Objectives
ECE 473 Computer Architecture and Organization Project: Design of a Five Stage Pipelined MIPS-like Processor Due: December 8, 2011 Instructor: Dr. Yifeng Zhu Project Team This is a team project. All teams
More informationLC-3 Instruction Processing. (Textbook s Chapter 4)
LC-3 Instruction Processing (Textbook s Chapter 4) Instruction Processing Fetch instruction from memory Decode instruction Evaluate address Fetch operands from memory Usually combine Execute operation
More informationIts Assembly language programming
8085 Architecture & Its Assembly language programming Dr A Sahu Dept of Computer Science & Engineering IIT Guwahati 8085 Era and Features 8085 Outline Block diagram (Data Path) Bus Structure Register Structure
More informationLab 2 EECE473 Computer Organization & Architecture University of Maine
Lab 2: Verilog Programming Instructor: Yifeng Zhu 50 Points Objectives: 1. Quatus II Programming assignment: PIN assignments, LEDs, switches; 2. Download and test the design on Altera DE2 board 3. Create
More informationCPU. Fall 2003 CSE 207 Digital Design Project #4 R0 R1 R2 R3 R4 R5 R6 R7 PC STATUS IR. Control Logic RAM MAR MDR. Internal Processor Bus
http://www.engr.uconn.edu/~barry/cse207/fa03/project4.pdf Page 1 of 16 Fall 2003 CSE 207 Digital Design Project #4 Background Microprocessors are increasingly common in every day devices. Desktop computers
More informationLab 2: Introduction to Verilog HDL and Quartus
Lab 2: Introduction to Verilog HDL and Quartus September 16, 2008 In the previous lab you designed simple circuits using discrete chips. In this lab you will do the same but by programming the CPLD. At
More informationPractical Malware Analysis
Practical Malware Analysis Ch 4: A Crash Course in x86 Disassembly Revised 1-16-7 Basic Techniques Basic static analysis Looks at malware from the outside Basic dynamic analysis Only shows you how the
More informationLC-3 Instruction Set Architecture. Textbook Chapter 5
LC-3 Instruction Set Architecture Textbook Chapter 5 Instruction set architecture What is an instruction set architecture (ISA)? It is all of the programmer-visible components and operations of the computer
More informationLaboratory. Low-Level. Languages. Objective. References. Study simple machine language and assembly language programs.
Laboratory Low-Level 7 Languages Objective Study simple machine language and assembly language programs. References Software needed: 1) A web browser (Internet Explorer or Netscape) 2) Applet from the
More informationInstruction Sets: Characteristics and Functions Addressing Modes
Instruction Sets: Characteristics and Functions Addressing Modes Chapters 10 and 11, William Stallings Computer Organization and Architecture 7 th Edition What is an Instruction Set? The complete collection
More informationRelease 0.8. Multi-Purpose Light Unit Technical Reference Manual
Release 0.8 Multi-Purpose Light Unit Technical Reference Manual INTRODUCTION Introduction The Multi-Purpose Light unit is a multi-function DCC decoder that supports the following: DCC Characteristics 14
More informationTutorial 2 Implementing Circuits in Altera Devices
Appendix C Tutorial 2 Implementing Circuits in Altera Devices In this tutorial we describe how to use the physical design tools in Quartus II. In addition to the modules used in Tutorial 1, the following
More informationComputer Architecture Programming the Basic Computer
4. The Execution of the EXCHANGE Instruction The EXCHANGE routine reads the operand from the effective address and places it in DR. The contents of DR and AC are interchanged in the third microinstruction.
More informationLaboratory Exercise 9
Laboratory Exercise 9 Figure 1 shows a digital system that contains a number of -bit registers, a multiplexer, an adder/subtracter unit, a counter, and a control unit. Data is input to this system via
More informationFinal Exam Review. b) Using only algebra, prove or disprove the following:
EE 254 Final Exam Review 1. The final exam is open book and open notes. It will be made up of problems similar to those on the previous 3 hour exams. For review, be sure that you can work all of the problems
More informationCSCE 312 Lab manual. Instructor: Dr. Ki HwanYum. Prepared by. Dr. Rabi Mahapatra. Suneil Mohan & Amitava Biswas. Fall 2016
CSCE 312 Lab manual Lab-3 - Sequential logic design Instructor: Dr. Ki HwanYum Prepared by Dr. Rabi Mahapatra. Suneil Mohan & Amitava Biswas Fall 2016 Department of Computer Science & Engineering Texas
More informationCS 61C: Great Ideas in Computer Architecture. MIPS CPU Datapath, Control Introduction
CS 61C: Great Ideas in Computer Architecture MIPS CPU Datapath, Control Introduction Instructor: Alan Christopher 7/28/214 Summer 214 -- Lecture #2 1 Review of Last Lecture Critical path constrains clock
More informationAssembly Language Programming of 8085
Assembly Language Programming of 8085 1. Introduction A microprocessor executes instructions given by the user Instructions should be in a language known to the microprocessor Microprocessor understands
More informationEngin 100 (section 250), Winter 2015, Technical Lecture 3 Page 1 of 5. Use pencil!
Engin 100 (section 250), Winter 2015, Technical Lecture 3 Page 1 of 5 Use pencil! Last time Introduced basic logic and some terms including bus, word, register and combinational logic. Talked about schematic
More informationVLIW Digital Signal Processor. Michael Chang. Alison Chen. Candace Hobson. Bill Hodges
VLIW Digital Signal Processor Michael Chang. Alison Chen. Candace Hobson. Bill Hodges Introduction Functionality ISA Implementation Functional blocks Circuit analysis Testing Off Chip Memory Status Things
More informationACS College of Engineering. Department of Biomedical Engineering. Logic Design Lab pre lab questions ( ) Cycle-1
ACS College of Engineering Department of Biomedical Engineering Logic Design Lab pre lab questions (2015-2016) Cycle-1 1. What is a combinational circuit? 2. What are the various methods of simplifying
More informationLecture 12: Single-Cycle Control Unit. Spring 2018 Jason Tang
Lecture 12: Single-Cycle Control Unit Spring 2018 Jason Tang 1 Topics Control unit design Single cycle processor Control unit circuit implementation 2 Computer Organization Computer Processor Memory Devices
More informationAdvanced Electronics Lab.
College of Engineering Course Book of 2010-2011 Advanced Electronics Lab. Mr. Araz Sabir Ameen M.Sc. in Electronics & Communications ALTERA DE2 Development and Education Board DE2 Package: The DE2 package
More informationCSE 378 Midterm Sample Solution 2/11/11
Question 1. (9 points). Suppose we have the following MIPS instructions stored in memory starting at location 0x2400. 2400: add $v0,$t1,$t3 2404: loop: sll $t3,$a2,12 2408: or $s2,$t3,$a1 240c: bne $s2,$t8,loop
More informationDigital Systems Laboratory
2014 Spring CSE140L Digital Systems Laboratory Lecture #7, 8, 9 by Dr. Choon Kim CSE Department, UCSD Lecture #7,8,9 1 A Practical FSM Example: Small(Tiny) Computer System Design LAB4_tinycpu.pdf Lecture
More informationThe LC-3 Instruction Set Architecture. ISA Overview Operate instructions Data Movement instructions Control Instructions LC-3 data path
Chapter 5 The LC-3 Instruction Set Architecture ISA Overview Operate instructions Data Movement instructions Control Instructions LC-3 data path A specific ISA: The LC-3 We have: Reviewed data encoding
More informationThe Itanium Bit Microprocessor Report
The Itanium - 1986 8 Bit Microprocessor Report By PRIYANK JAIN (02010123) Group # 11 Under guidance of Dr. J. K. Deka & Dr. S. B. Nair Department of Computer Science & Engineering Indian Institute of Technology,
More informationEXPERIMENT NO. 1 THE MKT 8085 MICROPROCESSOR TRAINER
OBJECT: EXPERIMENT NO. 1 THE MKT 8085 MICROPROCESSOR TRAINER To understand the structure and operating instruction of the microprocessor trainer. INTRODUCTION: The MKT 8085 is a single-board microcomputer,
More informationEE 231 Fall EE 231 Lab 3. Decoders and Multiplexers. Figure 1: 7-Segment Display. Memory: where the program is stored.
EE 231 Lab 3 Decoders and Multiplexers Decoders and multiplexers are important combinational circuits in many logic designs. Decoders convert n inputs to a maximum of unique 2 n outputs. A special case
More information9/25/ Software & Hardware Architecture
8086 Software & Hardware Architecture 1 INTRODUCTION It is a multipurpose programmable clock drive register based integrated electronic device, that reads binary instructions from a storage device called
More informationCPE 200L LABORATORY 4: INTRODUCTION TO DE2 BOARD UNIVERSITY OF NEVADA, LAS VEGAS GOALS: BACKGROUND:
CPE 200L LABORATORY 4: INTRODUCTION TO DE2 BOARD DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING UNIVERSITY OF NEVADA, LAS VEGAS GOALS: Getting familiar with DE2 board installation, properties, usage.
More informationProblem Points Your Points Total 80
Grades: 20% of the final grade. CDA 3103 Computer Organization Exam 2 Solution Set Name: USF ID: Problem Points Your Points 1 10 2 10 3 20 4 10 5 15 6 15 Total 80 Exam Rules Close book, notes and HW. Only
More informationCISC 662 Graduate Computer Architecture. Lecture 4 - ISA MIPS ISA. In a CPU. (vonneumann) Processor Organization
CISC 662 Graduate Computer Architecture Lecture 4 - ISA MIPS ISA Michela Taufer http://www.cis.udel.edu/~taufer/courses Powerpoint Lecture Notes from John Hennessy and David Patterson s: Computer Architecture,
More informationDigital Systems Laboratory
2012 Fall CSE140L Digital Systems Laboratory by Dr. Choon Kim CSE Department UCSD 1 Welcome to CSE140L! 2 3-way Light Controller, 2-1 MUX, Majority Detector, 7- seg Display, Binary-to- Decimal converter.
More informationEN2911X: Reconfigurable Computing Lecture 05: Verilog (2)
EN2911X: Lecture 05: Verilog (2) Prof. Sherief Reda Division of Engineering, Brown University Fall 09 http://scale.engin.brown.edu Dataflow modeling Module is designed by specifying the data flow, where
More information