Digital Design using HDLs EE 4755 Final Examination

Transcription

1 Name Digital Design using HDLs EE 4755 Final Examination Thursday, 8 December 26 2:3-4:3 CST Alias Problem Problem 2 Problem 3 Problem 4 Problem 5 Problem 6 Exam Total (3 pts) (2 pts) (5 pts) (5 pts) ( pts) ( pts) ( pts) Good Luck!

2 Problem : [3 pts] The diagram and Verilog code belo sho incomplete versions of module prob_seq. This module is to operate something like mag_seq from Homeork 6. When start is at a positive clock edge the module ill set ready to and start computing v*v v*v v*v, here v and v are each IEEE 754 FP single values. The module ill set ready to at the first positive edge after the result is ready. Complete the Verilog code so that the module orks as indicated and is consistent ith the diagram. It is okay to change declarations from, say, logic to uire. But the synthesized hardare cannot change hat is already on the diagram, for example, don t remove a register such as ac and don t insert any ne registers in existing ires, such as those beteen the multiplier inputs and the multiplexors. Don t modify this diagram, rite Verilog code. start prob_seq ready v m CW_fp_mult ac a CW_fp_add result v rnd rnd clk 32'd ac Don t modify this diagram, rite Verilog code. module prob_seq( output uire [3:] result, input uire [3:] v, v, output uire ready, input uire start, clk); uire [7:] mul_s, add_s; uire [3:] mul_a, mul_b; uire [3:] add_a, add_b; uire [3:] prod, ; logic [3:] ac, ac; logic [2:] step; localparam int last_step = ; posedge clk ) if ( start ) step = ; else if ( step last_step ) step = step ; CW_fp_mult ѽ(.a( mul_a ),.b( mul_b ),.rnd(3 d),.z( prod ),.status(mul_s)); CW_fp_add ½(.a( add_a ),.b( add_b ),.rnd(3 d),.z( ),.status(add_s)); assign ready = step == last_step; /// THIS MUST BE CHANGED. /// ÍË Æ Ì È ÇÊ ËÇÄÍÌÁÇÆ endmodule 2

3 Problem, continued: Solution on this page. Complete Verilog so that module computes v*v v*v v*v. Synthesized hardare must be consistent ith diagram, especially synthesized registers. Note that ready must come from a register. Don t skip the easy part: connections to adder. start v v clk Don t modify, Verilog only. prob_seq m CW_fp_mult rnd 32'd ac ac a CW_fp_add rnd ready result module prob_seq( output uire [3:] result, output uire ready, input uire [3:] v, v, input uire start, clk); uire [7:] mul_s, add_s; uire [3:] mul_a, mul_b; uire [3:] add_a, add_b; uire [3:] prod, ; logic [3:] ac, ac; logic [2:] step; localparam int last_step = ; // MUST BE CHANGED. posedge clk ) if ( start ) step = ; else if ( step last_step ) step = step ; CW_fp_mult ѽ(.a( mul_a ),.b( mul_b ),.rnd(3 d),.z( prod ),.status(mul_s)); CW_fp_add ½(.a( add_a ),.b( add_b ),.rnd(3 d),.z( ),.status(add_s)); assign ready = step == last_step; // MUST BE CHANGED. endmodule 3

4 Problem 2: [2 pts] Analyze the timing of the to similar modules on the next page using the timing model used in class, as requested in the subproblems. Ase that all adders are synthesized as a ripple connection of binary full adders and that the comparison units are also based on ripple hardare. (a) Before analyzing the modules, sho the delay of each of the components listed belo using the simple model given in class. For this part ase that all inputs are available at t =. Delay for BFA is: Explain or sho diagram. Delay for a -bit adder is: Explain or sho diagram. Delay for a -bit (less than) comparison unit is: Explain or sho diagram. Delay for a -bit, n-input multiplexor is: Explain or sho diagram. 4

5 Problem 2, continued: (b) Find the length of critical path in the to modules belo using the timings above. Where applicable make the reasonable asption that a ripple adder can start hen its loer bits arrive, not hen all bits of its input are stable. limit greedy_fit limit fcfs_ t a a[] a[] a[2] a[3] a a[] a[] a[2] a[3] Length of critical path for greedy fit in terms of. Sho ork for partial credit. Length of critical path for fcfs fit in terms of. Sho ork for partial credit. 5

6 Problem 3: [5 pts] Complete the Verilog code so that it corresponds to the module shon. limit fcfs_fit Complete module. module fcfs_fit #( int nelts = 4, int = 6 ) ( output logic [-:], input uire [-:] a[nelts], limit ); alays begin // FINISH ALWAYS STATEMENT a a[] a[] a[2] a[3] for ( int i=; inelts; i ) begin end end endmodule 6

7 Problem 4: [5 pts] Appearing to the right is fcfs_cfit, a version of the fcfs_fit module in hich the a input has been changed to a parameter, meaning that a is an elaboration-time constant. Compute the cost of this module using the simple model used in class and accounting for optimization based on the constant values. As in an earlier problem, adders and comparision units are ripple-style. Cost of the a[] comparison unit. Explain. Cost of the a[] adder. Explain. limit 6h'4755 6h'472 6h'3755 6h'274 a[] a[] a[2] a[3] fcfs_cfit n=4, =6, a= Cost of the a[] multiplexor. Explain. Cost of the a[2] multiplexor. Explain. Total cost. 7

8 Problem 5: [ pts] Anser each question belo. (a) A time slot in the Verilog event queue contains many regions, among them active, inactive, and NBA. Explain ho an event gets put in each region. (You can use the next subproblem for examples.) An event is put into the active region hen: An event is put into the inactive region hen: An event is put into the NBA region hen: (b) In the code fragment belo sho the order in hich the statements are executed after the posedge clk. Identify a statement by the value that is assigned. The first to statements executed are a and b, that s shon. (Since a is a nonblocking assignment, the execution of a only means that a as computed, it doesn t mean that a as changed.) Complete the Order of statements list. module regions; posedge clk ) begin a = a ; b = b ; end alays_comb s = a b; alays_comb ax = a 2; alays_comb ay = ax 5; alays_comb by = bx 4; alays_comb bx = b 3; endmodule Order of statements: a, b, 8

9 Problem 6: [ pts] Appearing belo is the pipelined mag module from Homeork 6. (a) Suppose it turns out that the multiply (CW_fp_mult) takes tice as long as the add (CW_fp_add). Based on this fact, modify the pipeline to reduce cost, but ithout affecting clock frequency. Dra in your changes, there s no need to rite Verilog. Also, comment on latency and throughput changes. Modify for loer cost based on faster adder. Does the change help throughput? Does it help latency? mag 32 [] C [][] a [2] v 32 [] C [][] a2 [3] mag 2 32 [2] C [][2] [2][2] Stage Stage Stage 2 (b) Suppose that the v input arrives very early in the clock cycle. Based on this modify the pipeline to reduce cost. Modify for early-arriving v. mag 32 [] [][] a [2] v 32 [] [][] a2 [3] mag 2 32 [2] [][2] [2][2] clk Stage Stage Stage 2 9