Basic Concepts. Lexical Conventions

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1 Basic Cncepts Lexica Cnventins basic exica cnventins are simiar t C prgramming anguage tkens: cmment, deimiter, number, string, identifier, keywrd case-sensitive anguage keywrds are in wercase Basic Lexica 1. white space 2. cmment 3. peratr 4. number specificatin 5. string 6. identifiers 7. keywrd 8. escaped identifier

2 Lexica Cnventins bank spaces (\b) tabs (\t) newines (\n) white space pace anywhere [ignre] separate tken [nt ignre] pace in string [nt ignre] (bank space) mdue rippe_carry_cunter(q, ck, reset); utput [3:0] q; input ck, rst; (tab) T_FF tff0(q[0],ck, rst); T_FF tff1(q[1],q[0], rst); (new ine) T_FF tff2(q[2],q[1], rst); T_FF tff3(q[3],q[2], rst); mdue Lexica Cnventins Cmment ne-ine mutipe-ine Operatr type unary binary ternary // /* */ #. perand a = b && c; // This is a ne-ine cmment /* This is a mutipe ine cmment */ /* This is /* an iega */ cmment */ /* This is //a ega cmment */ exampe a = ~b; a = b && c; a = b? c : d;

Lexica Cnventins Number type bit width exampe sized imited 5 d23 un-sized un-imited 23 10111 binary <size> '<base frmat> <number>. Binary ('b r 'B) Decima ('d r 'D), Octa (' r 'O).

3 Lexica Cnventins Number type bit width exampe sized imited 5 d23 un-sized un-imited binary <size> '<base frmat> <number>. Binary ('b r 'B) Decima ('d r 'D), Octa (' r 'O). Hexade ('h r 'H), 4'b1111 // This is a 4-bit binary number 12'habc // This is a 12-bit hexadecima number 16'd255 // This is a 16-bit decima number // This is a 32-bit decima number by defaut 'hc3 // This is a 32-bit hexadecima number '21 // This is a 32-bit cta number Lexica Cnventins Number System Binary Octa Decima Hexadecima aw vaue 0, 1 (ne-bit) 0, 1, 2, 3, 4, 5, 6, 7 (three-bit) 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, a, b, c, d, e, f (fur-bit) unknwn x high impedance z 12 h13x 6 hx 32 hz 10 dc 0001_0011_xxxx xx_xxxx zzzz_zzzz_..._zzzz un-avaiabe 5 d2 6 hf 32 h7?_??10 0_0010??_ _1111????_????_..._ _0000_..._0111

4 Lexica Cnventins negative numbers -8'd3 1111_1101 (2 s) 4'd-2 Iega underscre 12'b 'b1111_0000_ bit fr 2 s f inverse pus readabiity questin marks 4'b10?? = 4'b10zz String Lexica Cnventins A string is a sequence f characters that are encsed by dube qutes. "He Verig Wrd" "a / b" String must be cntained n a singe ine Strings are treated as a sequence f ne-byte ASCII vaues One-byte = Eight-bit "He Verig Wrd" "a / b" 19 bytes 5 bytes

5 Lexica Cnventins Keywrd The specia identifier reserved t define the anguage cnstructs. Keywrds are in wercase the name f bjects aphanumeric characters, the underscre ( _ ), r the dar sign ( $ ) Identifiers are case sensitive wx123 _kkx5x 22x87y $xxxxx ega naming stye iega naming stye Reserve fr system task start with aphanumeric start with under scre start with number $finish, $mnitr Vaue Leve 0 1 x z Cnditin in Hardware Circuits Lgic zer, fase cnditin Lgic ne, true cnditin Unknwn gic vaue High impedance, fating state 1 x z 0 0 (enabe)

6 Net It represent cnnectins between hardware eements b c a which is cntinuusy driven n wire a; // decare net a wire b, c; // decare tw wires b, c wire d = 1'b0; // net d is fixed t gic vaue 0 A rea wire in hardware defaut vaue is z Register data strage eements defaut vaue is x retain vaue unti anther vaue is paced nt them means a variabe that can hd a vaue reg reset; initia begin reset = 1'b1; #100 reset = 1'b0; reset time reg signed [63:0] m; // 64 bit signed vaue integer i; // 32 bit signed vaue can be used fr signed arithmetic

7 Vectr mutipe bit width wire a; // 1-bit wire [7:0] bus; // 8-bit wire [31:0] busa, busb, busc; // 32-bit reg cck; reg [0:40] virtua_addr; // 41-bit d27 binary b11011 ( ) [high#:w#] r [w#:high#] MSB: mst significant bit MSB is bus[7] MSB is virtua_addr[0] busa busa[0] = 1 virtua_addr virtua_addr[0] = 0 Vectr partia seect busa[7] seect bit #7 f vectr busa busb[8:4] seect 5 bit frm #8 t #4 f busb busc[2:10] it is iega because f busc is [high# : w#] virtua_addr[0:1] tw MSB f virtua_addr reg type integer - the keywrd is integer - decare fr cunting purpse - defaut 32 bit - signed quantities (reg is unsigned quantities) rea (e.g. 3.14) (e.g. 3e6) - be specified in decima ntatin r scientific ntatin - n range decaratin, defaut vaue is 0 time -stre simuatin time - the width at east 64 bits - $time is invked t get the current simuatin time

8 Array 1. reg, integer, time, rea, vectr register data type 2. muti-dimensina array can as be decared with any number f dimensin 3. array f net can as be used t cnnect prts f generated instances integer cunt [0:7]; // an array f 8 cunt variabes reg b [31:0]; // array f 32 ne-bit b register variabes reg [4:0] prt [0:7]; // array f 8 prt; each prt is 5 bit width integer matrix [4:0][0:255]; // tw dimensina array f integers Nte: Vectr is a singe eement that is n-bit width; Array is mutipe eements that are n-bit width. memry In digita simuatin, ne ften needs t mde register fies, RAM, and ROM. Memry is mdeed in Verig simpy as a nedimensina array f registers. reg mem1bit [0:1023]; // mem1bit with 1K 1-bit wrds reg [7:0] membyte [0:1023]; // membyte with 1K 8-bit wrds membyte[511] // fetches 1 byte wrd whse address is bit 511 mem1bit 1023 membyte 1023

9 parameter define a cnstant in a mdue parameter prt_id = 5; // defines a cnstant prt_id parameter state = 3 b010; // define a fixed size parameter state parameter signed [15:0] WIDTH; // fixed sign and range fr parameter WIDTH caparam mdify by tp eve bck parameter x=3; (db3) (design bck 1) (design bck 2) tp eve bck define a cay parameter fr the mdue It is used t define parameters when their vaues shud nt be changed. Fr exampe, the state encding fr a state machine can be defined using caparam. The state encding cannt be changed. string can be stred in reg Each character in the string takes up 8 bits (1 byte). mdue test_string; reg [8*19:1] string_vaue; initia begin string_vaue = He Verig Wrd ; #10 $dispay( %s, string_vaue); mdue Escaped characters \n \t %% \\ \ \ Character dispayed new ine tab % \ ASCII 41: A 01_000_ : a 01_100_ Character written in 1-3 cta digits string_vaue H e V e r i g W r d string_vaue_ H e V e r i g W r d string_vaue_s V e r i g W r d

10 System Task A system tasks appear in the frm $<keywrd> dispaying n the screen mnitring vaues f nets stpping the simuatin finishing the simuatin System Task Usage $dispay $dispay(p1, p2, p3,..., pn); $mnitr $mnitr(p1, p2, p3,..., pn); $stp $stp; $finish $finish; * pi can be as time, string, reg, net $dispay $mnitr $stp $finish Frmat %d r %D %b r %B %h r %H %t r %T %s r %S %c r %C %m r %M Dispay variabe in decima variabe in binary variabe in hex in current time frmat string ASCII character hierarchica name $dispay System Task $dispay( He Verig Wrd ); $dispay($time); reg [0:40] virtua_addr; $dispay("at time %d virtua address is %h", $time, virtua_addr); $dispay("bus vaue is %b", bus); reg [3:0] bus; bus = 4 b0101; Bus vaue is 0101 bus[3:2] = 2 b10; Bus vaue is 10xx $dispay("this is a \n mutiine string with a %% sign"); new ine This is a mutiine string with a % sign

11 $mnitr initia begin $mnitr($time, " Vaue f signas cck = %b reset = %b", cck, reset); initia ck = 1'b0; aways #5 ck = ~ck; initia begin reset = 1'b1; #15 reset = 1'b0; #180 reset = 1'b1; #10 reset = 1'b0; #20 $finish; System Task $time cck reset 0 Vaue f signas cck = 0 reset = 1 5 Vaue f signas cck = 1 reset = 1 10 Vaue f signas cck = 0 reset = 1 15 Vaue f signas cck = 1 reset = 0 20 Vaue f signas cck = 0 reset = 0 25 Vaue f signas cck = 1 reset = 0 30 Vaue f signas cck = 0 reset = 0 input Design Bck utput System Task $stp $finish stp finish debug start cntinue $stp: t susp the simuatin at a certain time $finish: t terminate the simuatin at a certain time initia begin.. #50 $stp;. #1000 $finish; initia begin... #1000 $finish; initia begin... #1000 $stp;

`define `define WORD_SIZE 32 `define S $stp; Cmpier Directive `define WORD_REG reg [31:0] `define A 16 `define B 8 `define C 32 ( #define in C ) mdue KM ( ina, inb, utc); input [`A-1:0] ina; input

12 `define `define WORD_SIZE 32 `define S $stp; Cmpier Directive `define WORD_REG reg [31:0] `define A 16 `define B 8 `define C 32 ( #define in C ) mdue KM ( ina, inb, utc); input [`A-1:0] ina; input [`B-1:0] inb; utput [`C-1:0] utc; mdue reg [ `WORD_SIZE-1:0 ] reg32; reg [ 32-1:0 ] reg32; reg [ 31:0 ] reg32; #1000 `S #1000 $stp; 'WORD_REG reg32; reg [31:0] reg32; `incude `define A 16 `define B 8 `define C 32 Cmpier Directive ( #incude in C ) `define A 16 // bit width fr ina `define B 8 // bit width fr inb `define C 32 // bit width fr inc DEF.v mdue KM ( ina, inb, utc); input [`A-1:0] ina; input [`B-1:0] inb; utput [`C-1:0] utc; mdue spit int `timescae: define time scae #20 hw ng? 20s, 20ms, 20ns `incude DEF.v mdue KM ( ina, inb, utc); input [`A-1:0] ina; input [`B-1:0] inb; utput [`C-1:0] utc; mdue

CS1150 Principles of Computer Science Introduction (Part II)

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