Politecnico di Milano FACOLTÀ DI INGEGNERIA DELL INFORMAZIONE. Sistemi Embedded 1 A.A Exam date: September 5 th, 2017

Size: px

Start display at page:

Download "Politecnico di Milano FACOLTÀ DI INGEGNERIA DELL INFORMAZIONE. Sistemi Embedded 1 A.A Exam date: September 5 th, 2017"

Adele Sharp
6 years ago
Views:

Politecnico di Milano FACOLTÀ DI INGEGNERIA DELL INFORMAZIONE Sistemi Embedded 1 A.A. 2016-2017 Exam date: September 5 th, 2017 Prof. William FORNACIARI Surname (readable).

Anyone found in possession of documents relating to the course, although not directly relevant to the subject of the examination will cancel the test.

1 Politecnico di Milano FACOLTÀ DI INGEGNERIA DELL INFORMAZIONE Sistemi Embedded 1 A.A Exam date: September 5 th, 2017 Prof. William FORNACIARI Surname (readable)... Q1 Q2 TOTAL NOTES It is forbidden to refer to texts or notes of any kind as well as interact with their neighbors. Anyone found in possession of documents relating to the course, although not directly relevant to the subject of the examination will cancel the test. It is not allowed to leave during the first half hour, the task must still be returned, even if it is withdrawn. The presence of the writing (not delivered) implies the renunciation of any previous ratings. Question Q1 a) (11 points) Describe the main strategies and mechanisms to keep under control the power consumption of an Hw/Sw embedded systems. 1/6

2 2/6

3 3/6

4 Question Q2 a) (5 points) Considering the Verilog 2001 specification describe the difference between blocking and non-blocking assignments from the sematic viewpoint. Moreover, describe the general rules to use them in both the testbench and synthesizable logic. Last, introduce the continuous assignment construct in Verilog 2001 specification focusing on their syntax and constraints as well as on the differences with respect to the blocking assignements. b) (4 points) The design is made of two modules, namely the testbench (tb) and the design under test (dut). The dut implements a flip flop chain to delay the input to the output by 2 clock cycles. Identify the errors contained in the two modules. module tb(); //testbench reg clk; reg rst; reg sig_i; wire sig_o; dut dut0(.clk(clk),.rst(rst),.sig_i(sig_i),.sig_o(sig_o)); initial clk<=0; rst=1; sig_i=0; rst<=0; sig_i<=1; repeat(5) repeat(4)@(posedge clk); sig_i <=!sig_i; $finish(); always #5 clk =!clk; module module dut(clk,rst,sig_i,sig_o); //design under test input clk; input rst; input sig_i; output sig_o; reg a_o, b_o; wire a_i, b_i; always@(posedge clk) if(rst) a_o<=0; b_o<=0; else a_o <= a_i; b_o <= b_i; assign a_i = sig_i; assign b_i = a_o; assign sig_o = b_o; module c) (2 points) Fix the errors in the two modules described in question Q2.b. 4/6

5 Q2.a (short answer) continuous assignments assignments from RHS to LHS happens continuously. LHS has to be a wire according to Verilog User for combinatorial circuits reg b; wire a; assign a=b; blocking assignments (BA) inside procedural construct, i.e., always blocks. LHS has to be of type reg. BA statements within the same always block are evaluated one after the other. Used to implement combinatorial logic. Non-blocking assignment (NBA) - inside procedural construct, i.e., always blocks. LHS has to be of type reg. NBA statements are evaluated all together and the LHS update happens after the update of the LHS of continuous and blocking assignments. In the testbench exploits the order of the update to properly model the behavior. Clock after init has to be updated using blocking assignments (BAs) while all the other non clock signals should be updated using NBAs to force their update to be simultaneous and happening after the clock one. Q2.b (short answer) dut 1) assign cannot stay within a procedural block (i.e., always block) 2) a_i and b_i has to be declared as wires tb 1) clock semantic is missing: 2)all the signals but the clk have to be updated using NBAs after the first initialization. Q3.c (short answer) 1) move out the continuous assignments from the always block 2) redeclare a_i and b_i as wires 1) clock signal in the testbench: for example use always #5 clk =!clk; 2) change the blocking assignment with an NBA within the initial block of the testbench initial clk<=0; rst=1; sig_i=0; rst<=0; sig_i<=1; repeat(5) repeat(4)@(posedge clk); sig_i <=!sig_i; $finish(); 5/6

6 6/6

Politecnico di Milano FACOLTÀ DI INGEGNERIA DELL INFORMAZIONE. Real-Time Operating Systems A.A Exam date: 11 Sep 2014

Politecnico di Milano FACOLTÀ DI INGEGNERIA DELL INFORMAZIONE Real-Time Operating Systems A.A. 2013-2014 Exam date: 11 Sep 2014 Prof. William FORNACIARI Surname (readable)... Matr... Name (readable)...