CHAPTER Pearson Education, Inc. S_n. R_n. Q_n. 0 ps 20 ns 40 ns 60 ns 80 ns. C S R Q Q_n. 0 ps 50 ns 100 ns 150 ns 200 ns

Transcription

1 HAPTER 5 28 Pearson Education, Inc. 5-. S_n R_n Q Q_n 5-2. S R Q Q_n ps 2 ns 4 ns 6 ns 8 ns ps 5 ns ns 5 ns 2 ns 5-3. Q Q_n ps 5 ns ns 5 ns

2 5-5. Unknown 5-6. A Y A B Z B Present state Inputs Next state Output A B Y A B Z S - S - S2 - S3 - / / S /,/ S / S3 / / / S2 / / ( = unspecified) Y/Z ( = unspecified) 64

3 5-7.* Present state Input Next state A B A B A = (B + B) x + (B + B) x A = B + A = A A = B = = 5-8. Present state Inputs Next state Output Q Y Q S /, / /, / /, / /, / Format: Y/S 5-9. Present State Input Output Next State 5-. / / / x/, / / / / / 3 2 x/, / Format: Y/Z /, / / 65

4 5-.* S A = B R A = B S B = A R B = A Present state Input Next state Output / / A B A B Y / / / 2 3 / Format: /Y / / 5-2. a) A =, B =, Reset =, Asynchronous Reset A = A + B B = A A =, B =, Reset = S R A A =, B =, Reset = Reset S B Asynchronous Reset All the others gates remains as in figure 5-5. R b) A =, B =, Signal Reset =, Synchronous Reset. A A Reset lock B B Y 66

5 5-3.* Present state Input Next state A B A B A A = B + A B B A B = A + B A A B B 5-4. a) State Table Present state Inputs Next state Output Q Q 2 2 Q t+ Q 2 t+ Z Encoding: State ode(q Q 2 ) A B 67

6 Q Q2 Q Q Q2 Q2 Q Q Next State Q(t+) Present state For Input Output Q(t) = = Z A B B A F F E E F E F Encoding: State ode(q Q 2 Q 3 ) A B E F Unused states:,. The state assignment could be different. E.g. statesa,borcould be and states, E or F could be. 68

7 Q Q 2 Q Encoding: State ode(q Q 2 Q 3 ) A B E F Next State Q(t+) Present state For Input Output Q(t) = = Z A E B E E F A E B F E 69

8 Next State Q(t+) Output Present state For Input Q(t) = = M M N N N O O M M Y = YZ Z = Z + YZ Gate input cost of the original circuit: = 63 Gate input cost of the new circuit: = 37 States A,, F are equivalent and merged to get state M. States B and E are equivalent and merged to get state N. State becomes state O. Encoding: Z is a state variable and an output, and Y is a state variable. State ode(yz) M N O 5-7. Present state Inputs Next state Output ABE a b c d ABE U x x x x x x x x x x x x x x x x x x x x x x x x x x x x A = AA + BB + + B = A A = BB = E = E + U = E Signal L is applied to the asynchronous set/reset inputs on the flip-flops to implement locking. A B E U 7

9 5-8.* / x/x Format: Y/Z (x = unspecified) x/x / / / Present state Inputs Next state Output Q(t) Y Q(t+) Z 5-9. E= / / 2/ 3/ 4/ 5/ 6/ 7/ E= Present state Next State For Input Output 2 E= E= Z The state assignment could be different. E. g., state 7 could be with state. This would permit use of R inputs on the flip-flops for RESET. RESET E S S Z S 2 LK 7

10 5-2. E= / / 2/ 3/ 4/ 5/ 6/ 7/ Present state Next State For Input E= Output 2 E= E= Z Assumes for E =, the output remains at. RESET E S S Z S LK =x/ Z=,S= 5 =/Z=,S= =/ Z=, S= =/ Z=,S= =/Z=,S= =/Z=,S= =/ Z=,S= =/ Z=,S= 4 3 =/Z=,S= =/ Z=,S= 2 =/ Z=,S= Present state Input Next state Output A B A B Z S 72

11 Z S LK = / Z= = / Z= = / Z= = / Z= Present state Input Next state Output A A Z LK R RESET Z = / Z= = / Z= = / Z= Present state Input Next state Output = / Z= A A Z Z LK R RESET 73

12 74 Problem Solutions hapter Reset / x/ xx/ / x/ / x/ / x/ / Format: RA/E (x = unspecified) / / / Present state Inputs Next state Output B R A B E Present state Inputs Next state Output B R A B E x/ / / x/ x/ Present state Input Next state Output A Y A Z Format: Y/Z (x = unspecified)

13 5-26.* To use a one-hot assignment, the two flip-flops A and B need to be replaced with four flip-flops Y4, Y3, Y2. Y. Problem Solutions hapter 5 Present State Input Next State Output A B Y4 Y3 Y2 Y A B" Y4 Y3 Y2 Y Z No Reset State Specified. = Y = Y + Y4 2 = Y2 = Y + Y2 3 = Y3 = Y2 + Y3 4 = Y4 = Y3 + Y4 Y Y2 Y3 Y4 Y lock 5-27.* a) S R Q Q No hange Reset Set Set b) Format: SR,,,, 75

14 c) Present state Input Next state Q S R Q(t+) A B x x x x x A = S B = SR S R A S B R lock Q Present State AB Next State AB a) A = B = A = B b) lear A = Reset lear B = Reset lear = Reset c, d, e, f) The circuit is suitable for child s toy, but not for life critical applications. In the case of the child s toy, it is the cheapest implementation. If an error occurs the child just needs to reset it. In life critical applications, the immediate detection of errors is critical. The circuit above enters invalid states for some errors. For a life critical application, additional circuitry is needed for immediate detection of the error (Error = AB + AB). This circuit using the design in a), does return from the invalid states to a valid state automatically after one or two clock periods. Specification Verification Present state Input Next state Next state Q S R Q(t+) A B A B Q(t+) x x x x x 76

15 5-3. lock Reset Y A B ps 2 ns 4 ns 6 ns 8 ns 5-3.* RESET 7 x/, / / / 2 / / / / 3 2 x/, / Format: Y/Z 5 / 4 /, / / 9 Reset,,,,,, x, x,,,,,,,,. Y A Z lock B lock Reset Y A B ps 2 ns 4 ns 6 ns 8 ns 77

16 5-33.* lock J K Y Q ps 5 ns ns 5 ns This simulation was performed without initializing the state of the latches of the flip-flop beforehand. Each gate in the flip-flop implementation has a delay of ns. The interaction of these delays with the input change times produced a narrow pulse in Y at about 55 ns. In this case, the pulse is not harmful since it dies out well before the positive clock edge occurs. Nevertheless, a thorough examination of such a pulse to be sure that it does not represent a design error or important timing problem is critical Function table for the LH flip-flop. LK LOA ATA OUTPUT L Q(t+) S R No change No change S L R LL Flipflop in a Master-Slave ircuit. S R Q Q Y State table: State State Transition Next State Non-zero ode ondition State ode Outputs A A B B / Z Y A Y Y / Z A Z Y + Y Y + Y Y2 78

17 5-36. Problem Solutions hapter 5 onstraint checks on the transition conditions (T): Init: There is one pair of Ts to check: (ST ART +STOP ) START S TO P = Fill_: There are three pairs of Ts to check: L S TOP STOP =, L S TOP L S TOP =, STOP L S TOP = Fill_2: There are six pairs of Ts to check: L2 N I S TOP STOP =, L2 N I S TOP L 2 S TOP =, L2 N I S TOP L2 NI S TOP =, STOP L 2 S TOP =, STOP L2 NI S TOP =, L 2 S TOP L2 NI S TOP = Fill_3: There are three pairs of Ts to check: L 3 S TOP STOP =, Mix: There are three pairs of Ts to check: L 3 S TOP L3 S TOP =, STOP L3 S TOP = T Z S TOP STOP =, T Z S TOP TZ S TOP =, STOP TZ S TOP = Empty: There is one pair of Ts to check: L S TOP (L+STOP) = onstraint 2 checks on the transition conditions (T): Init: S TART +STOP +START S TOP = Fill_: L S TOP +STOP +L S TOP = Fill_2: L2 N I S TOP +STOP + L 2 S TOP +L2 NI S TOP = Fill_3: L 3 S TOP +STOP +L3 S TOP = Mix: T Z S TOP +STOP + TZ S TOP = Empty: L S TOP +L+STOP = 5-37.* ( ) 79

18 5-38. State Transition Next State Non-zero State ode ondition State ode Outputs Init N 5 Q ispense N Q Init oin_return R Init 5 N 5 Q ispense R oin_return R N Q 5 N 5 2 Q ispense R oin_return R N Q 5 N 2 +Q ispense R oin_return R N Q 5 2 N + + Q ispense R oin_return ispense R N Q 2 Init J flip-flop inputs: Init (t + ) = Init N Q + oin_return + ispense oin_return (t + ) = 5 R+ R+5 R+2 R 5 (t + ) = Init N+5 R N Q (t + ) = Init +5 N+ R N Q 5 (t + ) = 5 + N+5 R N Q 2 (t + ) = +5 N+2 R N Q ispense (t + ) = Q N (a) R Reset Outputs: R = oin_return J = ispense Noh Q Q Q Q Q Q Init 25c 5c 75c c 25c isp_orange isp_root_beer No_hange R R R L O R R R Q R LT2Q isp_ola isp_lemon 5c L O R LE 2c Return_2_Quarters 8

19 (b) Some possible changes to the specification follow.. Provide appropriate change and dispense soda for the cases in which 75 cents and 25 cents followed by a dollar have been deposited. Provide a coin return button for the event that the user is out of quarters and dollars before the 5c state is reached. 3. hange the No hange warning to cover all added cases in. 5-4.* library IEEE; use IEEE.std_logic_64.all; entity mux_4to is port ( S: in ST_LOGI_VETOR ( downto ); : in ST_LOGI_VETOR (3 downto ); Y: out ST_LOGI ); mux_4to; -- (continued in the next column) architecture mux_4to_arch of mux_4to is process (S, ) case S is when "" => Y <= (); when "" => Y <= (); when "" => Y <= (2); when "" => Y <= (3); when others => null; process; mux_4to_arch; 5-4. library IEEE; use IEEE.std_logic_64.all; entity mux_4to is port ( S: in ST_LOGI_VETOR ( downto ); : in ST_LOGI_VETOR (3 downto ); Y: out ST_LOGI ); mux_4to; -- (continued in the next column) architecture mux_4to_arch of mux_4to is process (S, ) if S = "" then Y <= (); elsif S = "" then Y <= (); elsif S = "" then Y <= (2); elsif S = "" then Y <= (3); null; process; mux_4to_arch; 8

20 library IEEE; use IEEE.std_logic_64.all; entity serial_b_ex3 is port (clk, reset, : in ST_LOGI; Z : out ST_LOGI); serial_b_ex3; architecture process_3 of serial_b_ex3 is type state_type is (Init, B, B, B2, B2, B2, B3, B3); signal state, next_state: state_type; -- Process - state register state_register: process (clk, reset) if (reset = '') then state <= Init; if (LK'event and LK='') then state <= next_state; process; -- (continued in the next column) -- Process 2 - next state function next_state_func: process (, state) case state is when Init => if ( = '') then next_state <= B; next_state <= B; when B => if ( = '') then next_state <= B2; next_state <= B2; when B => next_state <= B2; when B2 => next_state <= B3; when B2 => if ( = '') then next_state <= B3; next_state <= B3; when B2 => if ( = '') then next_state <= B3; next_state <= B3; when B3 => next_state <= Init; when B3 => next_state <= Init; process; -- Process 3 -output function output_func: process (, state) case state is when Init => if ( = '') then Z <= ''; Z <= ''; when B => -- (continued in the next column) if ( = '') then Z <= ''; Z<= ''; when B => Z <= ; when B2 => Z <= ; when B2 => if ( = '') then Z <= ''; Z <= ''; when B2 => if ( = '') then Z <= ''; Z <= ''; when B3 => Z <= ; when B3 => Z <= ''; process; process_3; 82

21 clk reset x z state init b b2 b3x init b b2 b3x init b b2 b3x init clk reset x z state init b b2 b3 init b b2x b3x init b b2x b3 init library IEEE; use IEEE.std_logic_64.all; entity prob_5_43 is port (clk, reset : in ST_LOGI; : in ST_LOGI_VETOR(2 downto ) ; Z : out ST_LOGI); prob_5_43; architecture process_3 of prob_5_43 is type state_type is (A, B,, ); signal next_state, state : state_type; -- ontinued in next column -- Process - state register state_register: process (clk, reset) if (reset = '') then state <= A; elsif (clk'event and clk = '') then state <= next_state; process; -- Process 2 - next state function next_state_func: process (, state) -- ontinued on next page 83

22 case state is when A => case is when "" => next_state <= A; when "" => next_state <= B; when "" => next_state <= B; when "" => next_state <= A; when others => next_state <= A; when B => case is when "" => next_state <= A; when "" => next_state <= A; when "" => next_state <= ; when "" => next_state <= ; when others => next_state <= A; when => case is when "" => next_state <= A; when "" => next_state <= A; when "" => next_state <= ; when "" => next_state <= ; when others => next_state <= A; when => case is when "" => next_state <= ; when "" => next_state <= B; when "" => next_state <= B; when "" => next_state <= ; when others => next_state <= A; process; -- ontinued in next column -- Process 3 -output function output_func: process (, state) case state is when A => case is when "" => Z <= ''; when "" => Z <=''; when "" => Z <= ''; when "" => Z <= ''; when others => Z <= ''; when B => case is when "" => Z <= ''; when "" => Z <=''; when "" => Z <= ''; when "" => Z <= ''; when others => Z <= ''; when => case is when "" => Z <= ''; when "" => Z <=''; when "" => Z <= ''; when "" => Z <= ''; when others => Z <= ''; when => case is when "" => Z <= ''; when "" => Z <=''; when "" => Z <= ''; when "" => Z <= ''; when others => Z <= ''; process; process_3; 84

23 * library IEEE; use IEEE.std_logic_64.all; entity prob_5_44 is port (clk, reset, : in ST_LOGI; Z : out ST_LOGI); prob_5_44; architecture process_3 of prob_5_44 is type state_type is (A, B,,, E, F); signal state, next_state: state_type; -- Process - state register state_register: process (clk, reset) if (reset = '') then state <= A; if (LK'event and LK='') then state <= next_state; process; -- Process 2 - next state function next_state_func: process (, state) case state is when A => if = '' then next_state <= B; next_state <= ; when B => if = '' then next_state <= ; next_state <= ; when => if = '' then next_state <= A; -- ontinued in next column library IEEE; use IEEE.std_logic_64.all; entity jkff is port ( J,K,LK: in ST_LOGI; Q: out ST_LOGI ); jkff; architecture jkff_arch of jkff is signal q_out: std_logic; state_register: process (LK) if LK'event and LK='' then --LK falling edge -- (continued in the next column) next_state <= F; when => if = '' then next_state <= F; next_state <= ; when E => if = '' then next_state <= ; next_state <= E; when F => if = '' then next_state <= E; next_state <= F; process; -- Process 3 -output function output_func: process (, state) case state is when A => Z <= ''; when B => Z <= ''; when => Z <= ''; when => Z <= ''; when E => Z <= ''; when F => Z <= ''; process; process_3; case J is when '' => if K = '' then q_out <= ''; when '' => if K = '' then q_out <= ''; q_out <= not q_out; when others => null; process; Q <= q_out; jkff_arch; 85

24 86

25 5-46. (Errata: Replace "5-" with "5-") library IEEE; use IEEE.std_logic_64.all; entity prob_5_46 is port (clk, reset, NI, Start, Stop, L, L, L2, L3, TZ : in ST_LOGI; M, PST, TM, V, V2, V3, VE : out ST_LOGI); prob_5_46; architecture process_3 of prob_5_46 is type state_type is (Init, Fill_, Fill_2, Fill_3, Mix, Empty); signal state, next_state: state_type; -- Process - state register state_register: process (clk, reset) if (reset = '') then state <= Init; if (LK'event and LK='') then state <= next_state; process; -- Process 2 - next state function next_state_func: process (NI, Start, Stop, L, L, L2, L3, TZ, state) if Stop = '' then next_state <= Init; case state is when Init => if Start = '' then next_state <= Fill_; next_state <= Init; when Fill_ => if L = '' then next_state <= Fill_2; next_state <= Fill_; when Fill_2 => if L2 = '' then if NI = ''then next_state <= Fill_3; next_state <= Mix; next_state <= Fill_2; -- ontinued in next column process; when Fill_3 => if L3 = '' then next_state <= Mix; next_state <= Fill_3; when Mix => if TZ = '' then next_state <= Empty; next_state <= Mix; when Empty => if L = '' then next_state <= Init; next_state <= Empty; -- Process 3 - output function output_func: process (L2, L3, NI, TZ, Stop, state) M <= ''; PST <=''; TM <=''; V <=''; V2 <=''; V3 <=''; VE <=''; case state is when Init => when Fill_ => V <= ''; when Fill_2 => V2 <= ''; if ((L2 and not NI and not Stop) = '') then PST <= ''; when Fill_3 => V3 <= ''; if ((L3 and not Stop) = '') then PST <= ''; when Mix => M <= ''; if ((not TZ and not Stop) = '') then TM <= ''; when Empty => VE <= ''; process; process_3; 87

26 5-47. library IEEE; use IEEE.std_logic_64.all; entity prob_5_47 is port (clk, reset, R, N,, Q : in ST_LOGI; J, R : out ST_LOGI); prob_5_47; architecture process_3 of prob_5_47 is type state_type is (S, S5, S, S5, S2, S25, RT); signal state, next_state: state_type; -- Process - state register state_register: process (clk, reset) if (reset = '') then state <= S; if (LK'event and LK='') then state <= next_state; process; -- Process 2 - next state function next_state_func: process (R, N,, Q, state) case state is when S => if N = '' then next_state <= S5; elsif = '' then next_state <= S; elsif Q = '' then next_state <= S25; next_state <= S; when S5 => if R = '' then next_state <= RT; elsif N = '' then next_state <= S; elsif = '' then next_state <= S5; elsif Q = '' then next_state <= S25; next_state <= S5; when S5 => if R = '' then next_state <= RT; elsif N = '' then next_state <= S2; elsif = '' then next_state <= S25; elsif Q = '' then next_state <= S25; next_state <= S5; when S2 => if R = '' then next_state <= RT; elsif N = '' then next_state <= S25; elsif = '' then next_state <= S25; elsif Q = '' then next_state <= S25; next_state <= S2; when S25 => next_state <= S; when RT => next_state <= S; process; -- Process 3 - output function output_func: process (R, N,, Q, state) J <= ''; R <= ''; case state is when S25 => J <= ''; when RT => R <= ''; when others => null; process; process_3; when S => if R = '' then next_state <= RT; elsif N = '' then next_state <= S5; elsif = '' then next_state <= S2; elsif Q = '' then next_state <= S25; next_state <= S; -- ontinued in next column 88

27 * module problem_6_38 (S,, Y) ; input [:] S ; input [3:] ; output Y; reg Y ; // (continued in the next column) module problem_6_39 (S,, Y) ; input [:] S ; input [3:] ; output Y; reg Y ; // (continued in the next column) //Serial B to Excess 3 onverter module serial_b_ex3(clk, reset,, Z); input clk, reset, ; output Z; reg[2:] state, next_state; parameter Init = 3'b, B = 3'b, B=3'b, B2= 3'b, B2 = 3'b, B2 = 3'b, B3 = 3'b, B3 = 3'b; reg Z; // State Register always@(posedge clk or posedge reset) if (reset == ) state <= Init; state <= next_state; // Next StateFunction always@( or state) case (state) Init: if ( == ) next_state <= B; next_state <= B; B: if ( == ) next_state <= B2; next_state <= B2; B: next_state <= B2; B2: next_state <= B3; B2: if ( == ) next_state <= B3; next_state <= B3; // (continued in the next column) or ) case (S) 2'b : Y <= [] ; 2'b : Y <= [] ; 2'b : Y <= [2] ; 2'b : Y <= [3] ; case; module or ) if (S == 2'b) Y <= []; if (S == 2'b) Y <= []; if (S == 2'b) Y <= [2]; Y <= [3]; module B2: if ( ==) next_state <= B3; next_state <= B3; B3: next_state <= Init; B3: next_state <= Init; case // Output Function always@( or state) case (state) Init: if ( == ) Z <= ; Z <= ; B: if ( == ) Z <= ; Z <= ; B: Z <= ; B2: Z <= ; B2: if ( == ) Z <= ; Z <= ; B2: if ( == ) Z <= ; Z <= ; B3: Z <= ; B3: Z <= ; case module 89

28 State Assignment State ode State Name Init B B2 B B3 B3 B2 B2 clk reset Z state clk reset Z state // State iagram in Figure 5-4 using Verilog module prob_5_5 (clk, reset,, Z); input clk, reset; input[:2] ; output Z; reg[:] state, next_state; parameter A = 2'b, B = 2'b, = 2'b, = 2'b; reg Z; // State Register always@(posedge clk or posedge reset) if (reset == ) state <= A; state <= next_state; // Next StateFunction always@( or state) case (state) A: if ( == 2'b == 2'b) next_state <= B; next_state <= A; B: if ( == 2'b == 2'b) next_state <= ; next_state <= A; : if ( == 2'b == 2'b) // (continued in the next column) next_state <= A; next_state <= ; : if ( == 2'b == 2'b) next_state <= ; next_state <= B; case // Output Function always@( or state) case (state) A: if ( == 2'b == 2'b == 2'b) Z <= ; Z <= ; B: if ( == 2'b == 2'b) Z <= ; Z <= ; : if ( == 2'b == 2'b) Z <= ; Z <= ; : if ( == 2'b == 2'b == ) Z <= ; Z = ; case module 9

29 5-52. // State iagram in Figure 5-4 using Verilog module prob_5_52 (clk, reset,, Z); input clk, reset; input ; output Z; reg[2:] state, next_state; parameter A = 3'b, B = 3'b, = 3'b, = 3'b, E = 3'b, F = 3'b; reg Z; // State Register always@(posedge clk or posedge reset) if (reset == ) state <= A; state <= next_state; // Next StateFunction always@( or state) case (state) A: if ( == ) next_state <= ; next_state <= B; B: if ( == ) next_state <= ; next_state <= ; : if ( == ) (continued in the next column) 5-53.* module JK_FF (J, K, LK, Q) ; input J, K, LK ; output Q; reg Q; next_state <= F; next_state <= A; : if ( == ) next_state <= ; next_state <= F; E: if ( == ) next_state <= E; next_state <= ; F: if ( == ) next_state <= F; next_state <= E; case // Output Function always@( or state) case (state) A: Z <= ; B: Z <= ; : Z <= ; : Z <= ; E: Z <= ; F: Z <= ; case module LK) case (J) 'b: Q <= K? : Q; 'b: Q <= K? ~Q: ; case module 9

30 5-54. // State Machine for Batch Mixing System (Figure 5-29) module batch_mixing_system (clk, reset, START, STOP, L, L, L2, L3, NI, TZ, V, V2, V3, PST, M, TM, VE); input clk, reset, START, STOP, L, L, L2, L3, NI, TZ; output V, V2, V3, PST, M, TM, VE; reg V, V2, V3, PST, M, TM, VE; reg[2:] state, next_state; parameter Init = 3'b, Fill_ = 3'b, Fill_2 = 3'b, Fill_3 = 3'b, Mix = 3'b, Empty = 3'b; // State Register always@(posedge clk or posedge reset) // (continued in the next column) if (reset == ) state <= Init; state <= next_state; // Next StateFunction always@( START or STOP or L or L or L2 or L3 or TZ or state) case (state) Init: if (START == & STOP == ) next_state <= Fill_; next_state <= Init; // (continued on the next page) Fill_: if (STOP == ) next_state <= Init; if (L == ) next_state <= Fill_2; next_state <= Fill_; Fill_2: if (STOP == ) next_state <= Init; if (L2 == ) if (NI == ) next_state <= Fill_3; next_state <= Mix; next_state <= Fill_2; Fill_3: if (STOP == ) next_state <= Init; if (L3 == ) next_state <= Mix; next_state <= Fill_2; Mix: if (STOP == ) next_state <= Init; if (TZ == ) next_state <= Empty; next_state <= Mix; Empty: if (STOP == L == ) next_state <= Init; next_state <= Empty; // (continued in the next column) case // Output Function always@(l2 or NI or STOP or L3 or TZ or state) case (state) Fill_: V <= ; Fill_2: V2 <= ; if (L2 & ~ NI & ~STOP) PST <= ; PST <= ; Fill_3: V3 <= ; if (L3 & ~STOP) PST <= ; PST <= ; Mix: M <= ; if (~TZ & ~STOP) TM <= ; TM <= ; Empty: VE <= ; case module 92

31 5-55. // State Machine for Jawbreaker Ving Machine module jawbreaker_ving_machine (clk, reset, R, N,, Q, R, J); input clk, reset, R, N,, Q; output R, J; reg R, J; reg[6:] state, next_state; parameter Init = 7'b, S5c = 7'b, Sc = 7'b, S5c = 7'b, S2c = 7'b, ispense = 7'b, oin_return = 7'b; // State Register always@(posedge clk or posedge reset) if (reset == ) state <= Init; state <= next_state; // Next StateFunction always@(r or N or or Q or state) case (state) Init: if (N == ) next_state <= S5c; if ( == ) next_state <= Sc; if (Q == ) next_state <= ispense; next_state <= Init; // (continued in the next column) S5c: if (N == ) next_state <= Sc; if ( == ) next_state <= S5c; if (Q == ) next_state <= ispense; if (R == ) next_state <= oin_return; next_state <= S5c; Sc: if (N == ) next_state <= S5c; if ( == ) next_state <= S2c; if (Q == ) next_state <= ispense; if (R == ) next_state <= oin_return; next_state <= Sc; S5c: if (N == ) next_state <= S2c; if ( == ) next_state <= ispense; if (Q == ) next_state <= ispense; if (R == ) next_state <= oin_return; next_state <= S5c; S2c: if (N == ) next_state <= ispense; if ( == ) next_state <= ispense; if (Q == ) next_state <= ispense; if (R == ) next_state <= oin_return; next_state <= S2c; ispense: next_state <= Init; oin_return: next_state <= Init; case (continued in the next column) // Output Function always@(state) R <= ; J <= ; case (state) ispense: J <= ; oin_return: R <= ; case module ; 93