RealDigital. Problem Set #7 S1 S2 S3 Y Z X Y + Y Z X Z

Transcription

1 Problem Set #7 RealDigital 1. (10 points) Modify the state diagram branching conditions in the diagrams below as needed to ensure the sum and exclusion rules are obeyed in each case. You can add a holding conditions or change branch codes as desired. and Y = 1 A = '0' and Y = 1 Y= 0' and W='0' S1 = 0' ='0' D ='1' = 0' and Y= 0' and Z='1' ='0' and Y= 0 C E = 0' and Y= 0' and Z='0' = 0' and Y= 1' W= 1' S2 S4 S3 Modify the S4 branch and holding condition only 2. (4 points) What to S2 branch can be added so that all possible branch conditions go to at least one state? How can the holding condition be modified to ensure there is one and only one next state for all possible branch conditions? Enter the branch conditions below. Z S0 Y Z Y + Y Z To S2: Holding condition: S1 S2 S3

2 3. (15 points) A ving machine should SELL an item if 30 cents is input. The machine has a coin sensor that can detect nickels, dimes, and quarters, and reject everything else. No change is given (i.e, if two quarters are input, simply assert SELL and keep the fifty cents). Sketch a state diagram to assert SELL when adequate coinage has been inserted.

3 4. (15 points) Sketch a Moore-model and also a Mealy-model state diagram for a sequential machine that can detect when a four-digit combination has been typed into a numeric keypad. Use last four numbers of your telephone number for a combination. A start button must be pressed immediately prior to entering a valid combination, and an open button must be pressed immediately after a valid combination. For this problem, you can assume that two buttons cannot be asserted simultaneously (i.e., if more than one button is pressed, only the signal from the first button pressed will be asserted until it is released; the second button will be asserted after the first button is released if it is still being pressed. If more than two buttons are pressed, and the first button pressed is released, then the second button pressed will be asserted until it is released, and so forth). The Any utton (A) output will be asserted as soon as any button is pressed, and deasserted only when no buttons are pressed St 0 Op St Op A

4 5. (25 points) Sketch a circuit for the state machines below. = '0' 00 A PS PS f 1 1 A NS A PS PS f 1 0 RED = '0' 11 A PS PS 0 1 f Y Next-state maps NS A PS PS f Output Maps GRN 6. (16 points) In the timing diagram below, show the time courses of the flip-flops (labeled A and ) and output signals defined by the state diagram. A A A 11 LU <= F 1 F 2 A RED A A+ LU RED <= A CLK RST A F 1 F 2 RED LU

5 7. (25 points) Sketch a state diagram based on the following Verilog Code module fsm ( CLK, RST,, Y, Z, RED, LUE); input CLK, RST,, Y, Z; output reg RED, LUE; localparam S1 = 2 d0; localparam S2 = 2 d1; localparam S3 = 2 d2; localparam S4 = 2 d3; reg [1:0] ps, ns; (ps, x, y, z) begin case (ps) S1: begin RED = 1 b0; LUE = 1 b0; if ( == 1 b0) ns = S1; else ns = S2; S2: begin RED = 1 b0; LUE = 1 b1; if ( == 1 b0 && Y == 1 b0 && Z == 1 b0) ns = S2; else if ( == 1 b1 Y == 1 b1) ns = S1; else if (Z == 1 b1 && == 1 b0 && Y == 1 b0) ns = S3; S3: begin RED = Y; LUE = 1 b0; if (Y == 1 b1 && == 1 b0 && Z == 1 b0) ns = S4; else if ( == 1 b0 && Y == 1 b0 && Z == 1 b0) ns = S3; else if ( == 1 b1 Z == 1 b1) ns = S1; S4: begin RED = 1 b1; LUE = ; ns = S1; default: begin RED = 1 b0; LUE = 1 b0; ns = S1; case (CLK, RST) begin if (RST == 1 b1) ps <= S1; else ps <= ns; module

6 8. (16 points) Assign state codes to the state diagrams below, using unit-distance coding and/or matching state codes to outputs = '0' ODD <= '1' ODD <= '1' = '0' = '0' and Y = 1 or Y = 0 = '0' and Y = 0 = '0' and Y = 0 ='0' ='1' ='1' and Y= 0 = '0' and Y = 1 LU <= '1' LU <= '1'

7 9. (16 points) A simple state machine must assert three outputs (R, G, ) in sequence for 333ms each. An input signal called Start is created from a push button. Sketch a state machine that can output the required sequence of signals (R, G, and ) once each time the button is pressed. You have a 3Hz clock and a 1KHz clock to work with. The push button can bounce for up to 2ms on any transition. (Hint: You can use two state machines)

8 10. (8 points) A state machine receives an input that is synchronous with the system clock. If is a 1, then the machine must output a signal RED for one clock cycle. Then, if is still asserted, the machine must output a signal GRN for one clock cycle, but if is not asserted, the machine must assert an output called LU. The state diagram below meets these requirements. Can you sketch a machine that can meet these same requirements, but that uses just one flip-flop? S0 Red S1 S2 GRN LU S3