ELE432. ADVANCED DIGITAL DESIGN HACETTEPE UNIVERSITY ROUTING and FPGA MEMORY. In part from ECE 448 FPGA and ASIC Design with VHDL

Transcription

1 ELE432 ADVANCED DIGITAL DESIGN HACETTEPE UNIVERSITY ROUTING and FPGA MEMORY In part from ECE 448 FPGA and ASIC Design with VHDL

2 Organization of the Week Routing in FPGA Memory Design in FPGA

3 Xilinx Programmable Gate Arrays CLB - Configurable Logic Block 5-input, 1 output function or 2 4-input, 1 output functions optional register on outputs Built-in fast carry logic Can be used as memory RAM-programmable can be reconfigured IOB IOB IOB IOB IOB IOB IOB CLB CLB Wiring Channels CLB CLB IOB

4 The Virtex CLB

5 Details of One Virtex Slice

6 CLB Slice Structure Each slice contains two sets of the following: Four-input LUT Any 4-input logic function, or 16-bit x 1 sync RAM (SLICEM only) or 16-bit shift register (SLICEM only) Carry & Control Fast arithmetic logic Multiplier logic Multiplexer logic Storage element Latch or flip-flop Set and reset True or inverted inputs Sync. or async. control

7 4-input function 3-input function; registered

8 Implement Some Larger Functions e.g. 9-input parity

9 LUT (Look-Up Table) Functionality x 1 x 2 x 3 x y x 1 x 2 x 3 x 4 LUT y x 1 x 2 x 3 x 4 x 1 x 2 x 3 x y Look-Up tables are primary elements for logic implementation Each LUT can implement any function of 4 inputs x 1 x 2 y y

10 Xilinx Routing The general architecture of Xilinx FPGAs consists of a two-dimensional array of programmable blocks, called Configurable Logic Blocks CLBs, with horizontal and vertical routing channels between CLB s rows and columns.

11 Island Style Architectecture

12 Connection boxes Flexibility of Connection, Fc = 2, Can A connect to B?

13 Switch Boxes Fs, defines for a wiring segment entering the S block the number of other wiring segments it can be connected to

14 Routings using C and S Boxes

15 Routing Algorithms Maze Router A* Search Routing The Pathfinder

16 Example Maze Router

17 Memory Types

18 Memory Needs Many applications require memory Table-Driven code Storage for tables Signal Processing Storage for coefficients Image Processing Storage for windows in images Text processing Storage for dictionaries Unfortunately, memory tends to be a critical resource in FPGA implementations!

19 Memory Types

20 Memory Types Memory Distributed (MLUT-based) Block RAM-based (BRAM-based) Memory Inferred Instantiated Manually Using Core Generator

21 Memory Organizations Classified by number of ports Single One reader or one writer at any time Dual Two ports simultaneous read or write You can simultaneously perform one read and one write operations to different locations where the write operation happens on port A and the read operation happens on port B. Conflicts can occur software is usually responsible for ensuring that operation is safe Used for interfacing between two separate systems eg communication between two processors add data R/~W add data R/~W add data R/~W add data R/~W

22 FPGA Distributed Memory The configuration logic blocks(clb) in most of the Xilinx FPGA's contain small single port or double port RAM. This RAM is normally distributed throughout the FPGA than as a single block(it is spread out over many LUT's) and so it is called "distributed RAM". A look up table on a FPGA can be configured as a 16*1bit RAM, ROM, LUT or 16bit shift register. For Spartan-3 series, each CLB contains upto 64 bits of single port RAM or 32 bits of dual port RAM. As indicated from the size, a single CLB may not be enough to implement a large memory. Also the most of this small RAM's have their input and output as 1 bit wide. For implementing larger and wider memory functions you can connect several distributed RAM's in parallel.

23 Multipurpose LUT Simplified logic cell (LC) The Design Warrior s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright 2004 Mentor Graphics Corp. (

24 Distributed RAM RAM16X1S CLB LUT s are configurable as Distributed RAM A LUT equals 16x1 RAM Cascade LUTs to increase RAM size Synchronous write Can create a synchronous read by using extra flip-flops Asynchronous read Naturally, distributed RAM read is asynchronous Two LUTs can make 32 x 1 single-port RAM 16 x 2 single-port RAM 16 x 1 dual-port RAM LUT LUT LUT = RAM32X1S D WE WCLK A0 A1 A2 A3 A4 or = O D WE WCLK A0 A1 A2 A3 RAM16X2S D0 D1 WE WCLK O0 A0 O1 A1 A2 A3 or O RAM16X1D D WE A0 A1 A2 A3 WCLK DPRA0 DPRA1 DPRA2 DPRA3 SPO DPO

25 Single-port 64 x 1-bit RAM

26 Dual-port 64 x 1 RAM

27 Total Size of Distributed RAM

28 FPGA Block RAM

29 Block RAM-or Embedded RAM Most efficient memory implementation Dedicated blocks of memory Ideal for most memory requirements 4 to 104 memory blocks 18 kbits = 18,432 bits per block (16 k without parity bits) Use multiple blocks for larger memories Builds both single and true dual-port RAMs Synchronous write and read (different from distributed RAM) Port A Spartan-3 Dual-Port Block RAM Port B Block RAM

30 RAM Blocks and Multipliers in Xilinx FPGAs

31 Spartan-6 Block RAM Amounts

32 0 Block RAM can have various configurations 1(port aspect ratios) k x 2 4k x 4 4,095 16k x 1 8, k x (8+1) 16, x (16+2)

33 Block RAM Port Aspect Ratios

34 Block RAM Interface

35 Block RAM Ports

36 Inferring is the (recognized) automatically generated logic by the tool that you didn t describe specifically instantiation is the tool generated logic which is described by you

37 Inferred RAM

38 Distributed vs Block RAMs Distributed RAM: must be used for RAM descriptions with asynchronous (data is read from memory as soon as the address is given, doesn't wait for the clock edge) read. Block RAM: generally used for RAM descriptions with synchronous read. Synchronous write for both Distributed and Block RAMs (data is written to RAM only happens at rising edge of clock). Any size and data width are allowed in RAM descriptions. - Depending on resource availability Up to two write ports are allowed.

39 Distributed vs Block RAMs Examples: 1. Distributed RAM with asynchronous read 2. Distributed RAM with "false" synchronous read 3. Block RAM with synchronous read 4. Distributed dual-port RAM with asynchronous read More RAM examples from XST Coding Guidelines: ode.html

40 Distributed RAM with asynchronous read

41 Distributed RAM with asynchronous read LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.all; entity raminfr is generic (bits : integer := 32; -- number of bits per RAM word addr_bits : integer := 3); -- 2^addr_bits = number of words in RAM port (clk : in std_logic; we : in std_logic; a : in std_logic_vector(addr_bits-1 downto 0); di : in std_logic_vector(bits-1 downto 0); do : out std_logic_vector(bits-1 downto 0)); end raminfr;

42 Distributed RAM with asynchronous read architecture behavioral of raminfr is type ram_type is array (2**addr_bits-1 downto 0) of std_logic_vector (bits-1 downto 0); signal RAM : ram_type; begin process (clk) begin if (clk'event and clk = '1') then if (we = '1') then RAM(conv_integer(unsigned(a))) <= di; end if; end if; end process; do <= RAM(conv_integer(unsigned(a))); end behavioral;

43 Report from Implementation Design Summary: Number of errors: 0 Number of warnings: 0 Logic Utilization: Logic Distribution: Number of occupied Slices: 16 out of 768 2% Number of Slices containing only related logic: 16 out of % Number of Slices containing unrelated logic: 0 out of 16 0% *See NOTES below for an explanation of the effects of unrelated logic Total Number of 4 input LUTs: 32 out of 1,536 2% Number used as 16x1 RAMs: 32 Number of bonded IOBs: 69 out of % Number of GCLKs: 1 out of 8 12%

44 Distributed RAM with "false" synchronous read

45 Distributed RAM with "false" synchronous read LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.all; entity raminfr is generic ( bits : integer := 32; -- number of bits per RAM word addr_bits : integer := 3); -- 2^addr_bits = number of words in RAM port (clk : in std_logic; we : in std_logic; a : in std_logic_vector(addr_bits-1 downto 0); di : in std_logic_vector(bits-1 downto 0); do : out std_logic_vector(bits-1 downto 0)); end raminfr;

46 Distributed RAM with "false" synchronous read architecture behavioral of raminfr is type ram_type is array (2**addr_bits-1 downto 0) of std_logic_vector (bits-1 downto 0); signal RAM : ram_type; begin process (clk) begin if (clk'event and clk = '1') then if (we = '1') then RAM(conv_integer(unsigned(a))) <= di; end if; do <= RAM(conv_integer(unsigned(a))); end if; end process; end behavioral;

47 Report from Implementation Design Summary: Number of errors: 0 Number of warnings: 0 Logic Utilization: Number of Slice Flip Flops: 32 out of 1,536 2% Logic Distribution: Number of occupied Slices: 16 out of 768 2% Number of Slices containing only related logic: 16 out of % Number of Slices containing unrelated logic: 0 out of 16 0% *See NOTES below for an explanation of the effects of unrelated logic Total Number of 4 input LUTs: 32 out of 1,536 2% Number used as 16x1 RAMs: 32 Number of bonded IOBs: 69 out of % Number of GCLKs: 1 out of 8 12% Total equivalent gate count for design: 4,355

48 Block RAM with synchronous read (read through) The following description implements a true synchronous read. A true synchronous read is the synchronization mechanism in Virtex device block RAMs, where the read address is registered on the RAM clock edge. Such descriptions are directly mappable onto block RAM, as shown in the diagram below.

49 Block RAM with synchronous read (read through) LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.all; entity raminfr is generic ( bits : integer := 32; -- number of bits per RAM word addr_bits : integer := 3); -- 2^addr_bits = number of words in RAM port (clk : in std_logic; we : in std_logic; a : in std_logic_vector(addr_bits-1 downto 0); di : in std_logic_vector(bits-1 downto 0); do : out std_logic_vector(bits-1 downto 0)); end raminfr;

50 Block RAM with synchronous read (read through) cont'd architecture behavioral of raminfr is type ram_type is array (2**addr_bits-1 downto 0) of std_logic_vector (bits-1 downto 0); signal RAM : ram_type; signal read_a : std_logic_vector(addr_bits-1 downto 0); begin process (clk) begin if (clk'event and clk = '1') then if (we = '1') then RAM(conv_integer(unsigned(a))) <= di; end if; read_a <= a; end if; end process; do <= RAM(conv_integer(unsigned(read_a))); end behavioral;

51 Report from Implementation Design Summary: Number of errors: 0 Number of warnings: 0 Logic Utilization: Logic Distribution: Number of Slices containing only related logic: 0 out of 0 0% Number of Slices containing unrelated logic: 0 out of 0 0% *See NOTES below for an explanation of the effects of unrelated logic Number of bonded IOBs: 69 out of % Number of Block RAMs: 1 out of 4 25% Number of GCLKs: 1 out of 8 12%

52 Distributed dual-port RAM with asynchronous read

53 Distributed dual-port RAM with asynchronous read library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity raminfr is generic ( bits : integer := 32; -- number of bits per RAM word addr_bits : integer := 3); -- 2^addr_bits = number of words in RAM port (clk : in std_logic; we : in std_logic; a : in std_logic_vector(addr_bits-1 downto 0); dpra : in std_logic_vector(addr_bits-1 downto 0); di : in std_logic_vector(bits-1 downto 0); spo : out std_logic_vector(bits-1 downto 0); dpo : out std_logic_vector(bits-1 downto 0)); end raminfr;

54 Distributed dual-port RAM with asynchronous read architecture syn of raminfr is type ram_type is array (2**addr_bits-1 downto 0) of std_logic_vector (bits-1 downto 0); signal RAM : ram_type; begin process (clk) begin if (clk'event and clk = '1') then if (we = '1') then RAM(conv_integer(unsigned(a))) <= di; end if; end if; end process; spo <= RAM(conv_integer(unsigned(a))); dpo <= RAM(conv_integer(unsigned(dpra))); end syn;

55 Report from Implementation Design Summary: Number of errors: 0 Number of warnings: 0 Logic Utilization: Logic Distribution: Number of occupied Slices: 32 out of 768 4% Number of Slices containing only related logic: 32 out of % Number of Slices containing unrelated logic: 0 out of 32 0% *See NOTES below for an explanation of the effects of unrelated logic Total Number of 4 input LUTs: 64 out of 1,536 4% Number used for Dual Port RAMs: 64 (Two LUTs used per Dual Port RAM) Number of bonded IOBs: 104 out of % Number of GCLKs: 1 out of 8 12%

56 Specification of memory types recognized by Synplify Pro program! SIGNAL memory : vector_array; Block RAM Memory: attribute syn_ramstyle : string; attribute syn_ramstyle of memory : signal is "block_ram"; LUT-based Distributed Memory: attribute syn_ramstyle : string; attribute syn_ramstyle of memory : signal is select_ram";

57 Block RAM Initialization Example 1 type ram_type is array (0 to 127) of std_logic_vector(15 downto 0); signal RAM : ram_type := (others => ; Example 2 type ram_type is array (0 to 127) of std_logic_vector(15 downto 0); signal RAM : ram_type := (others => (others => 1 )); Example 3 type ram_type is array (0 to 127) of std_logic_vector(15 downto 0); signal RAM : ram_type := (196 downto 100 => X B9B5, others => X 3344 );

58 Block RAM Initialization from a File rams_20c.data:

59 Generic Inferred ROM

60 Distributed dual-port ROM with asynchronous read LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.all; entity rominfr is generic ( bits : integer := 10; -- number of bits per ROM word addr_bits : integer := 3); -- 2^addr_bits = number of words in ROM port (a : in std_logic_vector(addr_bits-1 downto 0); do : out std_logic_vector(bits-1 downto 0)); end rominfr;

61 Distributed dual-port ROM with asynchronous read architecture behavioral of rominfr is type rom_type is array (2**addr_bits-1 downto 0) of std_logic_vector (bits-1 downto 0); constant ROM : rom_type := (" ", " ", " ", " ", " ", " ", " ", " "); begin do <= ROM(conv_integer(unsigned(a))); end behavioral;

62 Report from Synthesis Resource Usage Report for rominfr Mapping to part: xc3s50pq208-5 Cell usage: VCC 1 use LUT2 2 uses LUT3 7 uses I/O ports: 13 I/O primitives: 13 IBUF 3 uses OBUF 10 uses I/O Register bits: 0 Register bits not including I/Os: 0 (0%) Mapping Summary: Total LUTs: 9 (0%)

63 Report from Implementation Design Summary: Number of errors: 0 Number of warnings: 0 Logic Utilization: Number of 4 input LUTs: 9 out of 1,536 1% Logic Distribution: Number of occupied Slices: 5 out of 768 1% Number of Slices containing only related logic: 5 out of 5 100% Number of Slices containing unrelated logic: 0 out of 5 0% *See NOTES below for an explanation of the effects of unrelated logic Total Number of 4 input LUTs: 9 out of 1,536 1% Number of bonded IOBs: 13 out of %

64 FPGA specific memories (Instantiation)

65 RAM 16x1 (1) library IEEE; use IEEE.STD_LOGIC_1164.all; library UNISIM; use UNISIM.all; entity RAM_16X1_DISTRIBUTED is port( CLK : in STD_LOGIC; WE : in STD_LOGIC; ADDR : in STD_LOGIC_VECTOR(3 downto 0); DATA_IN : in STD_LOGIC; DATA_OUT : out STD_LOGIC ); end RAM_16X1_DISTRIBUTED;

66 RAM 16x1 (2) architecture RAM_16X1_DISTRIBUTED_STRUCTURAL of RAM_16X1_DISTRIBUTED is -- part used by the synthesis tool, Synplify Pro, only; -- ignored during simulation attribute INIT : string; attribute INIT of RAM_16x1s_1: label is "0000 ; component ram16x1s generic( INIT : BIT_VECTOR(15 downto 0) := X"0000"); port( O : out std_ulogic; -- note std_ulogic not std_logic A0 : in std_ulogic; A1 : in std_ulogic; A2 : in std_ulogic; A3 : in std_ulogic; D : in std_ulogic; WCLK : in std_ulogic; WE : in std_ulogic); end component;

67 RAM 16x1 (3) begin RAM_16x1s_1: ram16x1s generic map (INIT => X"0000") port map (O => DATA_OUT, A0 => ADDR(0), A1 => ADDR(1), A2 => ADDR(2), A3 => ADDR(3), D => DATA_IN, WCLK => CLK, WE => WE ); end RAM_16X1_DISTRIBUTED_STRUCTURAL;

68 RAM 16x8 (1) library IEEE; use IEEE.STD_LOGIC_1164.all; library UNISIM; use UNISIM.all; entity RAM_16X8_DISTRIBUTED is port( CLK : in STD_LOGIC; WE : in STD_LOGIC; ADDR : in STD_LOGIC_VECTOR(3 downto 0); DATA_IN : in STD_LOGIC_VECTOR(7 downto 0); DATA_OUT : out STD_LOGIC_VECTOR(7 downto 0) ); end RAM_16X8_DISTRIBUTED;

69 RAM 16x8 (2) architecture RAM_16X8_DISTRIBUTED_STRUCTURAL of RAM_16X8_DISTRIBUTED is -- part used by the synthesis tool, Synplify Pro, only; -- ignored during simulation attribute INIT : string; attribute INIT of RAM_16x1s_1: label is "0000"; component ram16x1s generic( INIT : BIT_VECTOR(15 downto 0) := X"0000"); port( O : out std_ulogic; A0 : in std_ulogic; A1 : in std_ulogic; A2 : in std_ulogic; A3 : in std_ulogic; D : in std_ulogic; WCLK : in std_ulogic; WE : in std_ulogic); end component;

70 RAM 16x8 (3) begin GENERATE_MEMORY: for I in 0 to 7 generate RAM_16x1_S_1: ram16x1s generic map (INIT => X"0000") port map (O => DATA_OUT(I), A0 => ADDR(0), A1 => ADDR(1), A2 => ADDR(2), A3 => ADDR(3), D => DATA_IN(I), WCLK => CLK, WE => WE ); end generate; end RAM_16X8_DISTRIBUTED_STRUCTURAL;

71 ROM 16x1 (1) library IEEE; use IEEE.STD_LOGIC_1164.all; library UNISIM; use UNISIM.all; entity ROM_16X1_DISTRIBUTED is port( ADDR : in STD_LOGIC_VECTOR(3 downto 0); DATA_OUT : out STD_LOGIC ); end ROM_16X1_DISTRIBUTED;

72 ROM 16x1 (2) architecture ROM_16X1_DISTRIBUTED_STRUCTURAL of ROM_16X1_DISTRIBUTED is -- part used by the synthesis tool, Synplify Pro, only; -- ignored during simulation attribute INIT : string; attribute INIT of rom16x1s_1: label is "F0C1"; component ram16x1s generic( INIT : BIT_VECTOR(15 downto 0) := X"0000"); port( O : out std_ulogic; A0 : in std_ulogic; A1 : in std_ulogic; A2 : in std_ulogic; A3 : in std_ulogic; D : in std_ulogic; WCLK : in std_ulogic; WE : in std_ulogic); end component; signal Low : std_ulogic := '0';

73 ROM 16x1 (3) begin ); rom16x1s_1: ram16x1s generic map (INIT => X"F0C1") port map (O=>DATA_OUT, A0=>ADDR(0), A1=>ADDR(1), A2=>ADDR(2), A3=>ADDR(3), D=>Low, WCLK=>Low, WE=>Low end ROM_16X1_DISTRIBUTED_STRUCTURAL;

74 Block RAM library components Component Data Cells Parity Cells Address Bus Data Bus Parity Bus Depth Width Depth Width RAMB16_S (13:0) (0:0) - RAMB16_S (12:0) (1:0) - RAMB16_S (11:0) (3:0) - RAMB16_S (10:0) (7:0) (0:0) RAMB16_S (9:0) (15:0) (1:0) RAMB16_S (8:0) (31:0) (3:0)

75 Component declaration for BRAM (1) -- Component Declaration for RAMB16_S1 -- Should be placed after architecture statement but before begin component RAMB16_S1 -- synthesis translate_off generic ( INIT : bit_vector := X"0"; INIT_00 : bit_vector := X" "; INIT_3F : bit_vector := X" "; SRVAL : bit_vector := X"0"; WRITE_MODE : string := "WRITE_FIRST"); -- synthesis translate_on port (DO : out STD_LOGIC_VECTOR (0 downto 0) ADDR : in STD_LOGIC_VECTOR (13 downto 0); CLK : in STD_ULOGIC; DI : in STD_LOGIC_VECTOR (0 downto 0); EN : in STD_ULOGIC; SSR : in STD_ULOGIC; WE : in STD_ULOGIC); end component;

76 Genaral template of BRAM instantiation (1) -- Component Attribute Specification for RAMB16_{S1 S2 S4} -- Should be placed after architecture declaration but before the begin -- Put attributes, if necessary -- Component Instantiation for RAMB16_{S1 S2 S4} -- Should be placed in architecture after the begin keyword RAMB16_{S1 S2 S4}_INSTANCE_NAME : RAMB16_S1 -- synthesis translate_off generic map ( INIT => bit_value, INIT_00 => vector_value, INIT_01 => vector_value,.. INIT_3F => vector_value, SRVAL=> bit_value, WRITE_MODE => user_write_mode) -- synopsys translate_on port map (DO => user_do, ADDR => user_addr, CLK => user_clk, DI => user_di, EN => user_en, SSR => user_ssr, WE => user_we);

77 Initializing Block RAMs 1024x16 INIT_00 : BIT_VECTOR := X"014A0C0F09170A A A01C5020A A "; INIT_01 : BIT_VECTOR := X" A A A A0C0F03AA "; INIT_02 : BIT_VECTOR := X" "; INIT_03 : BIT_VECTOR := X" "; INIT_3F : BIT_VECTOR := X" ") DATA ADDRESS INIT_00 ADDRESS 014A 0F 0C0F 0E A INIT_01 ADDRESS F E 014A 14 0C0F 13 03AA INIT_3F ADDRESS 0000 FF 0000 FE Addresses are shown in red and data corresponding to the same memory location is shown in black 0000 F F F F F0

78 Component declaration for BRAM (2) VHDL Instantiation Template for RAMB16_S9, S18 and S36 -- Component Declaration for RAMB16_{S9 S18 S36} component RAMB16_{S9 S18 S36} -- synthesis translate_off generic ( INIT : bit_vector := X"0"; INIT_00 : bit_vector := X" "; INIT_3E : bit_vector := X" "; INIT_3F : bit_vector := X" "; INITP_00 : bit_vector := X" "; INITP_07 : bit_vector := X" "; SRVAL : bit_vector := X"0"; WRITE_MODE : string := "WRITE_FIRST"; );

79 Component declaration for BRAM (2) -- synthesis translate_on port (DO : out STD_LOGIC_VECTOR (0 downto 0); DOP : out STD_LOGIC_VECTOR (1 downto 0); ADDR : in STD_LOGIC_VECTOR (13 downto 0); CLK : in STD_ULOGIC; DI : in STD_LOGIC_VECTOR (0 downto 0); DIP : in STD_LOGIC_VECTOR (0 downto 0); EN : in STD_ULOGIC; SSR : in STD_ULOGIC; WE : in STD_ULOGIC); end component;

80 Genaral template of BRAM instantiation (2) -- Component Attribute Specification for RAMB16_{S9 S18 S36} -- Component Instantiation for RAMB16_{S9 S18 S36} -- Should be placed in architecture after the begin keyword RAMB16_{S9 S18 S36}_INSTANCE_NAME : RAMB16_S1 -- synthesis translate_off generic map ( INIT => bit_value, INIT_00 => vector_value, INIT_3F => vector_value, INITP_00 => vector_value, INITP_07 => vector_value SRVAL => bit_value, WRITE_MODE => user_write_mode) -- synopsys translate_on port map (DO => user_do, DOP => user_dop, ADDR => user_addr, CLK => user_clk, DI => user_di, DIP => user_dip, EN => user_en, SSR => user_ssr, WE => user_we);

81 Memory Organizations Shift Registers Synchronous Stores n words For each word input, one word is output data Exactly n words stored internally data clk

82 Memory Organizations LIBRARY ieee; USE ieee.std_logic_1164.all; USE work.app_types.all; ENTITY shift_register IS GENERIC( n : POSITIVE := 8 ); PORT( data_in : IN word; data_out : OUT word; clk : std_ulogic ;( END ENTITY shift_register; ARCHITECTURE a OF shift_register IS TYPE data_array IS ARRAY( 0 TO n-1 ) OF word; SIGNAL mem: data_array; BEGIN PROCESS( clk ) BEGIN IF clk'event AND clk = '1' THEN mem( mem'low ) <= data_in; data_out <= mem( mem'high ); FOR j IN 1 TO n-1 LOOP mem( j ) <= mem( j-1 ); END LOOP; END IF; END PROCESS; END a;

83 Memory Organizations First-In First-Out (FIFO) Stores n words Independent R and W ports Used for matching data rates Variants Synchronous Asynchronous Need full and empty flags Also commonly provide almost full, almost empty flags These allow a busy response to be sent to the provider (input) several cycles before the FIFO actually becomes full, eg we used it over the network in Achilles the receiver end FIFO sends busy when it s almost full back through the net to the sender. This may take several cycles, but the sender can safely continue to send. Similarly almost empty can tell the provider to wake up

84 LIBRARY ieee; USE ieee.std_logic_1164.all; USE work.app_types.all; ENTITY FIFO_asynch IS GENERIC( n : POSITIVE := 8 ); PORT( data_in : IN word; data_out : OUT word; rd, wr, reset : std_ulogic; full, empty : OUT std_ulogic ); END ENTITY FIFO_asynch; FIFO (synchronous) Model ARCHITECTURE a OF FIFO_asynch IS SUBTYPE index IS natural RANGE 0 TO n-1; TYPE data_array IS ARRAY( index'low TO index'high ) OF word; SIGNAL mem: data_array; SIGNAL read_ix, write_ix : index; BEGIN PROCESS( rd, wr ) VARIABLE r_ix, w_ix : natural := 0; BEGIN IF reset = '1' THEN read_ix <= 0; write_ix <= 0; ELSIF rd = '1' THEN IF ( read_ix /= write_ix ) THEN data_out <= mem( read_ix ); empty <= '0'; read_ix <= read_ix + 1; END IF; END IF; IF wr = '1' THEN IF ( read_ix /= write_ix ) THEN data_out <= mem( read_ix ); empty <= '0'; write_ix <= write_ix - 1; END IF; END IF; IF ( read_ix = write_ix ) THEN empty <= '1'; END IF; END PROCESS; END a;

85 Memory Organizations key Up to n words stored internally Content Addressable memory Dictionary style applications match Does the memory contain a given word? Ordinary memory requires O(n) time Each word is checked in turn Binary and tree searches can reduce this to O( log n ) Input : a search key one word of data Each location of memory is searched in parallel Indicates whether or not a match occurred in O( 1 ) time! Returns Either True / false = key found / not found or Index of (one) match Allows lookup of data in accompanying data table Expensive to implement Requires O(n) comparators for an n-word store search/ ~add

86 Example hardware implementation Content-addressable memory is often used in computer networking devices. For example, when a network switch receives a data frame from one of its ports, it updates an internal table with the frame's source MAC address and the port it was received on. It then looks up the destination MAC address in the table to determine what port the frame needs to be forwarded to, and sends it out on that port. The MAC address table is usually implemented with a binary CAM so the destination port can be found very quickly, reducing the switch's latency.

87 LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all;use work.app_types.all; ENTITY CAM IS GENERIC( n : POSITIVE := 8 ); PORT( key : IN word; found : OUT std_ulogic; search : IN std_ulogic; full : OUT std_ulogic; reset, clk : std_ulogic ); END ENTITY CAM; ARCHITECTURE a OF CAM IS TYPE data_array IS ARRAY( 0 TO n-1 ) OF word; SIGNAL mem: data_array; SIGNAL top : natural; BEGIN PROCESS( clk, reset ) VARIABLE match : BOOLEAN; BEGIN IF reset = '1' THEN top <= 0; full <= 0 ; ELSIF clk'event AND clk = '1' THEN IF search = '1' THEN -- Search mode match := FALSE; FOR j IN data_array'range LOOP match := key = mem( j ); END LOOP; IF match THEN found <= '1 ; ELSE found <= '0 ; END IF; ELSE -- Add a new entry IF top = data_array'high THEN full <= '1 ; ELSE top <= top + 1; mem( top ) <= key; END IF; END IF; END IF; END PROCESS; END a; CAM implementation

88 Memory Limitations Clearly these amounts are small for modern demands Example: Image processing A low resolution image 1000x1000 = 10 6 pixels 8 Mbits in B&W 24 Mbits in colour All large FPGAs now provide conventional memory blocks Some examples.

89 Some examples ispxga 1200 Block Memory or SysMEM 414K bits 90 Blocks of regular memory distributed throughout the device Each block (EBR) Dual port 256 x x 9 Quad port 512 x x 18 (using 2 blocks) FIFO 256 x x x 9 Content Addressable memory

90 Alternative memory creation Use Manufacturer s library components eg Altera LPM library : lpm_fifo, lpm_shiftreg, lpm_ram_dq, lpm_rom Memory generator programs Alteras mega-function wizard Xilinx CoreGen

91

92 LIBRARY altera_mf; USE altera_mf.altera_mf_components.all; ENTITY fff IS PORT ( address : IN STD_LOGIC_VECTOR (7 DOWNTO 0); END fff; ); clock : IN STD_LOGIC := '1'; data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); wren : IN STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)

93 ARCHITECTURE SYN OF fff IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); BEGIN q <= sub_wire0(7 DOWNTO 0); altsyncram_component : altsyncram GENERIC MAP ( clock_enable_input_a => "BYPASS", clock_enable_output_a => "BYPASS", intended_device_family => "Cyclone V", lpm_hint => "ENABLE_RUNTIME_MOD=NO", lpm_type => "altsyncram", numwords_a => 256, operation_mode => "SINGLE_PORT", outdata_aclr_a => "NONE", outdata_reg_a => "CLOCK0", power_up_uninitialized => "FALSE", read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", widthad_a => 8, width_a => 8, width_byteena_a => 1 ) PORT MAP ( address_a => address, clock0 => clock, data_a => data, wren_a => wren, q_a => sub_wire0 ); END SYN;

94 Still Not enough embedded RAM? External Memory Large FPGAs have 200+ I/O pins All configurable as IN or OUT Interfacing with external devices is straightforward Static RAM Not enough embedded RAM? FIFOs are particularly easy! Some manufacturers provide cores (packaged solutions) for SDRAM, DDRAM, etc Only problem You don t have quite the same flexibility when using an external memory chip(s) Size Data width