The FPGA: An Engine for Innovation in Silicon and Packaging Technology

Transcription

1 The FPGA: An Engine for Innovation in Silicon and Packaging Technology Liam Madden Corporate Vice President September 2 nd, 2014

2 The Zynq Book Embedded Processing with the ARM Cortex-A9 on the Xilinx Zynq All Programmable SoC Hands-on introduction to Zynq for: Technical/non-technical managers Hardware/software engineers Academics and students Book divided into three main sections 1) High level introduction to Zynq What is it? What can I do with it? How do I use it? 2) Technical overview Embedded system, Zynq, AXI, IP design, HLS, System Design (Vivado) 3) Operating systems for Zynq Background, Linux overview, Linux on Zynq Page 2

3 Free PDF of The Zynq Book From the book s website wwwzynqbookcom Same content as the hardcopy version of the book Also download tutorials and source files from website Open source license for academia Enables book contents to be re- used for non-commercial teaching and research Page 3

4 The Chameleon Chip Page 4

5 Moore s Law

6 Moore s Law 1965: Transistor density doubles every year 64K devices 10x doubling 64 devices 10 years Revised 1975: Transistor density doubles every two years Cramming more components onto integrated circuits Gordon Moore, Electronics, Volume 38, Number 8, April 19th 1965 Page 6

7 A Career in One Graph Minimum Feature Size 10um 1E-05 1um 1E nm 1E X 10nm 1E years 07 30/2 = nm 1E Page 7

8 Exponentials Are Tough to Grasp Ratio Gordon Moore #Transistors/die 64 6B 100M Minimum feature size ~76um 3mils 20nm 1/3800 Wafer diameter Wafer area Portable entertainment (songs) ~ Computer History Museum, Fairchild Semiconductor, IMEC, Norelco, Apple Computer

9 Node Name, Chip Dimensions or Marketing? 90nm Metal Half Pitch Node Name 65nm Metal Pitch Metal Half Pitch Gate Length 40nm 28nm 20nm 16/14nm IEEE Spectrum Nov 2013: The End of the Shrink 9

10 Real World Scaling

11 Driver Moore s Law is About Logic and Memory I/O Logic SerDes Inductor Bond pad ESD DCAP 11

12 AREA SCALING 330Mb/s 38Gb/s 1066Mb/s 66Gb/s 1866Mb/s 125Gb/s 2400Mb/s 32Gb/s Non-Uniform Block Scaling 100% 80% Logic/IO/GT Area Scaling Logic IO GT 60% 40% 20% 0% NODE 12

13 Mix Has Also Changed, Putting More Pressure on Area 100% 80% Logic/IO/GT Area Breakdown GT IO Area Scaling 60% 40% 20% Logic 0% NODE 13

14 AREA SCALING Area/Bandwidth Scaling a Different Story 100% 80% 60% Block Area Scaling (BW Normalised) Logic IO GT 40% 20% 0% NODE(nm) 14

15 What is Driving the Bandwidth Increase?

16 Cable Access Growth Exceeds Moore s Law (Nielsen s Law) Seoul, South Korea Menlo Park, CA 22X/2 years Page 16

17 Similar Story in USB, WLAN and Wireless 25X/2 years Page 17

18 Driven by Streaming Video HD 2-5Mb/s UHD 25Mb/s Page 18

19 How are FPGA s Responding?

20 klc s Maximum Density Of Xilinx FPGA By Node X/Node nm 40nm 28nm 20nm Node (nm) Page 20

21 Maximum Xilinx SerDes Rate (by Pin) X/Node nm 40nm 28nm 20nm Node (nm) Page 21

22 Tb/s Aggregate Xilinx SerDes Bandwidth by Node 10 23X/Node 03 5, nm 40nm Node (nm) 28nm 20nm 22

23 Mb/s High End PC Per Pin DDR Rate by Year X/Node Year 23

24 GB/s Aggregate Xilinx FPGA Memory BW by Node 512,0 HMC 256,0 25X/Node 128,0 16X/Node DDR Ivy Bridge (101) 64,0 Nehalem (51) Sandy Bridge (76) 32, nm 40nm 28nm 20nm Node (nm) 24

25 Normalized Growth Takeaways Xilinx LC counts have exceeded Moore s Law and are keeping up with Communications requirements SerDes aggregate bandwidth is keeping up with Comms growth I/O (in particular DRAM) aggregate bandwidth is falling behind Serial memory (HMC) is mitigating Interposer based memory (HBM) will further mitigate LC Count SerDes BW Comms BW HMC Moore DDR BW Page nm nm 28nm 20nm Node (nm)

26 3-D Stacking, Providing More Silicon Area at Lower Cost and Lower Power

27 Die Cost Cost Comparison: Monolithic vs Multi-Die Moore s Law is really about economics Gordon Moore Monolithic Multi-Die Die Area Page 27

28 Why is First 3D Logic Product an FPGA? Natural partition using long lines Very low opportunity cost No 3 rd party dependence Size matters to customers Compelling value proposition next generation density in this generation technology Page 28

29 Virtex 2000T: Homogeneous Stacked Silicon Interconnect Technology (SSIT) FPGA slice FPGA Slices Side-by-Side Silicon Interposer >10K routing connections between Silicon slices ~1ns latency Interposer Page 29

30 Elements of SSIT TSV C4 FPGA Interposer Microbumps 004mm Access to power / ground / IOs Microbumps Through-silicon Vias (TSV) Only bridge power / ground / IOs to C4 bumps 02mm Passive Silicon Interposer (65nm Generation) 4 conventional metal layers connect micro bumps & TSVs Side-by-Side Package Die Layout Minimal heat flux issues New! 28nm FPGA Slice 28nm FPGA Slice 28nm FPGA Slice 28nm FPGA Slice Microbumps Silicon Interposer Through-Silicon Vias Package Substrate Package Ball 1mm C4 Bumps BGA Balls Page 30

31 SSIT Saves Leakage Power 3X Monolithic Leakage SSIT <50% Process Distribution 31

32 3D Supply Chain FPGA, Interposer, & Package Design 28nm FPGA & Interposer Package Substrate IBIDEN Bump, Die separation CoC/CoWoS, & Assembly Final Test of Packaged Part

33 3-D Heterogeneous Integration, Solving Inter-chip Bandwidth and Power Limitations

34 3 Decades of Microprocessor Integration A Personal History Integrate or be integrated Fred Weber, former CTO AMD Year Company Product Integration Level Core L2$ DP Ctl L1 $ FPU North Bridge GPU 1983 Harris J11 4um 1989 DEC Rigel 15um 1991 DEC Alpha 075um 2005 Microsoft Xenon 3 Core 90nm 2011 AMD Fusion 2 Core 40nm Page 34

35 What Happened to System on a Chip? Logic Memory Analog Global Revenue 2013 $150B $68B $45B Moore Scaling Good Good Poor Technology Vintage 20nm 20nm 180nm? Transistor Characteristics High performance/ Low leakage Low leakage/ moderate performance Stable with good voltage headroom Metallization layers >9 <5 <6 Differentiators High density logic Charge storage Passives, Optical Page 35

36 m m What s the Problem with Multiple Packages? The packaging chasm Two orders difference in package trace/width vs silicon metallization I/O also isn t scaling due to bump pitch and chip to chip loading issues Leads to increased area, power and complexity (SERDES) 100 Pkg via diam Pkg trace width 240 Bump Pitch Si 10 Package Via Diameter Package Trace Width Chip Top Metal ~06 m 1 Chip top metal Signal Power Solder Bump Cu Pillar ~3 m ~100 m PKG To scale in X dimension Page 36

37 Chip Input/Output Bottleneck Source: ITRS 15x drop in I/O-to-logic ratio by 2020 Page 37

38 Crossing the Packaging Chasm Logic Process Memory Process Analog Process up Wide bus Wide bus DRAM Memory Analog FPGA Mem Analog Package Page 38

39 Interposer Optimizes Energy/Bit Interconnects Energy Efficiency (pj/bit) Inter-Die on Si Interposer 1 04 Intra-Package MCM Inter Package (low loss cable) 3 26 Short-Reach SerDes on PCB Xilinx SSI technology 2 233, ISSCC 2013 (Poulton, Dally, et al) ISSCC 2013 ((Mansuri et al) 4 Pawlowski, Hot Chips 23 ISSCC

40 SerDes Integration

41 Virtex-7 HT: Heterogeneous SerDes Top View Cross Section TSVs 28G SerDes Fabric Interface 28G FPGA FPGA FPGA 28G 13G FPGA 13G Passive Interposer 13G FPGA 13G Yield optimized 13G FPGA 13G Noise isolation 28G SerDes 28G process optimized for performance Passive Interposer 28Tb/s ~3X Monolithic FPGA process optimized for power 16 x 28G Transceivers 72 x 13G Transceivers 650 GPIO Page 41

42 7V580T Dual FPGA Slice with 8x28Gb/s SerDes Die Virtex-7 28Gbps Page 42

43 Simulated Eye Diagram and Measured Eye Diagram 28Gb/s Simulation Measurement Measured Amplitude: 923mVp-p Measured Total Jitter: 625 BER 10E-12 Measured Random Jitter: 230 fs (0175UI of total jitter) Page 43

44 SSIT Enables Scalable FPGAs XC7VH580T XC7VH870T GTZ-IC GTZ-IC GTH FPGA GTH GTH FPGA GTH GTH FPGA GTH GTH FPGA GTH GTH FPGA GTH GTZ-IC Network 2 x 100G 1 x 400G or 4 x 100G GTZ (28G) 8 16 GTH (13G) Logic Cells 580K 876K Page 44

45 Heterogeneous ADC/DAC Integration

46 ADC BW Requirements Exploding Multi Channel Array of ADCs FPGAs Ultrasound Transducer FPGA 256 channels 32 x 8 channel 384Gb/s 3D real time for complex 12b x 125Ms/s ADCs raw data imaging beamforming 46

47 Power (mw) ADC I/O Power Not Scaling ADC cores are significantly more power efficient than previous implementations I/O power not scaling MS/s 14 bit (eq) ADC core power (mw) ADC Chip 1000 Core I/O 100 I/O Power 10 47

48 Test Vehicle Integrating ADC/DAC 1156-BGA 35x35mm 2 x FPGA slices DAC 125Gsps CLN65LP 16 channels 214mm 8 16x12 4 8x64 FPGA Slice 35mm 125GSPS 14-bit resolution ADC FPGA Slice CLN65LP 2-16 channels 246mm 125MSPS-1GSPS / channels 12-bit resolution 35mm 48

49 Noise voltage (μvrms) FPGA Power (W) World Class Digital Noise Immunity Up to 14W of switching power 1000 Analog die isolation from FPGA noise Clock related noise Data related noise Digital power ,000,000 x Analog die 0, FPGA clock (MHz) 0 Interposer shows outstanding isolation from massive digital noise to sensitive analog circuitry (up to 1,000,000 x) 49

50 HBM Memory Integration

51 HBM DRAM 0 HBM DRAM 1 High Bandwidth Integrated Memory Higher memory bandwidth at lower power 1Tbps 2Tbps ~1Gb/s per interposer wire Simple extension of existing work FPGA FPGA Die FPGA 0 FPGA 1 PKG Page 51

52 And Future Will be More Challenging

53 Cost Per Transistor is Saturating Defectivity Driven? Complexity Driven

54 Industry Slowdown to 25 years/node Reasons may be technical or business, either way pace is slowing Intel vs Ideal Moore s Law 32 Node (nm) 22 Ideal Moore s Law Intel CPU Production Year Page 54

55 Summary 3-D Stacking has been instrumental in mitigating cost and power challenges Bandwidth demand will continue to exceed traditional Moore s Law capabilities FPGA s will need to continue leading the industry in novel solutions to challenging problems Page 55

56 Thank You Questions? Page 56