Advanced Digital Logic Design EECS 303

Transcription

1 dvanced igital Logic esign S Teacher: Robert ick Office: L477 Tech mail: dickrp@northwestern.edu Phone:

2 Today s topics inate covering Tree mapping rithmetic circuits Number systems dders 2 Robert ick dvanced igital Logic esign

3 Outline Robert ick dvanced igital Logic esign

4 Section outline 1. 4 Robert ick dvanced igital Logic esign

5 We know how to minimize two-level and multi-level logic Generally expressed in terms of simple gates, e.g., NN2s and NOTs Need to map to efficient implementation in target technology Target technology consists of a set of gates ach has area, power consumption, and timing properties Map to those gates minimizing some combination of area, power, and delay 5 Robert ick dvanced igital Logic esign

6 Given: Simplified and decomposed (reduced) logic graph (G) Tree makes things easier omposed of NOT and NN2 gates Library: NOT, NN2, NN3, NOR4 (O4), and XNOR gates ecide minimal area/delay/power cost mapping from logic tree to technology library 6 Robert ick dvanced igital Logic esign

7 Given: Simplified and decomposed (reduced) logic graph (G) Tree makes things easier omposed of NOT and NN2 gates Library: NOT, NN2, NN3, NOR4 (O4), and XNOR gates ecide minimal area/delay/power cost mapping from logic tree to technology library 6 Robert ick dvanced igital Logic esign

8 example library gate area cost NOT 1 NN2 2 NN3 3 NN4 4 XNOR2 5 NOR4 4 7 Robert ick dvanced igital Logic esign

9 Potentially overlapping maps 8 Robert ick dvanced igital Logic esign

10 Potentially overlapping maps 8 Robert ick dvanced igital Logic esign

11 Potentially overlapping maps 8 Robert ick dvanced igital Logic esign

12 Potentially overlapping maps 8 Robert ick dvanced igital Logic esign

13 Potentially overlapping maps 8 Robert ick dvanced igital Logic esign

14 Section outline 1. 9 Robert ick dvanced igital Logic esign

15 for area as binate covering ind all possible matches However, complete cover insufficient Need match outputs to align with inputs of other matches an represent problem as binate covering 10 Robert ick dvanced igital Logic esign

16 inate covering term column J 1 1 J J J J ind a set of columns, S, such that, for every row 1-colum in the row is in S or a 0-column in the row is not in S 11 Robert ick dvanced igital Logic esign

17 G mapping binate covering formulation 12 Robert ick dvanced igital Logic esign

18 G mapping binate covering formulation 12 Robert ick dvanced igital Logic esign

19 G mapping binate covering formulation 12 Robert ick dvanced igital Logic esign

20 G mapping binate covering formulation 12 Robert ick dvanced igital Logic esign

21 G mapping binate covering formulation 12 Robert ick dvanced igital Logic esign

22 G mapping binate covering formulation (J K) (K J) (K L N) (L K) (N K) 13 Robert ick dvanced igital Logic esign

23 G mapping binate covering formulation (J K) (K J) (K L N) (L K) (N K) 13 Robert ick dvanced igital Logic esign

24 G mapping binate covering formulation Q R S (J K) (K J) (K L N) (L K) (N K) 13 Robert ick dvanced igital Logic esign

25 G mapping binate covering formulation M N Q J K R S L (J K) (K J) (K L N) (L K) (N K) 13 Robert ick dvanced igital Logic esign

26 G mapping binate covering formulation Outputs feed directly into next gate s inputs (J K) (K J) (K L N) (L K) (N K) lso ensure primary outputs are available (omitted from example) constraint gate J K L M N Q 1 1 R 1 1 S J K 0 1 K J 1 0 K L N L K 1 0 N K Robert ick dvanced igital Logic esign

27 Problems with binate covering lthough there are good heuristics to speed up unate covering, binate covering appears to be a harder problem Intractable for large problem instances ost function must be independent of other portions of solution an use area but can t use delay or power an use a fast alternative for tree, not G covering 15 Robert ick dvanced igital Logic esign

28 Section outline Robert ick dvanced igital Logic esign

29 Tree covering Split G at multiple output nodes to form trees Optimally and quickly map trees using dynamic programming Reconnect result into a G Locally improve connection points Result: Nearly (but not quite) optimal, fast G mapping 17 Robert ick dvanced igital Logic esign

30 for area complexity Reduced logic tree RLT = (V, ) Technology library with T gates Maximum gate size of S, i.e., no gate covers more than S vertices lgorithm is Linear in V Linear in T xponential in S 18 Robert ick dvanced igital Logic esign

31 Tree technology mapping for area (detailed) 19 Robert ick dvanced igital Logic esign

32 Tree technology mapping for area (detailed) 19 Robert ick dvanced igital Logic esign

33 Tree technology mapping for area (detailed) 19 Robert ick dvanced igital Logic esign

34 Tree technology mapping for area (detailed) 2 NN2(2) + NOT (1) = 5 or NN3(3) = 3 19 Robert ick dvanced igital Logic esign

35 Tree technology mapping for area (detailed) 2 NN2(2) + NOT (1) = 5 or NN3(3) = 3 19 Robert ick dvanced igital Logic esign

36 Tree technology mapping for area (detailed) 19 Robert ick dvanced igital Logic esign

37 Tree technology mapping for area (detailed) 19 Robert ick dvanced igital Logic esign

38 Tree technology mapping for area (detailed) 19 Robert ick dvanced igital Logic esign

39 Tree technology mapping for area (detailed) 2 NN2(2) + NOT (1) = 5 or NN3(3) = 3 cached 19 Robert ick dvanced igital Logic esign

40 Tree technology mapping for area (detailed) 2 NN2(2) + NOT (1) = 5 or NN3(3) = 3 cached 19 Robert ick dvanced igital Logic esign

41 Tree technology mapping for area (detailed) 19 Robert ick dvanced igital Logic esign

42 Tree technology mapping for area (detailed) 2 NN3(3) + NN2(2) = 8 or 2 NN2(2) + 2 NOT (1) + NOR4(4) = Robert ick dvanced igital Logic esign

43 Tree technology mapping for area (detailed) 2 NN3(3) + NN2(2) = 8 or 2 NN2(2) + 2 NOT (1) + NOR4(4) = Robert ick dvanced igital Logic esign

44 Tree technology mapping for area (detailed) 19 Robert ick dvanced igital Logic esign

45 Tree technology mapping for area (detailed) 19 Robert ick dvanced igital Logic esign

46 Tree technology mapping for area (detailed) 19 Robert ick dvanced igital Logic esign

47 Tree technology mapping for area (detailed) 19 Robert ick dvanced igital Logic esign

48 Tree technology mapping for area (detailed) 19 Robert ick dvanced igital Logic esign

49 Tree technology mapping for area (detailed) 3 NN2(2) = 6 or NOR4(4) = 4 19 Robert ick dvanced igital Logic esign

50 Tree technology mapping for area (detailed) 3 NN2(2) = 6 or NOR4(4) = 4 19 Robert ick dvanced igital Logic esign

51 Tree technology mapping for area (detailed) 19 Robert ick dvanced igital Logic esign

52 Tree technology mapping for area (detailed) 3 NOT (1) + NOR4(4) = 7 or XNOR2(5) = 5 19 Robert ick dvanced igital Logic esign

53 Tree technology mapping for area (detailed) 3 NOT (1) + NOR4(4) = 7 or XNOR2(5) = 5 19 Robert ick dvanced igital Logic esign

54 Tree technology mapping for area (detailed) 19 Robert ick dvanced igital Logic esign

55 Tree technology mapping for area (detailed) XNOR2(5) + NN2(2) = 7 or 2 NOT (1) + 2 NN2(2) + NN3(3) = 9 19 Robert ick dvanced igital Logic esign

56 Tree technology mapping for area (detailed) XNOR2(5) + NN2(2) = 7 or 2 NOT (1) + 2 NN2(2) + NN3(3) = 9 19 Robert ick dvanced igital Logic esign

57 Tree technology mapping for area (detailed) 19 Robert ick dvanced igital Logic esign

58 Tree technology mapping for area (detailed) 19 Robert ick dvanced igital Logic esign

59 Tree technology mapping for area (detailed) 2 NN3(3) + XNOR2(5) + 2 NN2(2) = Robert ick dvanced igital Logic esign

60 for speed If each gate had a different constant delay, could use simple dynamic programming algorithm This works pretty well but is suboptimal However, each gate s speed depends on next gate s input load 20 Robert ick dvanced igital Logic esign

61 for speed If each gate had a different constant delay, could use simple dynamic programming algorithm This works pretty well but is suboptimal However, each gate s speed depends on next gate s input load V a z b V SS 20 Robert ick dvanced igital Logic esign

62 Two-pass delay optimization Problem: Optimize area under timing constraint 1 ind the set of all possible pin-loads 2 rom leafs, build array of minimal-area solutions, one for each pin-load 3 alculate the arrival time for each possible mapping (pin-load) 4 or each point, select the optimal area solution for each pin-load 5 Propagate optimal solution backwards from output load Note, that this isn t efficient given a large number of pin-loads iscretize 21 Robert ick dvanced igital Logic esign

63 re circuits really trees? What happens when they are not? 22 Robert ick dvanced igital Logic esign

64 Section outline Robert ick dvanced igital Logic esign

65 for technology mapping Start from an arbitrary G of gates Want canonical G for technology mapping.g., NN2 gates only NN2 with inputs tied is a NOT However, decomposition is not unique 24 Robert ick dvanced igital Logic esign

66 N4 NN2 25 Robert ick dvanced igital Logic esign

67 N4 NN2 25 Robert ick dvanced igital Logic esign

68 N4 NN2 25 Robert ick dvanced igital Logic esign

69 Non-canonical decomposition ould decide to allow more complex gates in subject G However, little opportunity for optimization Instead, consider all equivalent mappings for each library gate an t consider numerous subject G omplexity exponential Restated: Store many matches for each library gate but use only one subject G decomposition 26 Robert ick dvanced igital Logic esign

70 Notes on optimality It is common for algorithm designers to come up with elegant and optimal algorithms Look closely at their assumptions! It is often, first, necessary to formulate a problem in a simplified form to arrive at an optimal solution n optimal solution to the simplified form is not necessarily an optimal solution to the original problem 27 Robert ick dvanced igital Logic esign

71 Notes on optimality The technology mapping algorithms in this lecture are polynomial-time (fast) and optimal however, they aren t polynomial-time (fast) in every term Maximum library gate size... or optimal for the original problem The original problem can be a G, instead of a tree The decomposition is not unique etter solutions might be possible for other decompositions 28 Robert ick dvanced igital Logic esign

72 Notes on optimality The algorithms are high-quality and efficient However They are only optimal with respect to the simplified inputs They are only polynomial in the most important terms This situation is very common in / because the original problems are often N P-complete Too slow to solve for large problem instances Whenever you see or use the word optimal, think very carefully about what is meant 29 Robert ick dvanced igital Logic esign

73 summary is taking a set of functions and determining how to implement them using gates from a library Optimal and fast approaches exist for trees However, no optimal solution is known for arbitrary circuit topologies This is what you are doing when you type map in SIS 30 Robert ick dvanced igital Logic esign

74 Next lecture Multipliers and LUs Sequential logic networks Latches (RS Latch) lip-flops ( and JK) Timing issues (setup and hold times) 31 Robert ick dvanced igital Logic esign

75 Outline Robert ick dvanced igital Logic esign

76 Reading assignment M. Morris Mano and harles R. Kime. Logic and omputer esign undamentals. Prentice-Hall, NJ, third edition, 2004 hapter 5 33 Robert ick dvanced igital Logic esign