Anatomy of a Post PC Device. Prof. S.E Thompson EEE4310/5322 Fall 2017

Transcription

1 Anatomy of a Post PC Device iphone 7 Samsung Galaxy S8 Prof. S.E Thompson EEE4310/5322 Fall 2017

2 Modern Computer or Mobile Computer? Samsung Galaxy S8 2 More than mobile computer - Robotics - Drones - Future laptops?

3 Logic, DRAM, NAND, Power Management, Analog/RF Iphone 7 X NAND Flash memory 3 Printed Circuit Boards: mechanically supports and electrically connects electronic components - etched copper sheets laminated onto non-conductive substrate - FR-4 glass epoxy (fibre Reinforced plastic)

4 Cost Per Bit of Storage in Mobile Computer: SRAM, DRAM, NAND Memory Memory Unit Cell Area SRAM 6 Transistors ~(60 80) f 2 DRAM 1 Transistor 1 Capacitor ~6 f 2 NAND 1 Transistor ~2 f 2 Why is 3 different types of memory needed in a computer? f = feature size Cost ~ area but only if processed wafer cost the same Other attributes: read/write speed/power, endurance, dynamic vs static, volatile vs nonvolitle 4

5 System On A Chip (SOC) Chip becomes a system Chip includes processors, memory, ASIC, Analog I/O + more Software Complexity Test Why did SOC start in mobile computing? space and cost 5 Source: Dimas Ruliandi: System on Chip Design, Architecture and Applications

6 System On A Chip: SOC: Space and Cost Vs SoC vs. CPU The battle for the future of computing DDR3/PCI Express signals vs on SOC 6

7 History of Computing 7 Source: Pushkar Ranade and Scott Thompson, SuVolta Inc.

8 iphone: SOC / Baseband On Same PCB Iphone 5S Logic Board Source: ifixit 8

9 Samsung S8 Chips/Cost Memory - Leading edge feature size 9 Application processor/modems - Leading edge feature size - often on same chip

10 iphone 1: 2007 Leading Edge ~ 90nm Camera: 2.0 MP with geotagging Processor: Apple-branded 412 MHz 32-bit Samsung ARM 11 with PowerVR MBX-Lite GPU Specified by Apple and manufactured by Samsung Single ARM CPU Samsung 90nm RAM: 128 MB edram Sold 6.1million units Storage 4, 8 or 16GB G about 1 billion 8bits in 1 Byte ~ 2bits per 1 transistor Data input: Multi-touch touchscreen 10 Homework: read by next class Intel s From Sand to Circuits in week 1 e-learning

11 90nm Silicon Gate Transistor (TSMC) TEM image Silicon gate technology Poly-Silicon Self-aligned Source/drain + Speed + Reliability + Density Key metrics Contact to gate pitch Transistor size ~90nm Silicide Metal on source/drain/gate W contacts Cu wires 11 Source: chipworks

12 History: Bell Labs First Insulated Gate Field Effect Transistor (FET) First Transistor 1947 (Shockley/Bardeen/Brattain) FET Demonstrated in 1959 But anticipated in Lilienfeld s 1926 patent Fabrication challenge Surface state challenge Thermally grown SiO2 provided good interface Why Si vs Ge or GaN or GaAs? 12

13 History: Complementary MOS (CMOS Invented 1963) N and P type transistors Allows low leakage circuits Required for VLSI N and P transistor network between supply and ground. One type always off 13

14 History: Invention of Integrated Circuit ~1959 There is no consensus on who invented the IC. The American press of the 1960s named four people: Kilby, Lehovec, Noyce and Hoerni Electronic circuits on single device patents in 1950 s 1970s the list was shortened to Kilby and Noyce, and then to Kilby, who was awarded the 2000 Nobel Prize in Physics "for his part in the invention of the integrated circuit ss Noyce: 1959 planar integrated circuit 14 Source: wikipedi Logical NOR IC from Apollo spacecraft

15 15 Read Intel s Tutorial

16 Pattern Transfer to Wafer Allows local Etch Ion implant (electrical properties n or p Silicon) Fundamental processes to build microstructures Lithography Etch, Ion implant Diffusion Deposition Polish Theramal annealing Source: Intel 16

17 Post Chip Fabrication Wafer/Sort test Yield Functionality Wafer dicing Packaging 17

18 A7 (28nm) in iphone 5s (2013) Intel 32nm chip 18 PC class like computer? First 64bit chip to ship in a smartphone Over 1 Billion transistors Manufactured Samsung Ghz Why not wide range of CPU clock freq. like Intel CPU

19 Strained Si / Metal Gate 19 Conventional scaling of poly-si gate transistor prior to 90nm Dennard scaling theory (0.7X) 2X transistor density New manufacturing node every 2 or 3 years

20 A8 ( 20nm) in iphone 6 (2014) 20nm process TSMC and Samsung Twice the number of transistors of the A7 13% smaller physical chip size (89mm 2 ) R+Rogue+GPU+Clusters/article36586.htm 20

21 A9 (16nm) in iphone 6S (2015) Fabricated in 16nm FinFET / TSMC Fabricated 14nm FinFET / Samsung Samsung A Ghz A64 GPU (six Cores)

22 Introduction to FinFET Source Intel FinFET width =? 22

23 A10 (16nm) in iphone 7 (2016) A10 die size is ~125 sq. mm 3.3 billion transistors. TSMC 16FF-based 23

24 24

25 A11 in iphone 8 (2017) 10nm TSMC Estimate 100 million chips will be manufactured in 2017 Number of transistor? > 3 B 25

26 First 10nm in Samsung S8 Snapdragon 835 > 3B transistors In area < penny CPU/GPU/LTE/WiFi and more What does 10nm mean? 26

27 Top Down Circuit View of CMOS TSMC 28nm CMOS logic style N and P logic stacks 27

28 28 Type of Chips / Summary Chip Technology Some Metric SOC Baseband NAND Flash DRAM Image sensor NFC / Microcontrollers/ RF chips Power Amplifiers Motion sensors Power Switches Filters Leading edge logic - Minimum low V transistors / CMOS - Few 2.5/3.3 Analog I/O Metal Layers Leading edge memory - mimimum feature floating gate 1T Leading edge memory - minimum feature 1T1C ~65nm photo diode, plus capacitor and transistors ~65 to 130nm - Analog, RF, envm ~ >100 nm GaAs, GaN, SOI phemt or HBT ~ > 100nm Sensor category: Capacitive, Piezoelectric, Piezoresistive ~ >100nm GaAs, GaN, SOI PHEMT or HBT ~> 100nm Surface acoustic wave (SAW) filters Interleaved metal / piezoelectric substrate PMIC 65 to 180nm - BiCMOS Process technology High Voltage (5.0, 3.3, 2.5, 1.8V) Transistors, Analog Cost /transistor Digital logic Power Cost per NVM bit Cost per RAM bit Picture quality Cost Power (uw) Power added efficiency (PAE) Sense Acceleration or Rotation Loss Low insertion loss with good rejection High efficiency power conversions

29 NAND Memory in iphone 7 A true 3D chip 48 device layers 29

30 NAND FLASH Chip Basics Single NAND Flash transistor String of transistors (NAND circuit) 30

31 Program/Erase NAND Flash ~20V Source: How is 20V supplied inside a cell phone? 31

32 TEM NAND Flash: Samsung 90nm State of art planar NAND memory is 1x (nm) node. 2-3 bits per cell MLC) 32

33 Program and Inhibit SGD V high = 10V V high = 10V V high = 10V V high = 10V V PGM = 20V V high = 10V V high = 10V V high = 10V V high = 10V BL 0 BL 1 BL 2 BL 3 BL 4 8V 8V 8V 0V 8V WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 WL8 SGC Well = 0V Inhibit 20V 20V Program 33 8V 8V 0V 0V 0V

34 Read Number of Cells SGD V high = 7V V high = 7V BL 0 BL 1 BL 2 BL 3 BL 4 0V 0V 0V 1V 0V WL0 WL1 Erased Cells V high = 7V V high = 7V Programed Cells V READ = RAMP V high = 7V V high = 7V WL2 WL3 WL4 WL5 WL6 Threshold Voltage Logic 1 Logic 0 V high = 7V V high = 7V SGC WL7 WL8 Well = 0V I READ RAMP V 34

35 ERASE Erased Cells Number of Cells Threshold Voltage Programed Cells Logic 1 Logic 0 SGD V high = 0V V high = 0V V high = 0V V high = 0V V high = 0V V high = 0V V high = 0V V high = 0V V high = 0V SGC BL 0 BL 1 BL 2 BL 3 BL 4 Float Float Float Float Float WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 WL8 Well = 20V 0 V 35 20V

36 Block and Page BL 0 BL 1 BL 2 BL 3 BL 4 SGD WL0 Block WL1 Block size Some chips can set block to be SLC or MLC WL2 WL3 WL4 WL5 WL6 Page WL7 WL8 SGC 36 Page Buffer

37 Page / Block / Chip /Multi Chip in Package

38 3D NAND Memory NAND in iphone 7 Source: Andy Walker 38

39 39 2TB Solid State Drive How Many Transistors in Small Space?

40 40 Type of Chips / Summary Chip Technology Some Metric SOC Baseband NAND Flash DRAM Image sensor NFC / Microcontrollers/ RF chips Power Amplifiers Motion sensors Power Switches Filters Leading edge logic - Minimum low V transistors / CMOS - Few 2.5/3.3 Analog I/O Metal Layers Leading edge memory - mimimum feature floating gate 1T Leading edge memory - minimum feature 1T1C ~65nm photo diode, plus capacitor and transistors ~65 to 130nm - Analog, RF, envm ~ >100 nm GaAs, GaN, SOI phemt or HBT ~ > 100nm Sensor category: Capacitive, Piezoelectric, Piezoresistive ~ >100nm GaAs, GaN, SOI PHEMT or HBT ~> 100nm Surface acoustic wave (SAW) filters Interleaved metal / piezoelectric substrate PMIC 65 to 180nm - BiCMOS Process technology High Voltage (5.0, 3.3, 2.5, 1.8V) Transistors, Analog Cost /transistor Digital logic Power Cost per NVM bit Cost per RAM bit Picture quality Cost Power (uw) Power added efficiency (PAE) Sense Acceleration or Rotation Loss Low insertion loss with good rejection High efficiency power conversions

41 DRAM in Mobile Computer Iphone 5s Package on package PC uses DIMM 41

42 DRAM (Simple) V CC /2 42

43 Simple DRAM CELL VCC/2 43

44 DRAM (simple) Embedded DRAM in Microsoft Xbox GPU fabbed by TSMC (65-nm) 44 m/2014/02/intels-e-dram-shows-upin-wild.html

45 State Of The Art DRAM Cylinder cell since ~2005 Slowing of DRAM density 1x (nm) node in Source:

46 46 Type of Chips / Summary Chip Technology Some Metric SOC Baseband NAND Flash DRAM Image sensor NFC / Microcontrollers/ RF chips Power Amplifiers Motion sensors Power Switches Filters Leading edge logic - Minimum low V transistors / CMOS - Few 2.5/3.3 Analog I/O Metal Layers Leading edge memory - mimimum feature floating gate 1T Leading edge memory - minimum feature 1T1C ~40-65nm photo diode, plus capacitor and transistors ~65 to 130nm - Analog, RF, envm ~ >100 nm GaAs, GaN, SOI phemt or HBT ~ > 100nm Sensor category: Capacitive, Piezoelectric, Piezoresistive ~ >100nm GaAs, GaN, SOI PHEMT or HBT ~> 100nm Surface acoustic wave (SAW) filters Interleaved metal / piezoelectric substrate PMIC 65 to 180nm - BiCMOS Process technology High Voltage (5.0, 3.3, 2.5, 1.8V) Transistors, Analog Cost /transistor Digital logic Power Cost per NVM bit Cost per RAM bit Picture quality Cost Power (uw) Power added efficiency (PAE) Sense Acceleration or Rotation Loss Low insertion loss with good rejection High efficiency power conversions

47 47 iphone 6 Board (Camera)

48 48 CMOS Camera

49 Stacked Image Sensor Module Power Problem Image Sensor Analog Pixels Image Digital Co-Processor Lower power Lower heat dissipation Package Lower thermal envelope Thinner package Sony 8Mpixal in Iphone 5S Stacked die TSV Through silicon vias

50 Simple CMOS Image Pixel Reverse biased Photo diode Source: Chipworks BSI Back Side Image of Light use in high end phones (iphone, Galaxy, etc) An active-pixel sensor (APS) is an image sensor consisting of an integrated circuit containing an array of pixel sensors, each pixel containing a photodetector and an active amplifier.

51 How CMOS Does Colors

52 M7: Always On Logic Chip Logic chip but fabricated with slow but ultra low leakage transitor (very high threshold voltage) Initially old process node (>90nm) but now can be on SOC with specialty transistor 52

53 RFID Passive and active RFID tag Magnetic field also provides power. Store tag info in embedded NVM 53 Source:

54 Power Management IC Lithium cell voltage 3.7 ~3 V Manage, control and distribute and supply power voltages from the battery source to other corresponding circuits or chips. Convert, regulate, stabilize current and voltages Fabricated in older logic nodes with lots of added devices BJT, CMOS, DMOS (Double Diffused) Named BCD 54

55 Power Amplifiers Source: Chipworks Skyworks 5 Ghz power amp die Metrics: efficiency and linearity Best in high mobility semiconductors with large bandgap Fabricated at large feature size On chip high Q inductors Few different technology options: III-V-compound-based technologies (GaN, GaAs, SiC) and silicon-based (CMOS, BJT and SiGe-HBT) Si based technology has advantage for cost and integration with RF front-end Enhancement-mode MOSFETs and BJT 55 Source:

56 56 Future Trends?