WAFER PROBE AND PACKAGE TEST FAILURE ANALYSIS

Transcription

1 Clemson University TigerPrints All Theses Theses WAFER PROBE AND PACKAGE TEST FAILURE ANALYSIS Deepa Kalva Clemson University, Follow this and additional works at: Part of the Electrical and Computer Engineering Commons Recommended Citation Kalva, Deepa, "WAFER PROBE AND PACKAGE TEST FAILURE ANALYSIS" (2007). All Theses. Paper 258. This Thesis is brought to you for free and open access by the Theses at TigerPrints. It has been accepted for inclusion in All Theses by an authorized administrator of TigerPrints. For more information, please contact

2 WAFER PROBE AND PACKAGE TEST FAILURE ANALYSIS OF NAND FLASH MEMORY A Thesis Presented to the Graduate School of Clemson University In Partial Fulfillment of the Requirements for the Degree Master of Science Electrical and Computer Engineering by Deepa Kalva December 2007 Accepted by: Dr. William R. Harrell, Committee Chair Dr. Kelvin Poole Dr. Michael A. Bridgwood

3 ABSTRACT In recent years, NAND flash memory has gained a lot of momentum in the semiconductor industry and has become an ideal choice for many consumer and communication products. One of the key elements in the successful production of NAND flash memory is to incorporate elaborate testing methods to ensure functionality and reliability before the part reaches the customer. This in turn necessitates the evaluation and understanding of different failure mechanisms, and the development of methodologies to correct problems. In this thesis, failure analysis was performed on NAND flash memory at wafer and package level. This involved massive data collection and evaluation of failures at both the wafer level and package from several thousand parts using PERL scripts and software codes. In the process of analysis, a test for reading the flash memory resulted in unusually high failure rates at the package level. Failure data was collected in order to study the trends and correlations with various parameters such as applied voltage, the proximity of failures on a wafer, the cell characteristics of each failing die compared to good die, and the threshold voltage distribution. A series of tests and experiments indicated that the reason for the higher failure rate was due to the positioning of the test for programming time in the package test flow. This altered the threshold voltage distribution of the flash cells in a way that resulted in higher fails after the test for read. When the added test for programming time was moved to a different location the result was a decrease in failure rate. This study resulted in a fundamental understanding of the ii

4 key issues in NAND flash memory. Even a very slight shift of the flash cell threshold voltage distribution can change the operation of the cell. Thus, failure analysis of NAND flash memory at wafer and package level presents methodologies and corrective actions which curb the occurrence of those kinds of failures for future products. iii

5 DEDICATION I dedicate this thesis to my parents, my husband, sister and brother; this thesis would not have been possible without their support. iv

6 ACKNOWLEDGEMENTS I am indebted to my advisor, Dr. Harrell for all of his assistance and guidance throughout this thesis. Working with him helped me acquire invaluable organizational skills. I am grateful to Dr. Poole for his invaluable contribution towards my education at Clemson. I wish to thank Dr.Bridgwood for being in my thesis committee. Finally, I am thankful to my family, my friends and colleagues at Micron who have been tremendous source of support and encouragement throughout my studies at Clemson University. v

7 TABLE OF CONTENTS TITLE PAGE...i ABSTRACT...ii DEDICATION...iv ACKNOWLEDGMENTS...v LIST OF FIGURES...ix LIST OF TABLES...xiii CHAPTER 1. INTRODUCTION Motivation Thesis Organization THEORETICAL BACKGROUND Overview of Flash memory Flash Cell Structure Memory Array Architecture of NAND Flash Parts Operational Modes of the NAND Flash Memory Chip Program Operation Erase Operation Read Operation NAND Flash Memory Chip Fabrication Process NAND Flash Memory Testing Wafer Probe/Test on NAND Flash Parts Redundancy/Repair strategy in Wafer Probe Overview of Defect Failure Analysis at Wafer Probe Package Test on NAND flash parts Package Tests in Electrical Flash Test Flow Overview of Defect Failure Analysis at Package Test...45 Page vi

8 Table of Contents (Continued) Introduction to the Wafer Map Tool Used for Failure Analysis Summary FAILURE ANALYSIS OF WAFER PROBE AND PACKAGE TEST Analysis at Wafer Probe Procedure for the Extraction of Wafer Probe Repair Data Observation of the Trends/Patterns for Repair Data Explanation for the Cause of the Generated Patterns Analysis at Package Test Procedure for the Extraction of Package Test Failure Data Observation of the Failure Trends/Patterns for Different Package Tests Explanation for the Cause of the Generated Patterns Variation of Trend for the Failure Data of Read1 Test Summary METHODOLOGIES FOR THE DETECTION OF HIGH BLOCK FAILURE RATES AFTER READ1 TEST First Approach -Extraction of History on Parts with High Failure Rate Second Approach - Use of Wafer Map Tool to Determine the Causes for Increase in Block Failure Rates Third Approach Package Tests Performed on the Parts With Higher Failure Rate Summary DETECTION OF HIGHER BLOCK RATE AFTER READ1 PACKAGE TEST Standard Test Flow Employed for NAND Flash Parts Observation of Deviation from Standard Test Flow Procedure Addition of Test for Programming Time on NAND Flash Parts Variation in Threshold Voltage Distribution of NAND Flash Parts Mechanism for the Increase in Block Failure Rate after Read1 Test Summary...99 Page vii

9 Table of Contents (Continued) 6. THEORETICAL CALCULATIONS FOR PROGRAMMING AND ERASING A NAND FLASH CELL Calculation of charge stored on the Floating Gate of a NAND Flash Cell Mechanism of Electron Injection into the Floating Gate of a NAND Flash Cell Calculation of Tunneling Current (I tun ) using Fowler Nordheim Tunneling Mechanism Calculation of Required Energy to Erase a NAND Flash Cell SUMMARY AND CONCLUSIONS APPENDICES A: Block Failure Data after Read1 Test B: Block Failure Data after Read1 Test with Programming Time Test moved in Standard Test Flow C: NAND Flash Memory Data Sheet LIST OF REFERENCES Page viii

10 LIST OF FIGURES Figure Page 2.1 Applications of NAND Flash Memory Physical Layout of Single Flash Cell Circuit Symbol of Single Flash Cell Energy Band Diagram of a Floating Gate Memory during Programming by FN Tunneling Energy Band Diagram of a Floating Gate Memory during Erasing by FN Tunneling NAND Array Architecture Array Architecture of NAND Flash Memory Chip Array Organization of NAND Flash Memory Chip Programming of a NAND Cell Programming 0 for a Single Flash Cell Programming 1 for a Single Flash Cell Threshold Voltage Distribution after Program Operation (A) Erasing of a NAND Flash Array...19 (B) Schematic of Selected NAND Cell for Erase Threshold Voltage Distribution after Erase Operation Reading of a NAND Flash Array Schematic of Selected NAND Cell for Read...23 ix

11 List of Figures (Continued) Figure Page 2.17 (A) Reading 0 Programmed Cell...23 (B) Reading 1 Erased Cell Epitaxy Photolithography (A) Etch...26 (B) Strip Diffusion and Implantation Deposition of Oxide Layer NAND Flash Memory Cell Chip Manufacturing Process NAND Flash Memory Testing Wafer Probe Set Up Probe Card Fully Automated Wafer Probing System (A) Memory Repair for NAND Flash Memory Devices...36 (B) Increase of Yield with Memory Repair Package Test Set-Up Logical Checkerboard Test Pattern for Speed Timing Write Test Physical Checkerboard Test Pattern for Speed Timing Write Test Checkerboard 0 Test Pattern for Speed Timing Write Test...44 x

12 List of Figures (Continued) Figure Page 2.34 Wafer Maps Plot of Column Repair Data after Wafer Probe for 2Gb NAND Flash Parts Plot of Block Repair Data after Wafer Probe for 2Gb NAND Flash Parts Column Fails due to Process Variations Plot of Block Fails after Speed Timing Write Test (High Corner Vcc) Plot of Block fails after Speed Timing Write Test (Low Corner Vcc) Plot of Block Fails after Speed Timing Read Test Plot of Block Fails after Speed Timing Write Test (with logical 0 checkerboard test pattern) Plot of Block fails after Read1 Test Plot of Expected Trend after Read1 Test Plot of Unexpected Trend after Read1 Test Wafer Map of NAND Flash Parts after Read1 Test Threshold Voltage Distribution after Erase Operation Threshold Voltage Distribution after Programming Time Test Threshold Voltage Distribution after Block Erase Threshold Voltage Distribution after Read1 Test...96 xi

13 List of Figures (Continued) Figure Page 5.5 Plot of Block Fails after Read1 Test with Programming Time moved in Standard Test Flow Schematic Cross Section of Single NAND Flash Cell with Intrinsic Capacitances Number of stored electrons in a NAND Flash cell Equivalent Circuit of a NAND Flash Cell Programming a NAND Flash Cell Erasing a NAND Flash Cell Measured I-V Characteristics of NAND Flash Cell Fowler-Nordheim plot of the FIGURE 6.3 (a) Forward direction (b) Reverse direction Energy Band Diagram of a Floating Gate Memory during Erasing by FN Tunneling xii

14 LIST OF TABLES Table Page 3.1 Column Repair Data at Wafer Probe for 2Gb NAND Flash Parts Block Repair Data after Wafer Probe for 2Gb NAND Flash Parts Comparison of 2Gb NAND Flash Cell Parameters from Micron and Research Paper xiii

15 CHAPTER 1 INTRODUCTION 1.1 Motivation NAND Flash memory has become a promising source for the growing memory storage requirements, and now a days is an ideal choice for applications requiring a large amount of data storage, such as digital cameras and camcorders, PDA s, MP3 players, digital consumer equipment including cell phones, and removable storage media such as USB disks and Flash Cards. Extensive research efforts are being carried out by the semiconductor companies to provide quality control of the NAND Flash memory produced to ensure that good parts are being shipped to the customers. It is profitable and efficient to detect and eliminate the defective chips at an early stage of production. Hence, failure analysis forms an integral part of any company s growth. In this thesis, we studied and characterized high failure rate observed in a sample of NAND flash chips. There was an observed increase in the failure rate occurred when the failure data was extracted for at Package Test 2Gb NAND flash at Micron Technology, Inc. The investigation into the possible causes for these failures will help to eliminate the defects in the future, enhance the production cycle, and improve the overall quality and yield of product. 1

16 1.2 Thesis Organization This thesis is divided into seven chapters. We present in Chapter 2 a theoretical background on NAND flash memory and provide insight into the NAND cell structure, its memory array architecture, and the operational modes. This is followed by a discussion of the NAND flash chip fabrication process and flash memory testing at the wafer level and after packaging. An overview of the failure analysis is then presented. Towards the end of this chapter, we introduce a wafer map software tool that is used for failure analysis. Chapters 3 begins with details on the extraction of large volumes of failure data before and after the die are packaged. The procedure followed for the extraction of failure data at wafer level and package level are illustrated in this chapter. Then the failure data was plotted to look for parts with higher failures. We discuss towards the end of chapter about the observation of increase in failure rate at package test. We present in Chapter 4 three different methodologies employed for the determination of reasons for the higher failure rate in a sample of NAND flash parts after Read1 Test. We present that the first two methods were not conclusive and the third method was speculated as the possible reason for higher failure rates. In this chapter, we also illustrate the need to study the threshold voltage distribution of NAND flash parts before and after the tests conducted at package level to investigate the reason for increase in failure rates. 2

17 We analyze the failure data at package test in Chapter 5 and discuss in detail about the variation in the threshold voltage distribution of NAND flash parts for the tests performed in package test flow. We present towards the end of chapter the mechanism for the increase in failure rates at Package Test and the corrective actions employed for decreasing the failure rates. In Chapter 6, details of programming and erasing a NAND flash cell using Fowler Nordheim (FN) mechanism are illustrated. Tunneling current and minimum number of electrons injected into the floating gate of a NAND flash cell are calculated from FN tunneling equation. Also, the minimum energy required to erase a flash cell is computed in this chapter from minimum count of electrons injected into the floating gate. Chapter 7 summarizes the results and draws conclusions to this thesis work which shall be useful for similar kind of failures and yield improvement in the future. 3

18 CHAPTER 2 THEORETICAL BACKGROUND 2.1 Overview of Flash Memory Electronic memory comes in a variety of forms to serve a variety of purposes. The strong consolidated know-how, the flexibility, and the cost make the Flash memory a largely utilized, well-consolidated, and mature technology for most of the nonvolatile memory applications [1]. Flash memory is non-volatile, and thus will retain stored data even when the system is powered off [2-4]. Flash memory also offers fast write, erase, and read access times. Even though the volatile memories like SRAM and DRAM are faster than flash in reading and writing, their contents are lost when power is switched off [1]. These characteristics explain the popularity of flash memory for applications such as storage in battery-powered devices and mass-storage devices such as PC cards and various memory cards. Low power consumption, small size, and relatively low cost make flash memory an ideal option for many applications. Flash memory is widely used for easy and fast information storage in consumer devices such as Notebook computers, Digital Cameras, Cell phones, Personal Digital Assistants (PDA s), Solid-state music players such as MP3 players, Pagers, Personal computers, and Global Positioning Systems (GPS) as shown in FIGURE 2.1. Flash memory also finds use in many industrial applications where reliability and data retention in power-off situations are key requirements. Typical industrial applications include Military and Security systems, Embedded computers,

19 Solid-state disk drives, Wireless communication devices, Networking and Communication products, Medical products such as handheld scanners, and retail management products. Thus, NAND flash memory is used extensively for applications requiring large amount of data storage memory. FIGURE 2.1 Applications of NAND Flash Memory Source: Flash memory was invented by Dr. Fujio Masuoka while working for Toshiba in According to Toshiba, the name 'Flash' was suggested by Dr. Masuoka's colleague, Mr. Shoji Ariizumi, because the erasure process of the memory contents reminded him of a flash of a camera. Dr. Masuoka presented the invention at the IEEE 1984 International Electron Devices Meeting held in San Jose, California. NAND flash memory from Samsung and Toshiba followed in 1989 [15]. 5

20 2.1.1 Flash Cell Structure Flash memory stores information in an array of floating gate transistors, called "cells", each of which stores one bit of information. Newer flash memory devices, referred to as multi-level cell devices, can store more than 1 bit per cell, by varying the number of electrons placed on the floating gate of a cell [7]. A single NAND flash cell is basically a floating-gate MOS transistor which stores 1 bit of information. The physical layout of single NAND flash cell is illustrated in FIGURE 2.2, and describes it as an n- channel transistor with a gate completely surrounded by dielectrics, referred to the floating gate (FG), and is electrically controlled by a capacitively coupled control gate (CG) [1]. The circuit symbol of a single NAND flash cell with control gate, floating gate, and source and drain contacts is as shown in FIGURE 2.3. The floating gate and the control gate of a NAND flash cell are made of polysilicon. Polysilicon is the traditional material to use for transistor gates since the material is stable enough to withstand high temperature process. Using polysilicon for both the floating gate and control gate simplifies the process, and also stores the charge quite well. The FG is essentially located between the CG and the substrate, as seen in FIGURE 2.2, but the FG is isolated by an insulating oxide layer. Any electrons placed on the FG are trapped there, and thus the storage of the information is achieved. The interpoly dielectric (IPD) that separates the FG from the CG in FIGURE 2.2 is formed by a triple layer of oxide nitride oxide (ONO). The ONO films form a triple layered capacitor structure, which features the high dielectric constant of silicon nitride (Si 3 N 4 ) deposed between two silicon dioxide (SiO2) films. The structure thus can provide 6

21 higher program/ erase speeds and better data retention characteristic. The ONO thickness is normally in the range of nm. The gate dielectric, i.e., the one between the transistor channel and the FG in FIGURE 2.2, is an oxide in the range of 9 10 nm. SiO 2 is the industry standard material used for the tunnel oxide. The dielectric constant as well as the work function of silicon dioxide is best suited for the NAND cell transistor. SiO 2 is called a tunnel oxide because electrons flow through it via the Fowler Nordheim (FN) tunneling mechanism [25]. FIGURE 2.2 Physical Layout of Single Flash Cell FIGURE 2.3 Circuit Symbol of Single Flash Cell 7

22 Fowler-Nordheim tunneling, also called field emission, is the process by which electrons tunnel through a barrier of reduced width in the presence of a high electric field. The charge needed to program the device has to be injected into the floating gate. The FN tunneling mechanism is used in order to change the charge or the data content of the cell [5]. Programming and erasing of a flash cell is done by using FN tunneling mechanism which is explained as follows. During programming a flash cell, a relatively large voltage of about 20V is applied at the control gate. The energy band structure will be significantly changed from the equilibrium state influenced. This band structure gives rise to charge storage. FIGURE 2.4 illustrates the energy band diagram of a floating gate memory during programming by FN tunneling. e c and e v are the conduction and valence bands respectively, E g is the energy band gap (1.1 ev for silicon), and Ø b is the Si-SiO 2 energy barrier (Ø b is 3.2 ev for electrons and 4.7 ev for holes). The applied control voltage creates the electric field which changes the potential barrier. The change in barrier reduces the width allowing the electrons in the substrate to tunnel through the thin gate oxide (typically less than 12 nm) and eventually be collected in the n+ poly-si floating gate. The collection of electrons on the floating gate increases the threshold voltage as it requires larger control voltage to turn on the flash cell. The bending of the energy bands of the IPD and the gate oxide are different due to the thickness differences between them. Thus, programming a flash cell by FN tunneling puts the electrons into the floating gate and the cell stores logic 0. 8

23 FIGURE 2.4 Energy Band Diagram of a Floating Gate Memory during Programming by FN Tunneling [24] FN tunneling is also used to erase a flash cell. A large negative voltage is applied to the control gate and the source and drain are left floating. The energy band structure of floating gate memory during erasing by FN tunneling is as shown in FIGURE 2.5. The electric field generated causes the electrons to tunnel away from the floating gate, making it more positive and turning on the transistor. This decreases the threshold voltage of the cell as it requires less gate voltage to be applied to turn on the flash cell. Thus, erasing a flash cell by FN tunneling removes the charge from the floating gate and erased cell stores logic 1. 9

24 FIGURE 2.5 Energy Band Diagram of a Floating Gate Memory during Erasing by FN Tunneling [24] When electrons are on the FG, they modify the electric field coming from the CG, which modifies the threshold voltage (V t ) of the cell. Thus, when the cell is "read" by placing a specific voltage on the CG, electrical current will either flow or not flow, depending on the V t of the cell, which is controlled by the number of electrons on the FG. This presence or absence of current is sensed and translated into 1's and 0's, reproducing the stored data. In flash memory lingo, programming (putting electrons into the floating gate) means writing a 0, erasing (removing the charge from the floating gate) means resetting 10

25 the flash memory contents to 1; or in other words: a programmed cell stores a logic 0, an erased cell stores a logic 1. Thus, programming and erasing of a single NAND flash cell is carried out by using the FN tunneling Memory Array Architecture of NAND Flash Parts The NAND Flash name is related to the way the flash cells are arranged in series in an array. An array is a collection of flash cells arranged in rows and columns which stores the information. NAND flash cells sharing the same control gate (CG) constitute the wordline (WL), while those sharing the same drain electrode constitute the bitline (BL) as shown in FIGURE 2.6. A typical NAND array is formed by 16 or 32 NAND flash cells or transistors connected in series with two select transistors, the ground select transistor (GSL) and the bitline select transistor (SSL), as shown in FIGURE 2.6. CG1 to CG16 in FIGURE 2.6 represent the control gates of the NAND flash cells. Each NAND cell stores one bit of information. The bitline select transistor and the word line ensure the selectivity of a particular NAND flash cell or bit. The ground select transistor prevents the cell current from passing during programming. Based on the voltages applied to the word line and bitline a particular bit can be programmed or erased, thus storing the data in flash cells. 11

26 FIGURE 2.6 NAND Array Architecture [11] The memory array architecture of the 2Gb NAND flash parts used in this thesis work is discussed in this section. A memory array in a chip can be organized as a single piece of memory or can be divided into several sets of memory arrays. It is convenient for the memory chip with a large memory size to be divided into smaller arrays. In a memory chip with a single memory array, if a particular column of an array is damaged then the entire part fails to function. But when the memory is divided into sets of array, the memory chip can be easily repaired. This efficient memory management of an array provides for easy detection and correction of failures. A 2Gb NAND flash memory is divided into 2048 blocks. A single block of a NAND flash chip has 32 word lines/rows and bit lines/columns of flash cells arranged as shown in FIGURE 2.7. Each bitline stores 32 bits of information. The size of a single flash memory block is 32 bits bitlines which is about a 1Mb (Mega bit) 12

27 array size. The total size of the NAND flash memory array shown in FIGURE 2.7 is 1Mb 2048blocks which is about 2Gb (2 Giga bit). FIGURE 2.7 Array Architecture of NAND Flash Memory Chip A NAND flash chip, based on its size; i.e., 2Gb (Giga bit), 4Gb or 8Gb, is divided into various blocks each of 1Mb (Mega bit) array space. Each block is again subdivided into pages. The array organization of the 2Gb NAND flash chips used in this research is as shown in the FIGURE 2.8 and is described as follows: Array Organization Device size: 2Gb: 2,048 blocks; 4Gb: 4,096 blocks; 8Gb: 8,192 blocks Block size: Page size: 64 pages (128K + 4K bytes) 2, bytes 13

28 FIGURE 2.8 Array Organization of NAND Flash Memory Chip [12] A 2Gb NAND flash chip is composed of the blocks. There are 2048 blocks in a 2Gb NAND flash part. One block is composed of 64 pages. The division of the entire flash memory array into blocks and pages enables easy detection of failures and increases the yield Operational Modes of the NAND Flash Memory Chip In section we discussed that a single flash cell can be programmed and erased using FN tunneling. In this section the operational modes of the whole NAND flash memory chip are discussed. The characteristics of the flash memory chips vary based on the voltage applied to the control gates, or word lines (WL) and bit lines (BL). The principles involved in performing the programming, erase, and read operations are similar for all NAND flash components. However, the voltages at which they operate 14

29 differ based on the memory device size. In this thesis, samples of 2Gb NAND flash parts were investigated using failure analysis techniques. The ensuing subsections describe the operations and the voltages associated with each of the operational modes for 2Gb NAND flash parts Program Operation Programming a NAND flash memory consists essentially of moving charges onto the floating gates of the flash cells which are arranged in an array. This changes the threshold voltage of the FG transistor. A Programmed flash cell stores logic 0. In the programming operation as shown in FIGURE 2.9 ( 0 data), the substrate is grounded; 20V is applied to the selected gate word line (GWL), the unselected bit line is at Vcc (Supply Voltage) along with the bitline select transistor (SSL) and 10V applied to all unselected control gates within the string. The selected bit line and ground select transistor (GSL) are then grounded and Vcc is applied to the common source to suppress current flow from the unselected bitline as shown in FIGURE 2.9. Electrons are injected into the floating gate from the inversion channel by Fowler-Nordheim tunneling [4] as shown in FIGURE The threshold voltage of the selected cell goes from negative to positive [9]. In the case of programming 1, the channels of the NAND structured cells are boosted up to 8V as shown in FIGURE 2.11 and the threshold voltage of the unselected cells remains negative. No tunneling occurs in the unselected cells because the voltage difference between the control gate and the source/drain is insufficient to initiate 15

30 tunneling current [17]. Since the memory cells in the NAND string are connected in series, the threshold voltage of each programmed cell must be between the selected control gate voltage and the pass gate voltage in order to read the string. If the threshold voltage of any pass transistor in the string exceeds the pass control gate voltage, the other cells in the string cannot be read. FIGURE 2.9 Programming of a NAND Cell [9] FIGURE 2.10 Programming 0 for a Single Flash Cell [1] 16

31 FIGURE 2.11 Programming 1 for a Single Flash Cell [1] The cells are checked whether they are programmed correctly by performing read operation on flash cells. The NAND cells have a threshold voltage higher than 0V if they are programmed. The threshold voltage distribution of the flash cells after program operation is illustrated in FIGURE Here, the X-axis represents the threshold voltage of the flash cells and y-axis represents the flash cells in blocks of NAND flash array. A program verify level, is the voltage level applied to the flash cells to obtain required threshold voltage for programming. Typically its value ranges from 1-1.5V. In FIGURE 2.12, the NAND flash cells above the program verify level are programmed correctly, as they have a threshold voltage higher than program verify level. Hence, the programmed flash cells above the program verify level pass when a read operation is performed on the cells. Distribution of programmed 0 flash cells is above the program verify level as illustrated in FIGURE 2.12 so that all the flash cells are programmed. The voltage 17

32 applied to the gate should change the threshold voltage of the flash cells to a verify level which exceeds the read level to ensure that all of the cells will be able to be properly read. The read level is a voltage level applied to the flash cells to properly read them. The read voltage level varies from 0 0.5V as shown in FIGURE The read level is set up such that it is able to read the programmed and erased cell. Thus, NAND flash cells which have a threshold voltage above the program verify level are programmed properly. FIGURE 2.12 Threshold Voltage Distribution after Program Operation Erase Operation Erasing a NAND flash memory is basically removing the charges from the floating gates of the flash cells arranged in an array. This decreases the threshold voltage of the FG transistor. An erased flash cell stores logic 1. Erase can be performed on the whole chip or on a selected block. In a block erase operation (resulting in 1 ) of a 18

33 NAND flash array as shown in FIGURE 2.13 (A), the control gates are grounded, SSL and GSL are floating and the bitline is left floating. Here, floating refers to the same state as it was when applied last time. A schematic of a single NAND flash cell selected for erase operation is shown in FIGURE 2.13 (B), where the control gate is grounded, 20V applied to the substrate, and the source and drain are floating. Electrons are removed from the floating gate to the p- substrate by Fowler-Nordheim tunneling [1, 9], and the threshold voltage of the erased cells shifts from positive to negative. All cells in the block are erased with a threshold voltage of 1V. To inhibit erase on unselected blocks, the control gates are biased to approximately 20V in order to prevent F-N tunneling from occurring. (A) (B) FIGURE 2.13 (A) Erasing of a NAND Flash Array (B) Schematic of Selected NAND Cell for Erase [9] 19

34 The NAND flash cells have a negative threshold voltage in the erased state and hence it is conductive. Threshold voltage distribution of the flash cells after erase operation is as shown in FIGURE Here, the threshold voltage distribution of programmed 1 values i.e. erased cells is shifted to the negative values. X-axis represents the threshold voltage values of the flash cells and the y-axis represents the flash cells in blocks of NAND flash array. Erase verify level is the threshold voltage required by the flash cells to be erased. Typically, erase verify level ranges from -0.2V to -0.8V. In FIGURE 2.14, the NAND flash cells below the erase verify level are erased correctly, as they have a threshold voltage lower than erase verify level. The NAND flash cells which have the threshold voltage below the erase verify level are erased properly and pass when a read operation is performed on the cells. Read level is the voltage level applied to the flash cells to properly read the cells. Read level is same for program operation and erase operation. The erase process is similar to that of programming in that the V T that is on the cell is marginally below that required to read a 1 from the cell [11]. Thus, NAND flash cells which have the threshold voltage below the erase verify level are erased properly and read logic 1. 20

35 FIGURE 2.14 Threshold Voltage Distribution after Erase Operation Read Operation A read operation is performed on the NAND flash cells to check if a particular cell is a programmed cell or an erased cell. The read operation is performed by applying a gate voltage to the cell that is between the values of the threshold voltages of the erased and programmed cells and then sensing the channel current flowing through the device [4]. Figure 2.15 illustrates the voltages applied to the flash cells of selected bitline while performing a read operation on a NAND flash array. 1.2V is applied to the selected bitline, 0V is applied to the selected WL and 4.5V is applied to the control gates of the unselected cells. The unselected bitlines of the array are grounded. The schematic of the selected NAND cell for read operation is as shown in FIGURE Here the control gate and source are grounded, 4.5V is applied to the drain and the substrate is grounded. A programmed cell ( 0 ) has a positive threshold voltage and an erased cell ( 1 ) has a 21

36 negative threshold voltage. Therefore, if the selected cell is a 1 (erased cell), the memory cell transistor is in depletion mode and current flows as shown in FIGURE 2.17 (B). On the other hand, if the selected cell is a 0 (programmed cell) no current flows because the memory cell is in the enhancement mode as shown in FIGURE 2.17 (A). Due to large arrays of flash cells, the resulting signal, for the read operation, has a much lower voltage swing. To compensate the swing, sense amplifier will amplify a signal coming off the bit lines during read sequence. A sense amplifier that is connected to the bit line detects the state of the cell. Thus, a read operation is performed on the NAND flash array to read the state of cell i.e. whether it is erased or programmed. FIGURE 2.15 FIGURE 2.16 Reading of a NAND Flash Array [9] Schematic of Selected NAND Cell for Read [9] 22

37 (A) (B) FIGURE 2.17 (A) Reading 0 Programmed Cell (B) Reading 1 Erased Cell 2.2 NAND Flash Memory Chip Fabrication Process Device fabrication processes are used to create chips, the integrated circuits that are present in everyday electrical and electronic systems. It is a multiple-step sequence of photographic and chemical processing during which electronic circuits are gradually created on a wafer made of its doped silicon. The wafer is made out of extremely pure silicon grown into mono-crystalline cylindrical ingots up to 12" (300 mm) in diameter using the Czochralski process [23]. These ingots are then sliced into wafers about 0.75mm thick and polished to obtain a very regular and flat surface. Once the wafers are prepared, they undergo a series of process steps to produce the desired semiconductor integrated circuit; i.e., NAND flash memory. The NAND flash memory fabrication process is grouped into four areas. 23

38 Wafer Fabrication o Front end processing o Back end processing Wafer Probe or Test Assembly Cycle Package Test In this section, the fabrication process (which is compromised of both front end and backend processing) of NAND flash memories is explained in detail. Flash memory testing is discussed in the next section. "Front End Processing" refers to the formation of the transistors directly on the silicon. "Back End Processing" creates metal interconnecting wires, isolated by insulating dielectrics. First, the front end processing of NAND flash memory chip is discussed in this section. Crystalline or contaminate defects kill the operation of an IC, so it is desirable that the silicon be ultra-pure. The best possible quality of silicon is created by growing a pure layer of silicon on the raw wafer via an epitaxial growth process. FIGURE 2.18 illustrates the epi-layer formed. This layer is very thin approximately 3 percent or less of the wafer thickness. The active circuits are thus fabricated in this epilayer. 24

39 FIGURE 2.18 Epitaxy Source: The construction of NAND flash cells on wafers involves several steps. The first step involves heating of the epi-wafer to grow an oxide layer, specifically silicon dioxide. The lithography process is then used to transfer a pattern from a photomask (reticle) to the surface of a substrate as illustrated in FIGURE The photoresist is spun and baked to make it harder. The reticle is exposed step-by step over the wafer and the resist is developed to create the pattern on the wafer. FIGURE 2.19 Photolithography Source: 25

40 The wafer with patterned photoresist is then put into an oxide etch process to remove the oxide where there is no pattern as illustrated in FIGURE Either a wet etch or a "dry" etch is used for this purpose. The photoresist is then removed or stripped. The stripping of photoresist must be entirely complete as in FIGURE 2.20 (B), otherwise it would cause surface contamination. (A) (B) FIGURE 2.20 (A) Etch (B) Strip Source: The next step in the fabrication of NAND flash memory is ion implantation. During implantation, the dopant molecules are implanted vertically into the surface of the silicon by a high-energy ion beam as illustrated in FIGURE These regions are now doped with negative ions, creating n-type source and drain regions of the transistor in a p- type silicon base. A layer of oxide is then deposited and an opening is made in the oxide to build the gate region using the oxidation and photolithography process as shown in FIGURE A thin layer of tunnel oxide is then deposited on the surface of wafer 26

41 using chemical vapor deposition. Then a floating gate made of polysilicon is deposited by a Physical Vapor Deposition (PVD) process as shown in FIGURE FIGURE 2.21 FIGURE 2.22 Diffusion & Implantation Deposition of Oxide Layer Source: Another layer of oxide is deposited on top of the floating gate. The polyisilicon, used as the floating gate is deposited on top for gate voltage control. FIGURE 2.23 shows the schematic cross section of single NAND flash memory cell with source, drain and gate contacts respectively. FIGURE 2.23 NAND Flash Memory Cell Source: 27

42 After the NAND flash cells are created, they must be interconnected to form the desired electrical circuit. This "Back End Processing" involves creation of metal interconnecting wires, isolated by insulating dielectrics. Reticles and photolithography are used in back end processing for formation of contact areas. The contact areas in the silicon dioxide are unmasked to etch all the way down to silicon and polysilicon areas of the transistor's source, drain and gate regions. These holes, called "vias", are essentially chemically "drilled" holes which expose the contacts to the three-terminals of the transistor. A layer of aluminum is deposited on the surface and down into the via holes. Excess aluminum is etched away during another photolithography process, leaving the desired interconnect pattern. Another layer of dielectric isolation oxide is deposited to insulate the first layer of aluminum from the next layer of another NAND flash cell. CMP (Chemical Mechanical Planarization), an abrasive process, is used for polishing the surface of the wafer flat. Chemical slurries and a circular (sanding) action are used to polish and smooth the surface of the wafer. The smoothed surfaces are then ready for additional process steps and additional layers. Another set of via holes are etched in the dielectric isolation oxide to enable access down to the layer below. Contact plugs of tungsten are deposited into the vias to reach down and make contact to lower layers. The layers establish the interconnection between various NAND flash cells to form a NAND flash memory. The next layer of aluminum is deposited, patterned and etched. Typically there are about 2-3 layers of metal. This process is repeated for as many interconnect layers as are required for the NAND flash memory chip design. 28

43 After fabricating the NAND flash cells; i.e., NMOS transistors with floating gates, they are interconnected as per the NAND flash memory structure to form a NAND flash memory chip. The fabrication process is then followed by a wafer testing process discussed in the next section. When the finished wafer comes out of the fabrication process, it is ready for the wafer test, assembly and packaging processes to finally produce a set of good, usable integrated circuits. The flow chart in FIGURE 2.24 outlines the salient steps involved in the memory chip manufacturing process. FIGURE 2.24 Chip Manufacturing Process Source: 29

44 2.3 NAND Flash Memory Testing NAND flash memory is tested at the fabrication phase before the wafer is sent to die packaging and this is defined as wafer probe or test. After packaging the die is tested, defined as package test. Wafer probe is performed after wafer fabrication during which the electrical parameters of the integrated circuits are extracted, and the circuits are tested for functionality. The wafer probe is performed after the fabrication so that yield data can be assessed quickly and fed back to the fabrication group, in order to correct and optimize the fabrication processes. After IC packaging, a packaged chip will be tested again with the process similar to that of wafer probe. Removal of defective die at wafer probe saves the cost of packaging faulty devices. Therefore, wafer probing is performed after fabrication of the finished wafer and before package test as shown in FIGURE The packaged die is tested again under stressed conditions after package burn-in. A detailed discussion of the package tests on the NAND flash parts is presented in Section Then the packaged die is finally checked for its functionality at final test as shown in FIGURE The good products are then shipped to the customers. FIGURE 2.25 NAND Flash Memory Testing Source: 30

45 Thus, wafer probing after fabrication accelerates the detection of any defects from fabrication and provides a faster feedback to the fabrication engineers. The tests done after the chip is packaged ensure that the parts are good before they are shipped to the customers. Wafer probe and package tests result in the elimination of the defects thus improving the yield of the die Wafer Probe/Test on NAND Flash Parts The NAND flash fabrication process consists of many complicated steps that form functional die on the wafer. Unexpected variations at any of these steps can affect the electrical characteristics of the memory cells. Therefore, the wafer probing step is performed after the fabrication process to determine the failures. Wafer probing is a complex procedure. Wafer probe employs the use of a probe station combined with complicated electrical test equipment along with software tools to store information about the parts tested. At wafer probe, a large volume of parts are initially tested for basic operations and functionality. The memory chips that fail at wafer probe are not packaged. Wafer probing is performed before a wafer is sent to die packaging. All individual integrated circuits that are present on the wafer are tested for functional defects by applying special test patterns to them. A test pattern is a sequence of bits ( 0 or 1 ) provided as input to the circuit to check its functionality. The wafer testing is performed with a piece of test equipment called a prober, and the process in general is referred to as a wafer probe or test. 31

46 The three basic tools used to perform wafer probe are illustrated in FIGURE 2.26, and are called wafer prober, test head and test mainframe. First, the wafer prober takes wafers from their carriers, loads them onto a flat chuck, and then aligns and positions them precisely under a set of fine contacts on a probe card. Secondly, in test head set-up, each input-output or power pad on the die is contacted by a fine electrical probe. This is done by a probe card, which translates the small individual die pad features into connections to the tester. A probe card, shown in FIGURE 2.27 holds a number of tiny needles with specific spacings designed to make contact with bond pads so that the die can be tested while still in wafer form. Thirdly, the functional tester or automatic test equipment (ATE) as shown in FIGURE 2.28 is connected to the probe system using special interfacing hardware. ATE is a test mainframe, which is capable of exercising the die on the wafer under software control. It also provides inputs for testing the functionality of die and identifies the failed die on wafer. In this thesis, the failure data for samples of 2Gb NAND flash die was collected from agilent ATE. Agilent testers are effectively used in the semiconductor industry for wafer testing and offer lower test cost per bit when compared to other testers in the market. Thus, the information from ATE in wafer probe is normally used for the failure analysis. 32

47 FIGURE 2.26 Wafer Probe Set-Up Source: FIGURE 2.27 Probe Card FIGURE 2.28 Fully Automated Wafer Probing System Source: The wafer electrical tests are not as extensive as that of the packaged parts. However, the wafer probing checks for the functional and critical electrical parameters. If a device does not meet the data sheet specifications, it is identified by the tester and the device is rejected. The tester/probe card combination may be able to contact and test 33

48 more than one die at a time on the wafer. This parallel test capability enhances the productivity of wafer testing. The main objective of wafer probe is to look for the defects that occurred during manufacturing. The tests performed on NAND flash parts at wafer probe are as listed below: Functional testing determines whether the device is able to perform its basic operations. Parametric testing usually consists of applying a constant voltage at a node and measuring the current response (force-voltage-measure-current) at that node, or applying a constant current at a node and measuring the voltage response (forcecurrent-measure-voltage). Parametric testing, thus checks if the device exhibits the correct voltage, current, or power characteristics, regardless of whether the unit is functional or not. When a die passes all the tests at wafer probe, its position on the wafer is stored in database for use during IC packaging. If a particular NAND flash memory part fails one of the tests, wafer probe categorizes it as a specific failure. For example, the parts are tested for column shorts at wafer probe. When any two columns in a NAND array are shorted, it is defined as a column short. Yield enhancement engineers group or categorize all the parts which fail to this test. Wafer probe provides large amounts of defect information and process related issues to fabrication engineers, product engineers, and design engineers. This assists in process and design improvement. A die that passes some 34

49 but not all test patterns can still be used as a product with limited functionality and can be shipped to the required customers. All good die, those that pass the functional and parametric tests at wafer probe, are then sent to assembly for packaging Redundancy/Repair Strategy in Wafer Probe Redundancy/Repair has been widely used for enhancing the yield and reliability of memory chips [18]. Redundancy is the duplication of elements to provide an alternative incase of failures. Memory Repair is performed after the wafers are tested at wafer probe. Redundant memory is the extra or spare memory built in the chip which can be used incase of failures. If a fault occurs in the main memory, it is switched to the redundant memory [21]. The blocks or columns of a memory array that fail certain tests at probe can thus be replaced with the redundant blocks/columns built into the chip. This improves the yield of the die. The redundancy/repair strategy used in this thesis work for 2Gb NAND flash parts is discussed in this section. A NAND flash memory is designed with redundant rows and columns (spares) which can logically replace rows or columns which may contain defective memory cells, as illustrated in FIGURE If a particular bit fails, the entire row or column containing that cell is to be replaced. If a NAND flash chip does not pass some test patterns at probe, it is repaired with the available internal spare resources. The redundant solution provides the information about the redundant column used for repair and the column to be replaced. Repair is done merely by programming in the redundant solution. 35

50 The probe engineers at wafer probe repair as many die as possible by analyzing all failures and replacing failing elements with redundant elements. The yield of die increases with memory repair than without repair as the failure rate is decreased. This is illustrated in FIGURE 2.29 (B) where percentage of yield of die increases with repair. Design engineers make sure that there are not many redundant columns in a die, as it will increase the die size which shall have an impact on yield. Probe tests and redundancy repairs are performed at the wafer level in order to fail nonfunctioning die before they are sent to assembly, thereby reducing packaging and final test costs. (A) (B) FIGURE 2.29 (A) Memory Repair for NAND Flash Memory Devices (B) Increase of Yield with Memory Repair Source: Overview of Defect Failure Analysis at Wafer Probe Failure analysis (FA) plays a vital role in the development and manufacture of integrated circuits (ICs) [19]. Failure analysis at probe is useful for determining the 36

51 causes for the failure of a semiconductor device and enables corrective and preventive measures in the future. The steps followed for failure analysis are unique. Analysis proceeds with each subsequent step depending on the outcome of the previous step. The analysis is completed once enough information is obtained to draw a conclusion about the cause of the failure. Wafer probe is a test procedure where various tests are conducted on NAND flash parts. The failures are analyzed after the wafers are tested. Then, the information about the block/column repaired and redundant block/column used for the repair are provided. As part of this thesis work, repair data for different tests at wafer probe were collected in order to observe and analyze any abnormalities from the expected trend/pattern. A pattern or a trend is a graphical representation of the sample repair or failure data. Various trends can be represented from the repair data. For example, from the repair data we can plot a trend of each of the columns or blocks in a sample of NAND flash parts determine the count of fails. Suppose the trend shows a particular column/block to fail a larger number of times as compared to the other columns/blocks. This would constitute an abnormal trend. Another abnormal trend could be a set of columns in the middle of a NAND flash array that failed more than other columns. It is necessary to find out the cause for such abnormal trends in order to eliminate such fails in future production. The analysis of the repair data is thus provided to the fabrication department, product engineering, and design department for assistance in process and design improvements, which will improve the yield. 37

52 2.3.2 Package Test on NAND Flash Parts Package test checks the chips for functionality just before leaving the factory. Package test is performed after the die is packaged. The information generated at package test is used to monitor yields and performance of a product. In the assembly process, individual die are separated from the wafer and packaged. The die is then passed through the package test to screen out infant mortalities and perform functional pattern tests at ambient, cold, and hot temperatures. The chips are tested to ensure that they were not damaged during packaging and that the die-to-pin interconnect operation was performed correctly. At package test more extensive tests are performed than at wafer probe. At wafer probe, only the critical electrical parameters and basic operations are tested. In package testing, the devices are tested for data sheet specifications and electrical parameters under stressed conditions at different temperatures. This is done to improve the quality of die. The tools employed for packaged test are discussed in this section. The three tools used to perform the package test operation are illustrated in FIGURE 2.30, and are called package handler, test head and test mainframe. First, the package handler takes packaged die from their carriers and sets the environmental temperature as specified. Secondly, each pin on the chip's package must be contacted by inserting it into a socket on a custom designed PC board known as Design Under Test (DUT). This DUT is the test head set up as illustrated in FIGURE Thirdly, the functional tester, or automatic test equipment (ATE), is used as a Test Main Frame which is capable of functionally exercising all of the chip's designed features under software control as illustrated in FIGURE Any failure to meet the published specification is 38

53 identified by the tester and the device is marked as a reject. The tester/handler combination is able to contact and test more than one part at a time in parallel for increased productivity. FIGURE 2.30 Package Test Set-Up Source: Chips are tested at more than one temperature before being shipped, to make sure it functions properly. Thus, testing helps insure the quality, performance, and integrity of parts so that the customers receive a product that meets published device specifications Package Tests in Electrical Flash Test Flow Package tests ensure that the customer s requirements are met and the die performs as per the data sheet specifications. The packaged die are tested in two environmental conditions, i.e.; hot sort and cold final. 39

54 Hot Sort Testing In hot sort testing, parametric and functional tests are conducted at high temperatures ranging from 70 o C to 90 o C on production testers. This is done to verify if the parts function over a range of temperatures as specified in the datasheet. Parametric tests are performed to detect opens, shorts, input / output leakage and to determine whether input / output high and low levels and standby / operating currents are within specified limits. Functional tests check for noise margin, programming and erase times, and verification of AC parameters. Some of the AC parameters, for which the parts are verified are rise time/ fall time, setup time, hold time, and write cycle timings. At hot sort, the packaged die are tested at extended temperatures. This makes hot sort testing one of the most important tests at package. Some of the functional tests that are performed on packaged NAND flash parts in hot sort conditions were focused on for the project. More parts fail for certain functional tests. Typically the operating power supply of a NAND flash chip is 3.3V. Vcc is the power supplied to the whole part externally, not for any specific cell. The data sheet specifies a Vcc range to the customers, across which the part is good. So, the part is tested at Vcc range corners i.e. low Vcc and high Vcc to catch the worst case problems. High corner Vcc applied to the NAND parts is normally about 3.7V and low corner Vcc is about 2.6V. Five functional tests at hot sort were chosen for this thesis in order to have enough failure data for analysis. They are as discussed below: 40

55 Test I: Speed Timing Write Test (High corner Vcc) This test checks whether a test pattern is written into an array of flash memory with high corner Vcc applied to the NAND flash parts within data sheet timings. In the data sheet specific program time is specified, within which the memory array has to be programmed. The test pattern that checks for the flash write operation has an alternating pattern of 1 s and 0 s. The data in the first logical address location has 1 s and the next logical address location has 0's. This is called a logical checker board test pattern. For example, if each logical address stores 4 bits of information then the logical checkerboard test pattern would be as shown in FIGURE FIGURE 2.31 Logical Checkerboard Test Pattern for Speed Timing Write Test This test is used to check whether a particular test pattern is written into the cells of a NAND flash array after it is programmed. This is done by reading back the data and comparing it with the input values. The chip which takes lesser time to program the flash array with a particular test pattern has greater performance. The test pattern must be written onto the flash array of NAND flash part in typically about us as mentioned in the data sheet. This is called as datasheet programming time. Speed Timing write Test also checks whether the flash cells are programmed within the timings 41

56 specified in the data sheet. Thus, it is important to check whether the flash array is programmed with a pattern similar to that of input test pattern and within the time specified to improve the performance and yield of the NAND flash part. Test II: Speed Timing Write Test (Low Corner Vcc ) This test checks if a flash memory array is programmed with a different test pattern i.e. physical checkerboard test pattern when compared to logical checkerboard pattern, as illustrated in FIGURE 2.32 with low corner Vcc applied to the NAND flash parts. The test pattern has alternating 1 s and 0 s stored in flash cells. This is called as physical checkerboard test pattern. The blocks of flash memory array are programmed with a different test pattern as compared to the test pattern used for Speed Timing Write Test (High corner Vcc) to ensure that it can be programmed to various test patterns within the timings specified in the data sheet. FIGURE 2.32 Physical Checkerboard Test Pattern for Speed Timing Write Test When the bits are read back, each bit in the array should be in the state opposite to that of all adjacent bits (both horizontally and vertically); i.e., the first physical bit line in an array is a 1 and the adjacent bit line is a 0 and so forth. Thus, the reason for the 42

57 Speed Timing Write Test is to check whether the flash cells are programmed correctly within the timings for the NAND flash parts at low corner Vcc. Test III: Speed Timing Read Test The Speed Timing Read Test programs the flash memory array with a logical checkerboard test pattern with low corner Vcc applied to the NAND flash parts. The blocks of the flash memory array are programmed with a test pattern and read by applying the necessary voltage combination to the flash cells. The tests checks if the blocks of flash memory array are read correctly within the specified datasheet timings which is typically about 20-25us. Here the time taken for reading the blocks of array is checked whereas in Test I and Test II, time taken to program the flash cells is tested. Test IV: Speed Timing Write Test (with different logical checkerboard test pattern) The blocks of the flash memory array is programmed to a different logical checkerboard pattern when compared to the pattern used for Test I, with high corner Vcc applied to the NAND flash parts. The test pattern used has the data in the first logical address has 0 s and the next logical address location has 1's as shown in FIGURE This pattern is called logical checkerboard 0 test pattern as the first logical address location starts with 0. The test checks for the logical checkerboard 0 test pattern to be written into an array within the data sheet specifications. 43

58 FIGURE 2.33 Logical Checkerboard 0 Test Pattern for Speed Timing Write Test Test V: Read1 Test This package test runs checks to read the blocks of flash memory array after an erase operation to verify that the flash cells are in an erased state with low corner Vcc applied to the NAND flash parts. When the cells are in an erased state they should read 1. Hence, if the data stored in the flash cells is 1, the NAND flash part passes the Read1 Test. The failure data was extracted for these five tests for analysis in the thesis. The sample size of the flash parts that fail to these five tests ranges from 10,000 20,000 individual die. If there are more number of parts with fails then it is meaningful to extract the data related to them and determine the reason for their failure. The five tests mentioned thus, provided sufficient data for failure analysis. This was the criterion for choosing these five tests. There are many more tests conducted on NAND flash memory in the package test phase, but we focused on these five tests and a few test patterns for failure analysis. 44

59 Cold Final Testing In cold final testing parametric and functional tests are also conducted similar to hot sort testing. However, the tests are run under different temperature conditions, ranging from 0 to -40 o C on production testers. This is done to verify if the parts function over a range of temperatures as specified in the datasheet. The failure information about the parts that failed under cold conditions is feedback to the fabrication group and design engineers for decreasing the fail Overview of Defect Failure Analysis at Package Test Failure analysis is used to provide specialized information that contributes towards the determination of the failure mechanisms operating in a sample. Application of failure analysis ensures improved designs, results in higher yields, and shortens the development cycle since the sources of failure that necessitate redesign and manufacturing changes are identified early [20]. Individual analytical tests are performed to complete the failure analysis process. In this process, non-destructive analysis must be conducted first, prior to any destructive ones. Non-destructive failure analysis at package test involves the extraction of whole block failure data of NAND flash parts. Packaged die from assembly are tested for their functionality at cold and hot temperatures. As discussed previously, the NAND flash memory array is divided into blocks where each block is 1Mb of array space. Failed blocks are blocks those contain one or more invalid bits. When the die fails to function properly, block information on the die is extracted for easy analysis. This information 45

60 helps to focus only on a particular block of the die responsible for the failure, instead of all the blocks in the die. From the failure information obtained, the reasons for the failure can be normally determined. Possible reasons for failure may be due to die scratches, die cracking, wire to wire shorting, wire to die shorting, or wire breaking. In this project, failure analysis of the block data for each NAND flash part at package test was studied. Samples of failed block data for different tests at package test were collected to investigate any abnormal trends. In the trends, if higher failure rate of the parts is observed, the cause for it has to be determined than the parts with lower failure rate as it shall effect the yield Introduction to the Wafer Map Tool Used for Failure Analysis Wafer Map Tool is a standard software tool used for failure analysis in the semiconductor industry. Wafer maps are widely used by the semiconductor industry for process monitoring and yield enhancement [22]. A wafer map is a report generated by the wafer map software tool that shows each individual unit, or die, on the surface of a silicon wafer, as illustrated in FIGURE Various tests are performed on the wafers at wafer probe. Wafer Map Tool displays the wafer map using color-coded die to indicate the test results. This helps the test engineers to visually identify the faults and locate the failed die on the wafer. The location of the die on the wafer is displayed using X/Y coordinates relative to a reference die. The reference die is selected anywhere on the wafer. It is also possible to zoom in and out on the wafer map to view more information about a particular die. Wafer Maps helps to look at individual wafers for specific failures 46

61 and can significantly improve the operational efficiencies of the wafer manufacturing process. They provide fast feedback to the fabrication process engineers to make adjustments to the process to improve overall yield. FIGURE 2.34 Wafer Maps Source: Summary In this chapter, we presented the theoretical background, concepts, and applications of NAND flash memory. The NAND flash memory cell structure and its operations were outlined. NAND flash memory chip array organization was also discussed. NAND flash chip fabrication processes and the tests performed on the devices at the wafer level and packaged die level were discussed. An overview of the failure analysis at wafer test and package test was described. Overall, this chapter provides the foundation and theory of the concepts and terminology required for a better understanding of the failure analysis methodologies undertaken in the next chapters. 47

62 CHAPTER 3 FAILURE ANALYSIS OF WAFER PROBE AND PACKAGE TEST Failure analysis plays a vital role in the development and manufacturing of integrated circuits [19]. It is important to keep a detailed record of failure rate at every stage of the chip manufacturing process. When the memory devices encounter an increase in the failure rate, the causes for it have to be determined as soon as possible so that production efficiency is not affected. Any similar future defects may be eliminated or rectified with alternative solutions. Failure analysis is performed at wafer probe to provide a feedback to the fabrication process engineers. It s cheaper for the industry to identify the defects at the earliest at wafer level so that they can be rectified early in the production cycle. However, the failures which are not caught at wafer probe shall be seen in package test because the parts are tested rigorously. This chapter provides in-sight into the failure analysis conducted at the wafer level and package level to identify defective parts, enabling quality and yield improvement of memory devices. 3.1 Analysis at Wafer Probe A NAND flash chip at wafer probe undergoes a series of electrical tests. Wafer probe analyzes the failures at each of these tests to detect the blocks and columns of NAND flash parts to be repaired. The failed blocks/columns are replaced by the redundant blocks/columns. There are extra columns and blocks built into the chip to provide repair solution information. This information provides the column/block being repaired and the

63 redundant column/block used for repair. This repair solution information is tracked to observe if there are more number of repairs which have an impact on the yield. For example, we can ascertain from this information if certain blocks/columns are being repaired the most or if a set of blocks/columns on one side of the array fail more than the other side, etc. The repair information is plotted and the trends are observed for abnormality. Failure analysis in this project was performed based on the repair solution information of a sample of 2Gb NAND flash parts. Column and Block repair analysis was performed on a 2Gb NAND flash part at wafer probe. The main objective was to observe any abnormal trends in the data. The following parametric tests were considered and repair data was extracted. Test to screen out grossly non-functioning bits Test for shorts that would lead to invalid data The tests mentioned above were considered for the analysis at wafer probe since the NAND flash parts have tendency to fail for these tests. Hence, there will be sufficient repair data for a sample of 2Gb NAND flash parts for analysis. 49

64 3.1.1 Procedure for the Extraction of Wafer Probe Repair Data The wafer probe repair data extraction process requires understanding of the concepts of probing and terminology of the semiconductor industry. The wafer probe repair data; i.e., block and column repair data used for the analysis, are extracted using web based tools and PERL scripts. A lot of time was spent extracting the necessary repair data from a large volume of test data using the PERL scripts. The following series of steps are involved in the repair data extraction used for failure analysis 1. Extraction of lots (A lot is a set of 25 wafers) that ran in wafer probe a few days back from the database using specific commands in UNIX. 2. Generation of Die ID s for each lot. Each wafer has about die with specific ID s associated with them to keep track of the information. About 20,000 die ID s are generated. 3. Repair solutions are obtained for each of the die. PERL scripts are developed to extract the necessary repair data for specific tests from large amounts of wafer probe data. 4. Specific parametric tests at hot sort are focused in wafer probe phase. These tests include the test to detect shorts and test to screen out non-functioning bits. The tests yielding more repair solutions are used for failure analysis in order to produce enough column repair data. 5. The block/column repair data is plotted to investigate the count of parts with a particular block/column repair in a sample of 2Gb NAND flash die. For example, in a sample of 20,000 die, a particular block 100 is repaired in 25 die. Here 25 50

65 represents count of parts where the 100 th block is repaired in a sample of 20,000 NAND flash die. The generated trends from the repair data and an analysis of the block/column failures are presented and discussed in the next sections Observation of the Trends/Patterns for Repair Data Repair analysis allows us to observe the trends in the NAND flash repair data and determine the reasons for any unexpected variations from the expected patterns. The block/column repair data generated for a sample of 20,000 individual die were plotted in Excel with the block/column number on the X-axis and the number of die which had a particular block/column repaired, or the number of times a particular block/column was repaired, on the Y-axis. The results are presented below. Column Repair Analysis A 2Gb NAND flash chip has typically rows and columns of flash cells arranged in an array. Columns are global bit lines, so the same column is repaired in all 2048 blocks. The parts are tested for column shorts in wafer probe and information about the failed columns is stored for repairing. The column repair data was extracted for a sample of 20,000 die, which were tested for column shorts in wafer probe. The column repair data for few columns is tabulated in Table 3.1. In the table, the data for every four columns i.e , 33754, and so on is shown. This is because one column repair consists of 4 physical columns being replaced. The column repair data from

66 33790 columns is presented, since it was observed that they are repaired a larger number of times when compared to other columns. The complete repair data of all the columns can be presented upon request as it is a large amount of data. The column repair data is normalized to the largest value, because the defect density is confidential at Micron Technology Inc. Sample Size 20,000 NAND Flash Parts #Parts having a particular column Column# repaired (Normalized Values) Table 3.1 Column Repair Data at Wafer Probe for 2Gb NAND Flash Parts A graph was plotted with the extracted column repair data tabulated in Appendix-A for 20,000 NAND flash parts at wafer probe using Excel. The resulting plot is as shown in FIGURE 3.1. Information about number of parts having a particular column repaired is known by plotting the column number on the x-axis and the count of parts for each of the columns repaired in a sample of 20,000 NAND flash die on the y- axis. It was observed from the generated trend in FIGURE 3.1, that for a sample of 52

67 20,000 NAND flash parts, the last few columns of an array have a higher repair rate than the other columns. A similar trend was observed for the other test at wafer probe which screens out non-functioning bits. The next section discusses the possible reasons for the observed trend. 1.2 Normalized Count of Parts with a Particular Column Repaired Column# ( ) FIGURE 3.1 Plot of Column Repair Data after Wafer Probe for 2Gb NAND Flash Parts Block Repair Analysis A 2Gb NAND flash memory is typically divided into 2048 blocks. Functional and parametric tests are conducted on the parts at wafer probe and information about the failed blocks is stored for repairing. The block repair data was extracted for a sample of 53

68 20,000 die, which were tested for shorts in wafer probe. The procedure for the extraction of block repair data at wafer probe is similar to that of the column repair analysis of section The block repair data for few blocks is tabulated in Table 3.2. In the table, the repair data for blocks 0-10 is presented, since it was observed that they were repaired more number of times when compared to other blocks. The complete repair data of all the blocks can be presented upon request as it is a large amount of data. The block repair data is normalized to the largest value as the defect density is confidential at Micron Technology Inc. #Parts having a particular column Block# repaired (Normalized Values) Table 3.2 Block Repair Data after Wafer Probe for 2Gb NAND Flash Parts A graph is plotted with extracted block repair data, tabulated in Appendix-B, for 20,000 NAND flash parts at wafer probe using Excel. The resulting plot is as shown in FIGURE 3.2. Information about the number of parts having a particular block repaired is known by plotting the block number on the x-axis and count of parts for each of the 54

69 blocks repaired on the y-axis. It was observed from the generated trend in FIGURE 3.2 that there is a decreasing pattern for the number of times a particular block is repaired. It is also observed from FIGURE 3.2 that Block-0 and Block-1 are being repaired the most. A similar pattern was generated for other test in wafer probe which screens out nonfunctioning bits. The following section discusses some possible reasons for the observed trends Normalized Count of Parts with a Particular Block Repaired Block# (0-2047) FIGURE 3.2 Plot of Block Repair Data after Wafer Probe for 2Gb NAND Flash Parts 55

70 3.1.3 Explanation for the Cause of the Generated Patterns Column Repair Analysis It was observed from the column repair analysis at wafer probe that last few columns towards the end of the array were repaired more when compared to the other columns. The column defects found were mainly due to the process variations such as metal width, etch time, implant variation, critical dimension variation, photo exposure, and chamber defects. Detailed explanations of some possible process induced reasons behind the failures of a particular column are explained below. Critical Dimension Variation: The critical dimensions of metal lines are thinner towards the edges of the die. This is because the chip is designed and fabricated in such a way that metal lines become dense and thinner towards the edges. This increases the resistance of the metal lines which decreases the charge flowing through them. This makes the bits slow to program and results in the subsequent failure of that particular column. This is one of the reasons behind the failure of the last column. This is a well known issue in fabrication but the failure rate is so small that there is no yield loss of die. Periphery Fails: The periphery is all of the circuitry that surrounds the array. All of the logic, latches, pumps, driver, and decoder are part of the periphery. If an entire column fails, it could be a problem in the periphery. For example, voltage pump is connected in the external circuitry to supply voltage to the parts. If the voltage 56

71 pump is not able to provide the necessary voltage to the flash cells for performing the operations they fail. Metal Widths: Metal lines could be shorted together during manufacturing of the part, causing columns to fail. The reason for this, may be contamination blocking the etch, photoresist or deposition. These are the process variations. FIGURE 3.3 illustrates such a failure of columns due to process variations. FIGURE 3.3 Column Fails due to Process Variations Early in the life of a new process, the column repair trend will have a higher failure rate towards the end of the flash array due to the process variations. But as the process matures and steps are optimized, edge defects are reduced and the curve flattens. Block Repair Analysis In the block repair trend generated at wafer probe in section 3.1.2, it was observed that block-0 and block-1 were repaired the most. Block 0 and block-1 are given priority over the other blocks for repair because it is one of the customer s requirements that block-0 and block-1 of the NAND flash part must be good. So, the probe engineers 57

72 repair the block-0 & block-1 more when compared to other blocks. This is to ensure that customer s specifications are satisfied. We can also see in the trend in FIGURE 3.2 that the block repairs are more towards both the edges of NAND flash array. Redundant blocks are the extra blocks built in the chip which can be used to replace the failed blocks. Typically there are about block repairs per die. First, the redundant blocks are used for repairing failed block-0 and block-1. Then other failed blocks of the die are repaired. During the sampling period, the repair algorithm starts repairing the bad blocks starting from block-0 and then continues down sequentially. So, the die is not left with enough redundant blocks towards the end for repair. Therefore, the blocks are repaired less towards the end. Thus, the block repair data analysis at wafer probe for a sample of 20,000 NAND flash die resulted in an expected pattern with more failures in both the ends of the flash array and is shown in FIGURE 3.2. An abnormal pattern was not observed for column repair analysis and block repair analysis at wafer probe. So, the failure analysis for the NAND flash memory at package test was done to look for abnormal patterns in order to search for the reasons behind the failure patterns. 3.2 Analysis at Package Test The packaged parts from assembly are passed through a test flow which is an electrical process that tests every part for parametric (operating currents, opens, shorts & input/output leakage), speed, and functional performance to device specification. In wafer probe, repair analysis is done whereas at package test failure analysis is the focused. This 58

73 is because by the time the product reaches package test it will be too late for repair. Analysis of the failed blocks at package test is done for the same 2Gb NAND flash parts since part of this thesis work is to look for any abnormal patterns and find the possible causes/explanation for these patterns. The more parts with failing blocks, the more data there is to analyze. Based on this criterion, the tests in electrical flash test flow were chosen for failure analysis and are listed below: Test I: Speed Timing Write Test ( High Corner Vcc) Test II: Speed Timing Write Test (Low Corner Vcc) Test III: Speed Timing Read Test Test IV: Speed Timing Write Test (logical checkerboard 0 test pattern) Test V: Read1 Test The block failure data for each of these tests were extracted for failure analysis, the procedure for the block failure data extraction is described in the next section Procedure for the Extraction of Package Test Failure Data The block failure data extraction involves coding in PERL. A clear understanding of the format of stored package test data in the semiconductor industry is necessary to perform this failure data extraction. The package test failure data used for the analysis was extracted using web based tools and PERL scripts. The following series of steps are involved in the block failure data extraction 59

74 1. Extraction of lots that ran in package test a few days back from the database using specific commands in UNIX. 2. Generation of Die ID s for each lot. About 20,000 die ID s are generated. Among them, the parts that have at least one block failing at a particular test are extracted using a PERL script. Parts generated for each lot and the tests conducted on them are given as input to this script. The number of parts that fail after this particular test is conducted is obtained as output. This sample of failed parts is used to obtain the block failure data as illustrated in step 3. The Scripts developed are not presented as they are proprietary to Micron Technology Inc. 3. The blocks which fail for specific tests for each of the failed parts are extracted from the sample generated in step 2. PERL scripts are developed to extract the block failure data for specific tests from large amounts of package test data. The scripts used for the generation of block failure data are not presented as they are confidential to Micron Technology Inc. 4. Specific tests conducted at package test such as Speed Timing Write Test and Speed Timing Read Test are chosen. This is because they have more repairs and have sufficient failure data for analysis. 5. The block failure data is plotted for selected tests after packaging to investigate the count of parts with a particular block fail in a sample of 2Gb NAND flash die. The block failure data at package test is thus extracted using the steps mentioned above for a sample of 2Gb NAND flash parts. The block failure data for 60

75 Speed Timing Read Test and Speed Timing Write Test at package test are extracted and plotted to look for abnormal patterns. The generated trends from block failure data at package test and an analysis of block failures are presented and discussed in the next sections Observation of the Failure Trends/Patterns for Different Package Tests In wafer probe, the trends generated from the column repair and block repair data were as expected. So, we focused on generating the failure trends for package test. The main purpose of analyzing the failure trends for different package tests is to look for any abnormal patterns, and to try to relate the patterns back to the design or the process to determine the causes. The trends observed for the various test runs are presented below: Test I: Speed Timing Write Test (High Corner Vcc) Speed Timing Write Test is conducted on the 2Gb NAND flash memory with high corner Vcc applied to the flash chip, which is typically about 3.7V. This test checks if all the blocks of NAND flash array are programmed with the logical checkerboard test pattern. If the test pattern is not written correctly onto the blocks of NAND flash array, they fail. The block failure data was extracted after the Speed Timing Write Test (High Corner Vcc) was conducted, using the procedure followed in section It was found that 12,000 NAND flash parts failed after this particular test. The block failure data was extracted from 12,000 NAND flash parts. The failure data gives the information about the normalized count of parts that have a particular block fail. The count of parts that fail to a 61

76 block is normalized to the largest value, because the information is confidential to Micron Technology Inc. The count of the parts having a particular block fail is plotted for all the blocks in the NAND flash array to observe the failure pattern. The resulting block failure pattern for the Speed Timing Write test is shown in FIGURE 3.4. Here x-axis represents blocks of the 2Gb NAND flash array; i.e., blocks, and the y-axis represents the number of parts having a particular block fail. It was thus observed from the trend generated that there is an increase in the block failure rate towards both the edges of the flash array. The explanation for the cause of generated pattern is presented in section SAMPLE SIZE: 12,000 NAND Flash Parts 62

77 1.2 1 Count of Parts with a Particular Block Fail Block# (0-2047) FIGURE 3.4 Plot of Block Fails after Speed Timing Write Test (High Corner Vcc) Test II: Speed Timing Write Test (Low Corner Vcc) Speed Timing Write Test is conducted on 2Gb NAND flash memory with low corner Vcc applied to the flash chip, which is typically about 2.6V. The blocks of the NAND flash array are programmed with a logical checkerboard test pattern in this test, and then the blocks are tested to determine the correct test pattern is written. The block failure data was extracted after the Speed Timing Write Test (Low Corner Vcc) was conducted, using the procedure followed in section It was found that 32,000 NAND flash parts failed after this particular test. The block failure data was extracted from these 32,000 NAND flash parts. This gives the information about the normalized count of parts that have a particular block fail. The count of parts that fail in a block after conducting the Speed Timing Write Test is normalized to the largest value because the 63

78 information is confidential to Micron Technology, Inc. A graph is plotted from the block failure data tabulated in Appendix D which is shown in FIGURE 3.5. In the plot, the x- axis represents the block numbers; i.e., of a 2Gb NAND flash array and y-axis represents the normalized count of flash parts with a particular block fail. The generated trend thus has higher block fails towards one end of the flash array when compared the other. The explanation for the cause of generated pattern is presented in section SAMPLE SIZE: 32,000 NAND Flash Parts Normalized Count of Parts with a Particular Block Fail Block# (0-2047) FIGURE 3.5 Plot of Block fails after Speed Timing Write Test (Low Corner Vcc) Test III: Speed Timing Read Test 64

79 Speed Timing Read Test is used to check if the blocks of the 2Gb NAND flash memory array are able to read the test pattern within data sheet timings. If the blocks of the flash array are not able to read the values within the time specified in the data sheet, they fail this particular test. The block failure data for 2Gb NAND flash memory was generated using the procedure followed in section The count of NAND flash parts that failed after this test was conducted was 14,000. The block failure data was extracted from these 14,000 NAND flash parts. A graph is plotted to investigate the count of flash parts that fail in each of the blocks; i.e., The plot is generated from the values failure data, with block numbers on the x-axis and the count of parts that fail to a particular block on the y-axis. A normalized count of the parts is presented because the data is confidential to Micron Technology, Inc. Thus, from the generated trend as shown in FIGURE 3.6 it can be seen that there is higher failure rate at the edges than the middle of the flash array. The explanation for the cause of generated pattern is presented in section

80 SAMPLE SIZE: 14,000 NAND Flash Parts Normalized Count of Parts with a Particular Block Fail Block# (0-2047) FIGURE 3.6 Plot of Block Fails after Speed Timing Read Test Test IV: Speed Timing Write Test (with logical 0 checkerboard test pattern) Speed Timing Write Test is conducted on the 2Gb NAND flash parts which checks whether a logical 0 test pattern is written correctly onto the flash array. This logical 0 test pattern is different from the physical checkerboard pattern and logical checkerboard test pattern. The blocks of flash array are programmed to a logical 0 checkerboard test pattern to check whether the pattern is written and within the datasheet specified timings. The series of steps discussed in section are followed for the extraction of block failure data on the 2Gb NAND flash memory. 9,000 NAND flash 66

81 parts failed after this particular test. The block failure data was extracted from these 9,000 NAND flash parts. This failure data gives the information about the normalized count of parts that have a particular block fail. The count of parts that fail in a block after conducting the Speed Timing Write Test is normalized to the largest value because the information is confidential to Micron Technology Inc. A graph is plotted from the block failure data which is as shown in FIGURE 3.7. In this plot, the x-axis represents the block numbers; i.e., of the 2Gb NAND flash memory and the y-axis represents the normalized count of flash parts with a particular block fail. Thus, the generated trend has higher block fails at both the edges of the flash array. The explanation for the cause of generated pattern is presented in section

82 SAMPLE SIZE: 9,000 NAND Flash Parts Normalized Count of Parts with a Particular Block Fail Block# (0-2047) FIGURE 3.7 Plot of Block Fails after Speed Timing Write Test (with logical 0 checkerboard test pattern) Test V: Read1 Test Read1 Test is conducted on the blocks of the NAND flash array with low corner Vcc applied to the parts after an erase operation was performed to verify that all the blocks are in an erased state. The blocks in the NAND flash array should be 1 when they are read after an erase operation. If the blocks of the array do not have value 1 after the Read1 Test is conducted, they fail this test. The block failure data was extracted after Read1 Test was conducted, using the series of steps mentioned in section It was found that 3,000 NAND flash parts failed after this particular test. The block failure data was extracted from 3,000 NAND flash parts and is tabulated in Appendix A. This table gives the information about the normalized count of parts that have a particular block fail. The 68

83 count of parts that fail to a block is normalized to the largest value because the information is confidential to Micron Technology Inc. The normalized count of the parts having a particular block fail is plotted for all the blocks in the NAND flash array to observe the failure pattern. The resulting block failure pattern after Read1 Test is shown in FIGURE 3.8. Here, the x-axis represents the blocks of the 2Gb NAND flash array; i.e., blocks, and the y-axis represents the number of parts having a particular block fail. The plot in FIGURE 3.8 shows that the number of blocks that failed at this particular package test had an abrupt increase in the middle of the array and towards the ends. There was a higher failure rate for the blocks in between 0-15, and SAMPLE SIZE: 3,000 NAND Flash Parts Normalized Count of Parts with a Particular Block Fail Block# (0-2047) FIGURE 3.8 Plot of Block Fails after Read1 Test 69

84 The block failure analysis was done for five package tests for the 2Gb NAND flash memory. The plots generated from the block failure data gave us the information about the number of parts that have a particular block fail. It was observed that Speed Timing Write Tests and Speed Timing Read Test resulted in the trends that had increase in block failure rate towards both the edges of the NAND flash array. However, the blocks that underwent the Read1 Test were found to have a trend which is different when compared to other four package tests conducted on the flash parts. The blocks 0-15, , and had larger number of failed blocks after the Read1 Test than the failed blocks after Speed Timing Write Tests and Speed Timing Read Test. Read1 Test resulted in higher block failure rate towards the middle and edges of the array as compared to other blocks in the array. The reason for this increase in block failure rate after the Read1 Test was conducted must be determined. The following section discusses the cause for the generated trends after the package tests are conducted on the flash parts Explanation for the Cause of the Generated Patterns It was observed from the trends presented in the previous section that Speed Timing Write Test (High Corner Vcc), Speed Timing Write Test (Low Corner Vcc), Speed Timing Write Test (with logical checkerboard 0 test pattern) and Speed Timing Read Test resulted in an increase of failed blocks on both the edges as compared to the middle of the NAND flash array. Typically, the critical dimensions of the parts towards the edge of the array are smaller because the array boundaries of the chip are denser, causing developing or etching differences near the edges of the array. Smaller critical 70

85 dimensions increase the resistance of the flash cells toward the edges of array. The increase in the resistance of the flash cells implies a higher voltage is needed to turn on the transistors. Thus, smaller critical dimensions results in an increase in the threshold voltage of flash cells. Because of this increase in threshold voltage, the control voltage applied to the flash cells is not sufficient to program the flash array. This causes the flash cells towards the edge of the array to be programmed slowly. When the blocks towards the edges of the array are tested, they tend to fail more than the other blocks of the array. Thus, when Speed Timing Write Test (High Corner Vcc), Speed Timing Write Test (Low Corner Vcc), Speed Timing Write Test (Logical checkerboard 0 test pattern) and Speed Timing Read Test are conducted on the NAND flash parts, the blocks towards the both the edges of the array fail. Thus, the patterns generated for these tests were as expected. However, after Read1 Test it was seen that there was an increase in the block failure rate towards the edges of the array and in the middle of the array from blocks Block failure analysis of 2Gb NAND flash parts for the Read1 test resulted in an unexpected pattern, specifically the increase in block failure rate in the middle of the array. At this stage in the research the exact reason for this increase in the failure rate of blocks was not known. 71

86 3.2.4 Variation of Trend for the Failure Data of Read1 Test The block failure trend at Read1 Test deviates from the trends generated at other package tests. The tests are conducted in the package test process to catch the block fails before the parts are shipped to the customers. There would be higher block fails on both edges of the array because the flash cells are programmed slowly and hence the cells are not programmed correctly. This would be an expected pattern after the tests are conducted on the NAND flash parts in Package Test. Therefore, the Speed Timing Write Tests and Speed Timing Read Test generated expected trends as shown in FIGURE 3.9. But, the Read1 Test resulted in an increase in block failure rate in middle of the array along with the edges of the flash array. This is an unexpected trend. FIGURE 3.10, shows the unexpected trend that resulted in the higher block failure rate from blocks 0-15, , and The block failure trend at Read1 Test is unexpected as there was an increase in the failed blocks in the middle of the array. The plots in FIGURE 3.9 and FIGURE 3.10 show the expected and unexpected trends at Read1 Test for 2Gb NAND flash parts respectively. Systematic approaches must to be made to determine the exact cause for the higher failure rate of blocks 0-15, , and We discuss in the next chapter the methodologies followed to determine the cause for the unexpected pattern generation of block failure after Read1 Test. 72

87 Normalized Count of Parts with a Particular Block Fail Block# (0-2047) FIGURE 3.9 Plot of Expected Trend after Read1 Test Normalized Count of Parts with a Particular Block Fail Block# (0-2047) FIGURE 3.10 Plot of Unexpected Trend after Read1 Test 73

88 3.3 Summary In this chapter, we presented the failure analysis performed at wafer probe and package test. The trends generated at wafer probe and package test were observed. The trends generated for the tests at wafer probe were as expected and the reasons for the generation of the failure trends were explained clearly. In package test, five tests for a sample of 2Gb NAND flash parts were considered for analysis. The plots generated from the block failure data gives information about the number of parts which have a particular block fail. The trends generated for four tests were similar. However, an abnormal trend was observed for Read1 Test. We discuss in next chapter, the methodologies followed to determine the reason for the increase in the block failure rate after Read1 Test. 74

89 CHAPTER 4 METHODOLOGIES FOR THE DETECTION OF HIGH BLOCK FAILURE RATES AFTER READ1 TEST As discussed in the previous chapter, the 2Gb NAND flash parts that were tested at Read1 Test, exhibited a pattern that deviated from other package tests. It was presented in Chapter 3 that Speed Timing Write Test (High Corner Vcc), Speed Timing Write Test (Low Corner Vcc), Speed Timing Write Test (with logical checkerboard 0 test pattern) and Speed Timing Read Test resulted in an increase of failed blocks on both the edges when compared to the middle of the NAND flash array. However, the Read1 Test had a higher failure rate for blocks in the middle of the array i.e along with the blocks towards the edges of array i.e and as shown in FIGURE 3.8. The increased failure rate decreases the yield of a die. This will have a direct impact on the quality of the final product and the efficiency of production. Hence it is pivotal for the semiconductor industry to diagnose the parts with failed blocks and resolve such problems. This research employs a systematic approach to this problem that will attempt to analyze all possible parameters that are responsible for failure of the parts. It will reduce the uncertainty window and help in getting to the crux of the problem. In the thesis work, three different methodologies were investigated to determine the reason for the increase in the block failure rate at Read1 Test. The three methodologies followed are Extraction of History on the Parts with High Failure Rate, Use of Wafer Map Tool to Determine the Causes for the Increase in the Block Failure Rates and Package Tests Performed on Parts

90 with Higher Failure Rate. In this section, we provide a detailed discussion on the sequence of different approaches we made to determine the possible causes for the higher block failure rate in a sample of NAND flash parts. 4.1 First Approach Extraction of History on the Parts with High Failure Rate The seemingly obvious and best approach for determining the increase in block failure rate would be to gather all the information about the failed blocks. The failure data at fabrication, wafer probe, and package phases may possibly lead to some particular parameters responsible for increase in block fails in a sample of NAND flash parts. Device failures are traced using the part information stored during wafer probe, assembly, and package test. The historical information about the parts with higher failure rate is stored at every stage of die manufacturing. This historical information is extracted to scrutinize any major failures and determine the causes for the failure. The information extracted on the NAND flash parts with failed blocks is discussed below. The failed parts were first grouped based on attributes. Attributes are the parameters which uniquely identify the part. The following is a list of some of the many attributes available that are important to this discussion. Country of assembly: Determines the location of the plant where the parts were built. Categories of country of assembly are US and China. Categories are different parts of an attribute. 76

91 Product Grade: Classifies the quality of the part based on the following unique levels of quality classifications. The categories of product grade are as listed below. o Level 1 : Cleanest die (Die which meet all the standard data sheet specifications) o Level 2 : Die with a lower quality (Die which partially meet the data sheet specifications) o Level 3 : Die with poor quality (The die that does not meet data sheet specifications with respect to speed tests or stress tests, but is functionally operational; i.e., passes parametric tests and margin tests.) Machine Model: The designated make and model number of the machine which electrically tested the failed parts. Machine ID: The unique identification number of the machine which tested the failed parts. Operator ID: The ID of the operator who conducted the tests. The failed parts were grouped based on the attributes listed above using PERL scripts. A large amount of information is stored in the database about the manufactured parts. A lot of time was spent in extracting the necessary data from a large volume of data. The scripts that were developed earlier in the company would only give the information about attributes associated with a particular part. But for the thesis work, PERL scripts were written to group all the failed parts with the same attribute. The particular scripts written 77

92 are not presented in this thesis as it is confidential information at Micron Technology Inc. The failed parts were grouped based on the test attributes and plotted to determine the percentage of parts failed, due to a particular attribute. In other words the main purpose was to determine whether the higher percentage of particular block fails was due to a particular attribute. For example, consider the machine ID test attribute. It may be possible that a particular machine is not functioning properly and the parts were manufactured using that machine. So, by grouping the failed parts based on test attributes we shall come to know if a particular machine, operator or country of assembly is responsible for increase in the block fails. From the data extracted it was observed that each category of the attribute contributed equally towards the block failure. There was no such category in any of the attributes that resulted in a higher block failure rate when compared to others. There were an equal percentage of failed blocks for each of the categories of an attribute. It was thus observed that no particular attribute was responsible for the higher failure rate for blocks 0-15, , and Although this methodology could not be used to determine the cause for the increase in block fails after Read1 Test, it did provide a good starting point. 78

93 4.2 Second Approach - Use of Wafer Map Tool to Determine the Causes for the Increase in Block Failure Rates Since the analysis of external parameters described in the previous section did not provide a solution to the problem, an in-depth analysis was needed. Before proceeding with any further analysis it is necessary to know the location on the wafer of the parts with higher block failure rate. This may lead to the reasons behind the higher failure rate. Wafer Map Tool was used for this purpose. Wafer Map Tool is a complex software tool which plays a useful role in failure analysis by visually presenting large amounts of die information onto a wafer map. Wafer Map Tool allows us to collect, edit, analyze, and visualize measured physical parameters on semiconductor wafers. Details about the Wafer Map Tool were described in Chapter 2. The usage of Wafer Map Tool for this project requires a clear understanding of its operation for effective use in failure analysis. The fabrication group stores the information about the location of the part/die on the wafer in a database during manufacturing. The information stored provides die ID, Wafer ID, and location of die (Xlocation and Y-location). When the die ID is provided to the Wafer Map Tool, it looks in the database for the wafer ID on which the die was manufactured and then for the location of die. It then shows the location of part on the wafer map. Wafer Map Tool can thus be used to determine the location of parts on the wafer by viewing the wafer map generated. Wafer Map Tool was employed to map the location of the NAND flash parts with failed blocks after Read1 Test to a wafer map. A lot of time was spent putting a large volume of block failure data; i.e., sample of 3,000 failed NAND flash parts, onto 79

94 the wafer map. It was important to identify the part from which the failed block occurred and that the die ID of failed block was stored correctly. This stored information was then presented as input to the Wafer Map Tool. The Wafer Map Tool then presents the exact location of the NAND flash parts with failed blocks on the wafer based on the die ID. The actual wafer map obtained could not be presented as the information of die density on the wafer is confidential to Micron Technology Inc. However, the wafer map schematic layout shown in FIGURE 4.1 is similar to the actual wafer map obtained. This figure presents the location of parts with block fails after Read1 Test was conducted on the 2Gb NAND flash parts. The blue color in the wafer map represents the maximum parts where blocks 0-15, , and failed. The red color indicates the minimum parts where blocks 0-15, , and failed. The dark green, light green and yellow colors in the wafer map indicate the location of parts whose count is between maximum parts and minimum parts for which blocks 0-15, , and fail. Thus, wafer map generated in FIGURE 4.1 using Wafer Map Tool shows the location of NAND flash parts for which blocks 0-15, , and fail. 80

95 ACTUAL SAMPLE SIZE USED 3,000 NAND Flash Parts FIGURE 4.1 Wafer Map of NAND Flash Parts after Read1 Test Note: Blue Location of Parts having maximum number of block fails Red Location of Parts having minimum number of block fails The main objective of analyzing block failure data on NAND flash parts using a Wafer Map Tool was to obtain information about the parts corresponding to failed blocks on the wafer. This determines to know the concentration of parts with higher block failure rate on any particular area of the wafer. Based on these results, a detailed analysis can be performed which may lead to design or manufacturing related issues. From the above wafer map in FIGURE 4.1, it can be observed that the parts with failed blocks were not concentrated in a particular region of the wafer. This approach to evaluate the reasons for the higher failure rate was also not conclusive as the location of parts that fail at read1 package test were randomly distributed on the wafer. The NAND flash parts with higher block fails were not concentrated on the wafer map. So, further analysis is 81