Tekmos. TK87C751 80C51 Microcontroller, 64K ROM, TWI. Features. General Description TK87C751 P3.7 P1.7 P1.6 P3.0 P0.2 P0.1 P0.0 P1.

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1 Tekms DS075 (V1.0) July 19, 2007 Features TK87C751 80C51 Micrcntrller, 64K ROM, TWI General Descriptin Data Sheet 8 Bit Micrcmputer with 8051 architecture 64Kx8 internal Flash based ROM, 128x8 RAM Reprgrammable Lw standby current at full supply vltage 0-20 MHz peratin Classic architecture instructin timing 3 bidirectinal prts (19 bits) 28 pin PLCC package Built in pwer management Tw Wire Interface (TWI) (I2C TM cmpatible) 16 bit timer/cunter with aut-relad. Fixed rate timer LED cmpatible utputs Direct replacement fr Philips 87C751 / 87C751 micrcntrllers. Implemented with the Tekms Custmer Cnfigured Micrcntrller (CCM) technlgy. NC P3.0 P0.2 P0.1 P0.0 NC P3.1 4 P3.2 3 P3.3 2 P3.4 1 VDD TK87C RST P P P P3.7 P1.7 P1.6 NC NC P1.5 The TK87C751 is a derivative f the 8051 micrcntrller architecture. With 64Kx8 f Flash ROM, and 128x8 f scratchpad RAM, this part is a pin-fr-pin replacement f the NXP 87C751 micrcntrller. The TK87C751 is intended t prvide the 80C51 architecture in a small package and with a hardware Tw Wire Interface (TWI). The integrated TWI interface allws the TK87C751 t perate as either a master r a slave n the TWI bus. T achieve this, prt P2, and 5 bits f prt P0 were remved, alng with the external bus cntrl pins. This allws the TK87C751 t fit within either a 24 pin, 300 mil PDIP package, r a 28 pin PLCC package. The 28 pin versin is available nw. The 24 pin versin will be available early in The 8051 architecture has been mdified t prvide a Tw-Wire Interface (TWI). Starting with the basic 80C51 design, the serial prt and the tw timers in the 80C51 were remved and replaced with the TWI interface and its assciated timers. The external interrupt pins and the timer gate and cunt pins were relcated frm prt P3 t prt P1. The interrupt cntrller was simplified t prvide nly a single set f pririties. The ability f the design t access external prgram and data memry was als remved, alng with the PSEN, ALE, and EA pins. Because the TK87C751 utilizes a Flash ROM, it may be re-prgrammed if required. The riginal part was a One-Time-Prgrammable (OTP) part. The TK87C751 is built utilizing the Tekms Custmer Cnfigured Micrcntrller (CCM) technlgy. Refer t the CCM data sheet fr details n creating ther micrcntrllers. I2C is a registered trademark f Philips Crpratin. P1.3 P1.2 P1.1 P1.0 VSS X1 X2 7/19/07

2 Tekms TK87C751 Micrcntrller Pin Descriptins PLCC PDIP Name Descriptin Prgramming 1 1 P3.4 Prt 3. Bit 4 A4 2 2 P3.3 Prt 3. Bit 3 A3 3 3 P3.2 Prt 3. Bit 2 A2 4 4 P3.1 Prt 3. Bit 1 A1 5 NC 6 5 P3.0 Prt 3. Bit 0 A0 7 6 P0.2 Prt 0. Bit 2 OE (Read = 1) 8 7 P0.1 / SDA Prt 0. Bit 1 + TWI data WEn (Write = 0) 9 8 P0.0 / SCL Prt 0. Bit 0 + TWI clck Address Strbe 10 NC 11 9 RST Active high reset Reset, and cntrl mde input XTAL2 Crystal Oscillatr Output XTAL1 Clck / Crystal Oscillatr Input Clck Input VSS Grund Grund P1.0 Prt 1. Bit 0 D P1.1 Prt 1. Bit 1 D P1.2 Prt 1. Bit 2 D P1.3 Prt 1. Bit 3 D P1.4 Prt 1. Bit 4 D P1.5 / INT0n Prt 1. Bit 5 + External interrupt 0 D5 21 NC 22 NC P1.6 / INT1n Prt 1. Bit 6 + External interrupt 1 D P1.7 / T0 Prt 1. Bit 7 + Timer 0 clck / gate D P3.7 Prt 3. Bit 7 A P3.6 Prt 3. Bit 6 A P3.5 Prt 3. Bit 5 A VDD Psitive Supply Psitive Supply (5V) Architecture The TK87C751 architecture cnsists f a classic 8051 cre cntrller surrunded by the TWI cntrller, three general purpse I/O prts, tw timer cunters, an interrupt cntrller, 64 bytes f RAM, and 2K bytes f ROM Cre The 8051 cre, register set, instructins, and timing are the same as in the classic The MOVX instructins exist, but are meaningless since the TK87C751 cannt access external memry. Likewise, the data pinters (DPTR) are still present, but serve n purpse ther than general purpse registers. I/O Prts The TK87C751 has 3 f the riginal 4 8-bit bidirectinal I/O prts. Prts 1 and 3 are the same as in the classic Prt 0 has been reduced t 3 bits, and prt 2 has been remved. All prts are mapped int the SFR address space and may be directly perated n by instructins. The prt bits are cnfigured as bidirectinal pins. Writing a 1 t the prt allws that bit t be cnfigured as an input. Prt 0 Prt 0 has been reduced t 3 bits. These bits are bidirectinal ñ pen drain pins. The TWI interfaces thrugh P0.0 (SCK) and P0.1 (SDA). These pins are strnger s as t meet the electrical requirements f the TWI bus /19/07

3 Tekms TK87C751 Micrcntrller P0 - Prt 0 Pin Name Alternate Functin P1.0 SCK TWI Clck P1.1 SDA TWI Data P1.2 Prt 0 is lcated at address 80H. Prt 1 These bits are bidirectinal pins, with a pullup present n all pins. Many f the special functin cntrls that were n Prt 3 in the riginal 8051 have been relcated t Prt 1. The fllwing table shws the new bit assignments. P1 - Prt 1 Pin Name Alternate Functin P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 INT0 External Interrupt 0 P1.6 INT1 External Interrupt 1 P1.7 T0 Timer 0 Clck / Gate Prt 1 is lcated at address 90H. Prt 2 Prt 2 has been remved frm the design. Prt 3 Prt 3 pins supprt the serial prt, Timer 0, Timer 1, the external interrupt functins, and the read and write strbes fr the external data space. Prt 3 is lcated at address B0H. Read-Mdify-Write Instructins Since each prt pin is cnfigured as an pen-drain, it is pssible fr the cntents f the prt latch t differ frm the value at the pin. Instructins that read the prt reference the value at the pin. An exceptin t this is a set f instructins that perfrm a read-mdify-write functin. These instructins read the cntents f the prt latch, mdify it, and write it back ut. The read-mdify-write instructins are: Precharge ANL CLR B CPL DEC DJNZ INC JBC MOV B, C ORL SET B XRL Each pin in Prt 0 is cnfigured as a bidirectinal pen-drain when it is used as a prt. The ther tw prts have an internal pull-up resistr n each pin. In additin, whenever a prt makes a 0 t a 1 transitin, a precharge ccurs fr tw crystal clck cycles. This precharge imprves the rise times f the prt pins. The precharge als ccurs during the alternate prt functins. Serial Prt The serial prt and the assciated special functin registers have been remved frm the TK87C751. Timers The Timer 0 and Timer 1 functins in the classic 8051 have been extensively mdified fr use in the TK87C751. The TK87C751 has tw timers: Timer 0 is a 16-bit timer/cunter. Timer I is a 10-bit fixedrate timer. The peratin f Timer 0 is similar t the mde 2 peratin in the classic 8051, but with 16 bits. Timer 0 is clcked by either T0 externally, r by 1/12 f the scillatr frequency internally. This is cntrlled by the C/T pin in special functin register TCON. Timer 0 is enabled when the TCON TR (Timer Run) bit is set. The clck surce increments the TL and TH register pair. When the register pair verflws, it is reladed with the cntents f the RTL and RTH register pair. The relad value des nt change. See the TK87C751 cunter/timer blck diagram fr further details. When Timer 0 verflws, it sets the TF bit in the TCON register. This will generate an interrupt if the interrupt has been enabled /19/07

4 Tekms TK87C751 Micrcntrller Clck Cntrl There is cnsiderable flexibility in the cntrl f the clck fr either timer. The C/T bit in the TCON register selects the surce f the clck. Setting it t a ne selects the external T0 pin as a clck surce, while clearing it t a zer selects the internal clck. After the surce has been selected, it is further cntrlled by the TR bit f the TCON register. Clearing this bit blcks the clck and prevents peratin. Setting the bit enables the clck. The clck can als be cntrlled by the GATEn bit in the TCON register. Setting this bit allws the external interrupt pin t gate the clck. A 1 n the external interrupt pin enables the clck. The clck cntrls act as an enable n the clck generatr. This prevents spurius clcks frm being generated when the cntrls are switched. Clck Speed When perating ff the internal clck surce, the timers will be incremented nce every machine cycle. Since there are twelve external clcks per machine cycle, the maximum cunt frequency is Fsc/12. External pins are sampled nce per machine cycle. If the external clck surce is selected, it will take tw machine cycles t create a cmplete clck wavefrm, thus making the maximum external clck frequency Fsc/24. While there are n limitatins n the external clck duty cycle, care must be taken t insure that the clck signal has been sampled crrectly during the S5P2 time. This is easily accmplished by maintaining the external timer clck in a given state fr a minimum f ne machine cycle. Interrupts The setting f the TF bit in the TCON register triggers an interrupt request. The TF bit is reset by hardware when the requested interrupt is acknwledged. The TCON register als cntrls the external interrupts. These functins are explained in the interrupt sectin. The Timer Data Registers Each timer cnsists f a lwer register (TL) and an upper register (TH). These registers are treated as any ther SFR register and may be read frm r written t at any time. These registers are unbuffered and represent the current cunt value. The data registers are mapped int the SFR address space at the fllwing lcatins: Register Address TL0 8AH TL1 8BH TH0 8CH TH1 8DH The Timer Cntrl Register With the remval f Timer 1, the remaining cntrl functins have been cnslidated in the TCON register. The TMOD register has been remved. As with the data registers, the cntrl registers may be treated as any ther SFR register, and may be read frm r written t at any time. The TCON register cntrls the enable fr Timer 0, the timer interrupt bit, the edge selects fr external interrupts and the external interrupt bits. Interrupt bits generate the interrupt and may be set by sftware as well as hardware. Here are the bit assignments fr the TCON register. Nte that the bit psitins are different than thse used in the classic Address Reset value = 88h = 00h TCON ñ Timer Cntrl Register Pin Name Functin TCON.7 GATE Timer 0 Clck / Gate TCON.6 C/T Cunter / Timer Mde TCON.5 TF Timer Flag TCON.4 TR Timer Run TCON.3 IE0 External Interrupt 0 TCON.2 IT0 INT0 Edge Select TCON.1 IE1 External Interrupt 1 TCON.0 IT1 INT0 Edge Select GATE 1 = Timer enabled when INT0 and TR are high. 0 = Timer enabled by TR nly /19/07

5 Tekms TK87C751 Micrcntrller C/T Cunter / Timer 1 = Clck frm external T0 pin. 0 = Clck frm internal clck. TF ñ Timer Flag 1 = Overflw ccurred n TH, request interrupt. This bit is cleared by the interrupt acknwledge. TR ñ Timer Run 1 = Timer runs 0 = Timer ff IE0 1 = Interrupt detected n INT0 0 = N interrupt n INT0 IT0 1 = Interrupt n falling edge f INT0 0 = Interrupt n INT0 = 0 IE1 1 = Interrupt detected n INT1 0 = N interrupt n INT1 IT1 1 = Interrupt n falling edge f INT1 0 = Interrupt n INT0 = 1 Tw Wire Interface The Tw Wire Interface (TWI) uses bidirectinal clck (SCK) and data (SDA) lines t transfer data between multiple devices. In the TK87C751, the TWI lgic cntains hardware t simplify the sftware required t interface with the bus. The hardware is a single bit interface that includes bus arbitratin lgic, framing errr detect, clck stretching, and a timer fr bus timeut. The hardware interfaces t the sftware thrugh either interrupts r plling. Timer I Timer I cntrls the six critical time spans in the TWI architecture. These are: 1. The minimum high time fr SCL when in master mde. 2. The minimum lw time fr SCL when in master mde. 3. The minimum SCL high t SDA high time fr a stp bit. 4. The minimum SDA high t SDA lw time between stp and start bits. 5. The minimum SDA lw t SCL lw time in a start bit. 6. The maximum SCL change time within a frame. The three lw rder bits f timer I cntrl the first 5 times. Selecting the apprpriate value based n the scillatr speed will allw these times t be the 4.7us required by the TWI specificatin. The upper 10 bits f Timer I cntrl the maximum SCL change time. This cunter is started by a start bit, cleared by every SCL transitin, and turned ff by the stp bit. Depending n the preset cnditin cntrlled by I2CFG, Timer I will timeut after frm 1020 t 1023 machine cycles. At that pint, it will clear the TWI hardware, and if enabled, generate an interrupt. TWI Interrupts The TWI will try t generate an interrupt when the ATN flag is set. The ATN flag is the OR f fur cnditins: start, stp, data ready, r lss f arbitratin. Because f the sftware verhead necessary t determine which cnditin created the interrupt, it is nt practical t use interrupts fr the main I2C peratin. Instead, it is recmmended that interrupts be used t detect a start bit in an idle slave mde, r a stp bit in an idle master mde. I2CON ñ TWI Cntrl Register Address Reset value = 98h = 81h I2CON - TWI Cntrl - Write Bit Name Functin 7 CXA Clear Transmit Active 6 IDLE Enter idle mde 5 CDR Clear Data Ready (DRDY) 4 CARL Clear Arbitratin Lss 3 CSTR Clear Start Bit 2 CSTP Clear Stp Bit 1 XSTR Transmit Repeated Start 0 XSTP Transmit Repeated Stp 5 7/19/07

6 Tekms TK87C751 Micrcntrller I2CON - TWI Cntrl - Read Bit Name Functin 7 RDAT Receive data 6 ATN Lgical OR f DRDY, ARL, STR, and STP 5 DRDY Data Ready 4 ARL Arbitratin Lss 3 STR Start Bit Detected 2 STP Stp Bit Detected 1 MASTER Master Mde 0 x The bits in the TWI cntrl register (I2CON) have different values, depending n whether the register is being read r written t. As a result, it shuld NOT be used with Read-Mdify-Write instructins. I2CON Register ñ Write CXA Writing a 1 t this bit clears the transmitter active state. This state is als cleared by reading the I2DAT register. The transmitter active state is entered by writing t the I2DAT register, r by setting the XSTR r XSTP bits in the I2CON register. The TWI must be in the transmitter active state t drive the SDA line lw. The transmitter must als be active in rder t have the ARL bit set. The transmitter active state is cleared by either reading the I2DAT register, r by setting the CXA bit. The transmitter active state is autmatically cleared with the setting f the ARL bit. IDLE Setting the IDLE bit causes a TWI slave t ignre the TWI bus until the next start bit ccurs. If MASTRQ is set, then the TWI will becme a master after the next stp bit is received. CDR Setting this bit clears the DRDY bit. The data ready bit is als cleared by reading r writing the I2DAT register. CARL Setting this bit clears the arbitratin lss bit (ARL). CSTR Setting this bit clears the start bit (STR). CSTP Setting this bit clears the stp bit (STP). Nte that if any f the DRDY, ARL, STR r STP bits is set, then the TWI hardware will extend the SCL lw time until the bit has been cleared. XSTR Setting this bit generates repeated start bits. It shuld be nly used in the master mde. It shuld nt be used t generate the initial start bit in a data packet. That start bit is generated autmatically by the TWI hardware. XSTP Setting this bit generate a stp bit. It shuld be nly used in the master mde I2CON Register ñ Read RDAT This bit in the I2CON register is a duplicate f the same bit in the I2DAT register. Hwever, reading the RDAT bit here des nt clear the DRDY bit. In a typical applicatin, the first 7 received bits are read frm the I2DAT register. The 8th bit is read here. Then the ACK respnse is written t the XDAT bit, which clears DRDY. ATN The attentin bit is high whenever any f the DRDY, ARL, STR, r STP bits is a 1. It prvides a single sftware test fr TWI status. Any f these cnditins will extend the SCL lw time until they have been cleared. Failure t clear all bits can result in a hung bus. DRDY The Data Ready bit is set n the rising edge f SCL, except when the part is perating as an idle slave. DRDY can be cleared by writing t the CDR bit, r by reading frm r writing t the I2DAT register /19/07

7 Tekms TK87C751 Micrcntrller Once SDL returns lw, it will remain lw until the DRDY bit has been cleared. ARL ARL = 1 means that an arbitratin lss has ccurred. The setting f the ARL bit will als clear the transmit active state. There are fur cnditins that will set the ARL bit. 1. The 87C751 tried t send a 1, but SDA was a zer at the rising edge f SCL. 2. The 87C751 tried t send a 1, but SDA went lw while SCL was still high. 3. The 87C751 tried t send a start bit, but anther device drve SCL lw befre the 87C751 culd drive SDA lw. 4. The 87C751 tried t send a stp bit, but anther device was hlding the SDA line lw. In any f the abve cnditins, ther bits such as STR r STP may be set, depending n the actual TWI signals. STR The STR bit is set when a TWI start cnditin has been detected n the TWI bus and the TWI hardware is perating as either a nn-idle slave r as a master. STP The STP bit is set when a TWI stp cnditin has been detected n the TWI bus and the TWI hardware is perating as either a nn-idle slave r as a master. MASTER MASTER = 1 indicates that the TWI hardware is currently the master n the WI bus. MASTER is set when MASTRQ is a 1 and the TWI bus is nt busy. MASTER is cleared when ARL is set, f after sftware has cleared the MASTRQ bit, and then set the XSTP bit. I2DAT ñ TWI Data Register Address Reset value = 99h = 80h XDAT I2DAT - TWI Data Bit Name Functin 7 XDAT RDAT Transmit Data (Write) Receive Data (Read) 6 x Nt used 5 x Nt used 4 x Nt used 3 x Nt used 2 x Nt used 1 x Nt used 0 x Nt used Transmit data bit. Writing t the XDAT bit defines the next bit t be transmitted n the TWI bus. It als clears the DRDY bit and sets the Transmit Active state. The XDAT data is nly applied t the SDA pin when SCL is lw. This prevents the accidental creatin f a start r stp bit. It als remves critical timing cnsideratins frm the sftware transmit rutines. RDAT Receive data bit. This bit is laded frm the SDA pin n every rising edge f SCL. Reading this bit clears the DRDY bit. It als clears the Transmit Active state. The hardware will delay the rising edge f SCL until the RDAT bit has been read. This remves critical timing cnsideratins frm the sftware receive rutines. Of curse, the data must be read befre Timer I has timed ut, which is a minimum f 750 us. I2CFG ñ TWI Cnfiguratin Register Address Reset value = D8h = 0000xx00 I2CFG - TWI Cnfiguratin Bit Name Functin 7 SLAVEN Slave enable 6 MASTRQ Bus master request 5 CLRTI Clear Timer I interrupt 4 TIRUN Timer I run 3 x Nt used 2 x Nt used 1 CT1 Cntrl timer bit 1 0 CT0 Cntrl timer bit /19/07

8 Tekms TK87C751 Micrcntrller SLAVEN Writing a 1 t the SLAVEN bit puts the TWI interface int the slave mde. This bit is cleared by a TWI time ut and reset. MASTRQ Setting MASTRQ t a 1 generates a request t becme the bus master f the TWI bus. If anther bus cycle is in prgress, then the TWI waits until a stp bit has been received. Once the bus is available, the TWI sends a start bit and sets the DRDY bit in the I2CON register. This in turn sets the ATN bit and generates an interrupt. Writing a 1 t the XSTP bit in the I2CON register will release the TWI bus. The MASTRQ bit is cleared by a TWI time ut and reset. The TWI hardware is disabled when bth SLAVEN and MASTRQ are 0. CLRTI The Timer I interrupt flag is cleared by writing a 1 t this bit. This bit always reads as a 0. TIRUN This bit cntrls Timer I. A 1 allws Timer I t run. A 0 stps and clears Timer I. This bit, alng with the SLAVEN, MASTRQ and MASTER bits sets the TWI peratinal mde. CT1, CT0 These tw bits set the Timer I prelad value at every SCL transitin. This allws the user t ptimize the TWI bus timing fr a given scillatr speed. These bits are cleared by reset CT1, CT0 Values CT1,CT0 OSC/12 Max Osc Timeut Perid Cunt Frequency cycles cycles cycles cycles TWI Operating Mdes with TIRUN The cntrl f Timer I is a functin f the current perating mde f the TWI hardware. When n mde is selected, TIRUN is an enable that allws Timer I t be a free-running timer If any mde is selected, then the bttm three bits f Timer I always run, s as t prvide timing infrmatin fr prper TWI peratin. The TIRUN bit then enables the peratin f the upper Timer I bits which check fr the TWI timeut cnditins. SLAVEN MASTRQ MASTER TWI Operating Mdes TIRUN Mde All 0 0 Off All 0 1 TI is free-running timer Any 1 0 TWI is n, but upper bits f TI d nt run. Any 1 1 Nrmal TWI peratin I2STA ñ TWI Status Register Address Reset value = F8h = x I2STA - TWI Status Register Bit Name Functin 7 x Nt used 6 IDLE TWI is in idle mde 5 XDATA Transmit buffer 4 XACTV Transmitter is active 3 MAKSTR TWI is making a start bit 2 MAKSTP TWI is making a stp bit 1 XSTR TWI is making multiple start bits 0 XSTP TWI is making multiple stp bits This is a read-nly register. IDLE The idle bit indicated the status f the TWI hardware. This bit is a mirrr f the bit in the I2CON register. XDATA The cntent f the transmit buffer. XACTV This bit indicates that the transmitter is active /19/07

9 Tekms TK87C751 Micrcntrller MAKSTR This bit indicates that the TWI hardware is generating a start bit. MAKSTP This bit indicates that the TWI hardware is generating a stp bit. XSTR This bit indicates that the TWI hardware is generating repeated start bits. This bit is a mirrr f the bit in the I2CON register. XSTP This bit indicates that the TWI hardware is generating repeated stp bits. This bit is a mirrr f the bit in the I2CON register. Interrupts The TK87C751 has five interrupt channels. These channels may be individually r cllectively enabled. Unlike the classic 8051, there is nly ne pririty level. The interrupt channels are dedicated t specific functins within the TK87C751 and are cntrlled by bits in the cntrl registers. An interrupt may be generated by sftware by setting the apprpriate cntrl bits. IE ñ Interrupt Enable Register Address = ABh Reset value = IE ñ Interrupt Enable Register Bit Name Functin 7 EA Enable All 6 x 5 x 4 EI2 Enable TWI 3 ET1 Enable Timer I 2 EX1 Enable INT1 1 ET0 Enable Timer 0 0 EX0 Enable INT0 External Interrupts The TK87C751 has tw external interrupts, which are called /INT0 and /INT1. The IT0 and IT1 bits in the TCON register determine if these interrupts are level triggered (ITn=0) r falling edge triggered (ITn=1). The interrupt bit will be reset by the interrupt hardware if it was an edge triggered interrupt. It is the prgrammer's respnsibility t insure that the external event that generates a level triggered interrupt is satisfied and that the input is remved befre the end f the interrupt service rutine. Timer 0, I Interrupts Overflws in Timer 0 sets the TF bit in the TCON register. Overflws in Timer I set the unreadable TI bit in the I2CFG register They in turn generate the interrupt. As with the external interrupts, the interrupt hardware will reset the interrupt bit during the interrupt rutine. TWI Interrupts A TWI interrupt will be generated if the ATN bit in the I2CON register has been set. It is the prgrammerís respnsibility t determine which f the 4 cnditins(start, stp, data ready, r lss f arbitratin) actually generated the interrupt. Interrupt Pririties Interrupt pririty register was remved frm the TK87C751. As a result, the interrupt pririties are fixed. Interrupt Vectr Lcatins The interrupt service rutine starts at the fllwing memry lcatins. Interrupt Vectr Lcatins Address Pririty Surce 0003h 1 IE0 000Bh 2 TF 0013h 3 IE1 001Bh 4 TI 0023H 5 TWI Interrupt Respnse An interrupt begins with the setting f the apprpriate bit in a cntrl register. The interrupt hardware cmpares the bit with the enables and pririties t determine if an interrupt request is warranted and which interrupt shuld be requested. This lgic prvides either a request fr a pririty 1 r a pririty 0 interrupt. This lgic als prepares a vectr address fr the interrupt service rutine /19/07

10 Tekms TK87C751 Micrcntrller If the prcessr is at the end f an instructin, and if the current instructin is nt a RETI, and the current instructin des nt invlve a write t either the IP r IE registers, and the prcessr is nt currently servicing an interrupt f equal r higher pririty, then the interrupt request will be granted, and the prcessr will execute the interrupt service rutine. Under nrmal peratin, the prgram cunter is incremented immediately after an pcde fetch. This actin is inhibited by the interrupt, and the prgram cunter is frzen at the current value. The interrupt service rutine then pushes the prgram cunter nt the stack, sets an internal interrupt status bit, clears the upper byte f the prgram cunter, and lads the lwer byte with the interrupt vectr. Overall, the interrupt service rutine behaves as a subrutine call. Interrupt Return The RETI instructin shuld be used fr a return frm a subrutine. This instructin is the same as a RET instructin, except that it clears the internal interrupt status bit, and thus enables future interrupts. Pwer Management The TK87C751 prvides fr the tw standard pwer management mdes and fr the POR status bit. PCON ñ Pwer Cntrl Register Address Reset value = 87h = b Pwer Cntrl (PCON) Bit Name Functin 7 x Nt used 6 x Nt used 5 x Nt used 4 POF Pwer On Flag 3 GF1 User Flag 1 2 GF0 User Flag 0 1 PD Cntrl timer bit 1 0 IDL Cntrl timer bit 0 Idle Mde The idle mde is entered by setting the IDLE bit in the PCON register. In the idle mde, the internal clck t the prcessr is stpped. The peripherals and the interrupt lgic cntinue t be clcked. The prcessr will leave idle when either an interrupt r a reset ccurs. Pwer Dwn Mde When the PD bit f the PCON register is set, the prcessr enters the pwer dwn mde. During this mde all f the clcks, including the scillatr are stpped. The nly way t exit pwer dwn mde is with a reset. GF0, GF1 Bits 2 and 3 f the PCON register are user definable, general purpse flags. POR Flag Bit 4 f the PCON register cntains a pwer-nflag. This bit is set when VDD has been applied t the part. If it is subsequently reset by sftware, it can be used t determine if a reset is a warm bt r a cld bt. Stpping the Clck The clck fr the TK87C751 may be stpped externally at any time and in any state. It may then be resumed at any time withut interference with the prcessr peratin. The nly cnsideratin is that the external clck stpping lgic shuld nt cause glitches n the clck input. Memry RAM The 87C751 cntains 128 bytes f RAM, lcated frm 00h t 7Fh in the SFR address space. ROM The 87C751 cntains bytes f Flash memry, lcated frm 0000h t FFFFh in the prgram address space /19/07

11 Tekms Prgramming and Verifying the Flash Memry Overview Tekms has replaced the OTP EPROM in the riginal 87C751 with a 64KB Flash memry. This allws much mre prgramming flexibility fr new designs while maintaining backwards cmpatibility fr existing designs. Hwever, since a Flash is nt an EPROM, the prgramming prcedures are different. This part is designed t be prgrammed in a dedicated prgrammer. ISP and IAP are nt supprted at this time. Tekms prvides a prgramming service, r it can be prgrammed thrugh thse third party prgrammers which supprt it. The Flash memry uses the chip 5 vlt supply fr all prgramming vltages. High prgramming vltages are nt required, and shuld never be applied t the chip. Flash Mde The TK87C751 is put int the prgramming mde in the same manner as the riginal chip. On the falling edge f reset, a 10 bit wrd, (296h) LSB first, is shifted int the reset pin, using X1 as the clck. The part then enters the Flash Mde, and the part pins are redefined as fllws: Addressing Flash Mde Pin Assignments Pin Functin Prt 1 Data Bus Prt 3 Address Bus P0.0 Address Strbe P0.1 WEn (0 = Write) P0.2 OE (1 = Read) X1 Clck The flash requires a full 19 bit address, thugh nly the lwer 16 address bits are used in the applicatin. The 87C751 has tw internal address latches that are used t hld the upper address bits. TK87C751 Micrcntrller When P0.0 (address strbe) ges high, then the data n P3 is clcked with the falling edge f XTAL1 int the lwer address latch (A8-A15), and the cntents f the lwer address latch are clcked int the upper address latch (A16-A23). T setup an address, first clck in A16-A23, then clck in A8-A15. The P3 pins becme A0-A7. Reading the Flash With OE high, the cntents f the Flash appear n prt 1. Nte that the lwer address can be changed withut affecting the upper address lines. This allws the read f 256 addresses withut having t write t the upper address lines. Flash Busy When A23 is a 1, bit D0 is changed t be a flash busy signal. This allws the mnitring f the flash status during the chip erase cmmand. Flash Write Operatins Writing t the flash cnsists f lading the desired address, bringing the P0.2 pin (OE) lw, putting the desired data n prt 1, and pulsing the P0.1 pin (WEn) lw. The flash memry cntains multiple interlcks t prevent accidental data writes. These take the frm f Flash cmmands. A cmmand is a sequence f 4 t 6 cnsecutive write peratins. Erasing the Flash The flash may be erased with the fllwing cmmands Flash Erase Cycle Address Data 1 000AAAh AAh h 55h 3 000AAAh 80h 4 000AAAh AAh h 55h 6 000AAAh 10h While the flash typically is dne erasing after 1 secnd, it may take up t 10 secnds. Tekms suggests mnitring the busy pin t determine when the erase cycle is cmplete /19/07

12 Tekms TK87C751 Micrcntrller Writing t the Flash Bytes may be written t the flash with a 4 cycle write as fllws: Flash Data Write Cycle Address Data 1 000AAAh AAh h 55h 3 000AAAh A0h 4 Address Data PDIP Package The TK87C751 is nt currently available in the 24.3 PDIP package. We expect t have samples in early The ROM versin f the part, the TK83C751 is available in that package. Burst Mde When prgramming large amunts f data, the Flash memry may be placed int a burst mde. This cnsists f a unlck cmmand, fllwed by multiple data writes, and terminated by a lck cmmand. The advantage f the burst mde is that it des nt require the prgramming f the upper address registers with each byte write. This reduces a byte write frm 12 clcks t tw. On every 256 byte bundary, it is necessary t rewrite the upper address bits t the crrect value. First, send the unlck cmmand Flash Unlck Cycle Address Data 1 000AAAh AAh h 55h 3 000AAAh 20h Then write each byte in a tw cycle sequence. This may be repeated as many times as necesary. Flash Burst Data Write Cycle Address Data 1 XXXXXXh A0h 2 Address Data Finish by sending the lck cmmand Flash Lck Cycle Address Data 1 XXXXXXh 90h 2 XXXXXXh F0h Encryptin Array and Security Bits At this time, the TK87C751 des nt supprt either the encryptin array r the tw security bits /19/07

13 Tekms TK87C751 Micrcntrller Electrical Specificatins Maximum Ratings Characteristics Symbl Min Max Unit Supply Vltage Vdd V Input Vltage Vin Vss ñ 0.3 Vdd V Current Drain per Pin Imax 15 ma Operating Temperature Range Cmmercial Industrial Tac Tai C C Strage Temperature range Tstg C DC Electrical Specificatins (Vdd = 5.0 V +/- 10%, Vss = 0 V, Ta = 0 C t +70 C) Characteristics Cnditin Symbl Min Max Unit Input high level (Prts 0, 1, 2, 3, /EA) V IH 2.0 Vdd V Input high level (X1, RST) V IH1 2.0 Vdd V Input lw level V IL V Output high level Ih = 2 ma V OH 2.4 Vdd V Output high level Ih = 4 ma V OH1 2.4 Vdd V Output lw level Il = 2 ma V OL V Output lw level Il = 4 ma V OL V Input current (Prts 1, 2, 3) V IN = 0.4 V I LI ua Lgical 1 t 0 transitin current (Prts 1, 2, 3) Nte 2 I TL ua Input Leakage current (Prt 0) I L ua Supply current, Active mde, X1 = 12 MHz I CCA 20 ma Internal Reset Pull-Dwn Resistr Vin = 0V R RST ua Pin Capacitance Ci C IO 10 ua Pwer dwn current Nte 3 I PD TBD ua Idle Mde Current Nte 4 I IDLE TBD ma Supply Current Nte 5 I DD TBD ma Ntes Fr DC Characteristics: 1. The utput lw current (Il) must be externally limited as fllws: Maximum Il per pin 10 ma Maximum Il per 8-bit prt 26 ma Maximum ttal Il 67 ma Exceeding these limits will cause current induced vltage drps in internal grund busses. This in turn will cause Vl t rise, and pssible exceed the specificatins. 2. Prts 1 and 3 surce a transitin current when a pin is pulled frm a 1 t a 0. This current reaches a peak value arund 2 vlts. 3. The pwer dwn current is measured with prt 0 = Vdd, prts 1 and 3 discnnected, RST = 0v, and X1 and X2 discnnected. 4. The idle mde current is measured with prt 0 = Vdd, prts 1 and 3 discnnected, RST = 0v, X2 discnnected, and X1 driven by a 12 MHz clck with 5 ns rise and fall times. 5. The supply current is measured with prt 0 = Vdd, prts 1 and 3 discnnected, RST = 0v, X2 discnnected, and X1 driven by a 12 MHz clck with 5 ns rise and fall times /19/07

14 Tekms TK87C751 Micrcntrller AC Electrical Specificatins (Vdd = 5.0 V +/- 10%, Vss = 0 V, Ta = 0 C t +70 C) Characteristics Symbl Min Max Unit Oscillatr Frequency 1/T CLCL MHz External Clck High Time T CH 20 ns External Clck Lw Time T CL 20 ns External Clck Rise Time T CR 20 ns External Clck Fall Time T CF 20 ns Ordering Infrmatin Cde Temperature Package Frequency Replaces TK87C751-1A28 0 t +70 Plastic 28 PLCC ñ RHS 3.5 t 12 MHz S87C751-1A28 TK87C751-2A28-40 t +85 Plastic 28 PLCC ñ RHS 3.5 t 12 MHz S87C751-2A28 TK87C751-4A28 0 t +70 Plastic 28 PLCC ñ RHS 3.5 t 16 MHz S87C751-4A28 TK87C751-5A28-40 t +85 Plastic 28 PLCC ñ RHS 3.5 t 16 MHz S87C751-5A28 Cntact Infrmatin The TK87C751 series may be rdered directly frm Tekms Tekms, Inc Cmmercial Center Drive Suite 400 Austin, TX phne fax Sales@Tekms.Cm Revisin Histry Date Revisin Descriptin 7/19/ Initial release 2007 Tekms, Inc. Infrmatin cntained in this publicatin regarding device applicatins and the like is intended fr suggestin nly and may be superseded by updates. N representatin r warranty is given and n liability is assumed by Tekms Incrprated with respect t the accuracy r use f such infrmatin, r infringement f patents r ther intellectual prperty rights arising frm such use r therwise. Use f Tekmsí prducts as critical cmpnents in life supprt systems is nt authrized except with express written apprval by Tekms. N licenses are cnveyed, implicitly r therwise, under any intellectual prperty rights. The Tekms lg and name are registered trademarks f Tekms, Inc. All rights reserved. All ther trademarks mentined herein are the prperty f their respective cmpanies. All rights reserved. Terms and prduct names in this dcument may be trademarks f thers /19/07