Interfacing the DP8420A 21A 22A to the AN-538

Transcription

1 Intrfacing th DP8420A 21A 22A to th INTRODUCTION This application not xplains intrfacing th DP8420A 21A 22A DRAM controllr to th Thr diffrnt dsigns ar shown and xplaind It is assumd that th radr is familiar with th accss cycls and th DP8420A 21A 22A mods of opration This application not also applis to th DESIGN 1 DESCRIPTION Dsign 1 is a simpl circuit to intrfac th to th DP8420A 21A 22A and up to 32 Mbyts of DRAM Th DP8420A 21A 22A is opratd in Mod 1 An accss cycl bgins whn th placs a valid addrss on th addrss bus and assrts th addrss strob (AS) Chip slct (CS) is gnratd by a 74AS138 dcodr If a rfrsh or Port B accss (DP8422A only) is not in progrss th DP8420A 21A 22A will assrt th propr RAS dpnding on th bank slct inputs (B0 B1) Aftr guaranting th programmd valu of row addrss hold tim th DP8420A 21A 22A will switch th DRAM addrss (Q ) to th column addrss and assrt CAS By this tim th 74AS245 s hav bn nabld and th DRAMs plac thir data on th data bus Th DP8420A 21A 22A also assrts DTACK which is usd to gnrat DTACK to th to complt th accss If a rfrsh or Port B accss had bn in progrss th DP8420A 21A 22A would hav dlayd th s accss by insrting wait stats into th accss cycl until th rfrsh or Port B accss was complt and th programmd amount of prcharg tim was mt This circuit can run up to 10 MHz with 0 wait stats with two or mor banks For 10 MHz zro wait stats with on bank s dsign 2 Timing paramtrs ar rfrncd to th numbrs shown in th DP8420A 21A 22A data sht timing paramtrs Numbrd tims starting with a $ rfr to th DP8420A 21A 22A timing paramtrs Numbrd tims starting with rfr to th data sht Equations hav bn givn to allow th usr to calculat timing basd on his frquncy and application Th clock is at 10 MHz a multipl of 2 MHz allowing it to b tid dirctly to DELCLK If DELCLK is not a multipl of 2 MHz ADS to CAS must b rcalculatd DESIGN 1 TIMING AT 10 MHz AND 8 MHz Clock Priod Tcp ns 10 MHz Tcp8 125 ns 8ns $400b ADS Assrtd Stup to CLK High Clock Priod b CLK High to AS Assrtd Tcp10 b ns b 55 ns 45 ns 10 MHz Tcp8 b ns b 60 ns 65 ns 8 MHz National Smiconductor Application Not 538 Jo Tat and Rusty Mir May 1989 $401 CS Stup to ADS Assrtd Addrss to AS Max b 74AS138 Dcodr 11 b Tphl Max 20 ns b 9ns 11 ns 10 MHz 11 b Tphl 30 ns b 9ns 21 ns 8 MHz $407 $404 Addrss Valid Stup to ADS Assrtd Addrss to AS Max 11 Max 20 ns 10 MHz 11 Max 30 ns 8 MHz $ ADS Ngatd Hld from CLK High CLK High to AS Assrtd Min 10 Min 0ns 10 MHz 10 Min 0ns 8 MHz DTACK Stup Tim Clock Priod b Clock to DTACK Assrtd Tcp10 b $18 50 ns b 28 ns 22 ns 10 MHz Using Tcp8 b $ ns b 33 ns 29 5 ns 8 MHz Using RAS LOW DURING REFRESH tras Programmd Clock b (CLK High to Rfrsh RAS Assrtd) b (CLK High to Rfrsh RAS Ngatd) Tcp10 a Tcp10 b $ ns a 100 ns b 6ns 194 ns 10 MHz Tcp8 a Tcp8 b $ ns a 125 ns b 6ns 244 ns 8 MHz Intrfacing th DP8420A 21A 22A to th AN-538 C1995 National Smiconductor Corporation TL F 9732 RRD-B30M115 Printd in U S A

2 RAS PRECHARGE PARAMETERS trp (Programmd Clocks b 1) b (AREQ to RAS Ngatd) b (CLK to RAS Assrtd) Tcp10 b $ ns b 16 ns 84 ns 10 MHz Tcp8 b $ ns b 16 ns 109 ns 8 MHz To gain mor prcharg program 3t or us dsign 2 trac AND tcac FOR DRAMs Timing is supplid for th systm shown in Figur 1 (s Figurs 2 3 and 4) Sinc systms and DRAM tims vary th usr is ncouragd to chang th following quations to match his systm rquirmnts Timing has bn supplid for systms with 0 or 1 wait stat If DELCLK is not a multipl of 2 MHz th timing for trah and tasc will incras or dcras according to th quations givn in th data sht Th ADS to RAS and ADS to CAS will also hav to b changd dpnding on th capacitanc of th DRAM array 0 Wait Stats trac s2 a s3 a s4 a s5 a s6 b CLK to AS Assrtd Max b ADS Assrtd to RAS Assrtd b 74AS245 Dlay Max b Data Stup Min 2 Tcp10 b 9 b $402 b Tphl Max b ns b 55 ns b 35 ns b 7ns b10 ns Using ns 10 MHz w Havy Load 2 Tcp8 b 9 b $402 b Tphl Max b ns b 60 ns b 35 ns b 7nsb15 ns Using ns 8 MHz w Havy Load 1 Wait Stat trac s2 a s3 a s4 a sw a sw a s5 a s6 b CLK to AS Assrtd Max b ADS Assrtd to RAS Assrtd b 74AS245 Dlay Max b Data Stup Min 3 Tcp10 b 9 b $402 b Tphl Max b ns b 55 ns b 35 ns b 7ns b10 ns Using ns 10 MHz w Havy Load 3 Tcp8 b 9 b $402 b Tphl Max b ns b 60 ns b 35 ns b 7ns b15 ns Using ns 8 MHz w Havy Load 0 Wait Stats tcac s2 a s3 a s4 a s5 a s6 b CLK to AS Assrtd Max b ADS Assrtd to CAS Assrtd b 74AS245 Dlay Max b Data Stup Min 2 Tcp10 b 9 b $403a b Tphl Max b 27 1 Wait Stat tcac 250 ns b 55 ns b 94 ns b 7ns b10 ns Using ns 10 MHz w Havy Load 2 Tcp8 b 9 b $403a b Tphl Max b ns b 60 ns b 94 ns b 7ns b15 ns Using ns 8 MHz w Havy Load s2 a s3 a s4 a sw a sw a s6 b CLK to AS Assrtd Max b ADS Assrtd to CAS Assrtd b 74AS245 Dlay Max b Data Stup Min 3 Tcp10 b 9 b $403a b Tphl Max b ns b 55 ns b 94 ns b 7nsb10 ns Using ns 10 MHz w Havy Load 3 Tcp8 b 9 b $403a b Tphl Max b ns b 60 ns b 94 ns b 7nsb15 ns Using ns 8 MHz w Havy Load 2

3 Dsign 1 Programming Bits Bits Dscription Valu R0 R1 RAS Low Tim During REFRESH 2T R0 0 RAS Prcharg Tim 2T R1 1 R2 R3 DTACK Gnration Mods R2 s for Non-Burst Accsss R3 s R4 R5 DTACK Gnration Mods R4 s for Burst Accsss R5 s R6 Add Wait Stats with WAITIN R6 s R7 DTACK Mod Slct R7 1 R8 Non Intrlavd Mod R8 1 R9 Staggrd or All RAS REFRESH R9 u C0 C1 C2 Divisor for DELCLK C0 s C1 s C2 s C3 a30 REFRESH C3 0 C4 C5 C6 RAS CAS Configuration Mod C4 u Choos All CAS Mod C5 u C6 u C7 Slct 0 ns Column Addrss Stup C7 1 C8 Slct 15 ns Row Addrss Stup C8 1 C9 CAS is Dlayd to th Nxt Rising C9 1 CLK Edg During Writs B0 Th Row Column Bank Latchs B0 1 Ar Fall Through Mod B1 Accss Mod 1 B1 1 ECAS0 CAS Not Extndd Byond RAS ECAS0 0 u usr dfind s systm dpndnt R2 1 R3 0 for 0 WAIT STATES R2 1 R3 0 R6 0 for 1 WAIT STATE C0 1 C1 0 C2 1 for 10 MHz C0 0 C1 0 C2 1 for 8 MHz R4 0 R5 0 for 0 WAIT STATES during writ portion of tst and st R4 1 R5 1 for 1 WAIT STATE during writ portion of tst and st 3

4 FIGURE Dsign 1 TL F

5 FIGURE Dsign 1 Timing TL F

6 FIGURE Dsign 1 Timing TL F

7 FIGURE Dsign 1 Timing TL F

8 DESIGN 2 DESCRIPTION Dsign 2 diffrs from Dsign 1 in that th can b run up to 12 5 MHz This dsign can also run with no wait stats at 10 MHz if only on bank of DRAM is bing usd A latch must b usd with th addrss strob to guarant th addrss stup to ADS assrtd rquirmnt of th DP8420A 21A 22A Again th DP8420A 21A 22A is opratd in Mod 1 An accss cycl bgins whn th placs a valid addrss on th addrss bus at th bginning of procssor stat s1 At procssor stat s2 th assrts th addrss strob AS This signal is qualifid with CLK low to st a latch Th output of this latch producs th signal ADS to th DP8420A 21A 22A Whn th signal ADS is assrtd on th DP8420A 21A 22A th chip will assrt RAS Aftr guaranting th row addrss hold tim th 8420A 21A 22A will plac th column addrss to th DRAM addrss bus Aftr guaranting th column addrss stup tim th DP8420A 21A 22A will assrt CAS Aftr tim tcac has passd th DRAM will plac its data on th data bus Th 8420A 21A 22A will assrt th DTACK output allowing th bus cycl to nd If a rfrsh of a Port B accss had bn in progrss th accss would hav bn dlayd by insrting wait stats in th Port A accss cycl DESIGN 2 TIMING AT 12 5 MHz Clock Priod Tcp12 80 ns 12 5 MHz $400b ADS Assrtd Stup to CLK High Clock Priod a Clock Priod a 74AS04 Dlay Min a 74AS04 Dlay Min b Clock to AS Assrtd Max b 74AS04 Dlay Min b 74AS02 Dlay Max b 74AS02 Dlay Max Tcp12 a Tcp12 a Tphl Min a Tphl Min b 9 b Tphl Min b Tphl Max b Tphl Max $ ns a 40 ns a 1nsa1nsb55 ns b 1nsb4 5 ns b 4 5 ns 57 ns 12 5 MHz CS Stup to ADS Assrtd Clock Priod a 74AS04 Dlay Min a 74AS04 Dlay Min a 74AS02 Dlay Min a 74AS02 Dlay Min b 74AS04 Dlay Min b Clock to ADR Max b 74AS138 Dlay Max Tcp12 a Tphl Min a Tphl Min a Tphl Min a Tphl Min b Tphl Min b 6 b Tphl Max 80 ns a 1nsa1nsa1nsa1ns b1nsb55 ns b 9ns 19 ns 12 5 MHz $407 $404 Addrss Valid to ADS Assrtd Clock Priod a 74AS04 Dlay Min a 74AS04 Dlay Min a 74AS02 Dlay Min a 74AS02 Dlay Min b Clock to ADR Max b 74AS04 Min Tcp12 a Tphl a Tphl a Tphl a Tphl b 6 b Tphl 80 ns a 1nsa1nsa1nsa1ns b55 ns b 1ns 28 ns 12 5 MHz $ ADS Ngatd Hld from CLK High Min 74AS04 a Min 74AS02 a Min 74AS02 a Min 74AS04 b Min 74AS04 Tphl a Tphl a Tphl a Tphl b Tphl 1nsa1nsa1nsa1nsb1ns 3ns 12 5 MHz DTACK Stup Tim 1 Clock Priod b CLOCK skw (74AS04) b Max Clock to DTACK Tcp12 b Tphl Max b $18 80 ns b 5nsb28 ns 47 ns 12 5 MHz RAS LOW DURING REFRESH tras Programmd Clock b (CLK High to Rfrsh RAS Assrtd) b (CLK High to Rfrsh RAS Ngatd) Tcp12 a Tcp12 b $55 80 ns a 80 ns b 6ns 154 ns 12 5 MHz RAS PRECHARGE PARAMETERS trp Programmd Clocks b Clock to AS Ngatd b (AREQ to RAS Ngatd) b (CLK to RAS Assrtd) $29b Tcp12 a Tcp12 b $50 80 ns a 80 ns b 16 ns 144 ns 12 5 MHz AREQ Ngatd Stup to CLK Clock Priod a Min CLOCK Skw 74AS04 b Max 74AS02 b Max 74AS02 Tcp12 a Tphl a Tphl b Tphl 80 ns a 1nsb4 5 ns b 4 5 ns 72 ns 12 5 MHz 8

9 trac AND tcac FOR DRAMs Timing is supplid for th systm shown in Figur 5 (S Figurs 6 ) Sinc systms and DRAM tims vary th usr is ncouragd to chang th following quations to match his systm Timing has bn suppild for systms with 0 wait stats and 1 bank of DRAM and 1 wait stat and 4 banks of DRAM If DELCLK is not a multipl of 2 MHz th tims of trah and tasc will incras or dcras according to th quations givn in th data sht Th ADS to RAS and ADS to CAS will also hav to b changd dpnding on th capacitanc of th DRAM array trac 0 wait stats dos not us transcivrs trac s2 a s3 a s4 a s5 a s6 b 74AS02 Max b 74AS02 Max b Clock to AS Max b ADS to RAS b Data Stup 2 Tcp12 b Tphl b Tphl b 9 b $402 b b 4 5 ns b 4 5 ns b 55 ns b 25 ns b 10 ns Using ns 12 5 MHz w Light Load 1 wait stat uss transcivrs trac s2 a s3 a s4 a sw a sw a s5 a s6 b 74AS02 Max b 7AS02 Max b Clock to AS Max b ADS to RAS b 74AS245 Dlay b Data Stup 3 Tcp12 b Tphl b Tphl b 9 b $402 b Tphl b ns b 4 5 ns b 4 5 ns b 55 ns b 29 ns b 7nsb10 ns 170 ns 12 5 MHz tcac 0 wait stats dos not us transcivrs tcac s2 a s3 a s4 a s5 a s6 b 74AS02 Max b 74AS02 Max b Clock to AS Max b ADS Assrtd to CAS b Data Stup 2 Tcp12 b Tphl b Tphl b 9 b $403a b ns b 4 5 ns b 4 5 ns b 55 ns b 75 ns b 10 ns Using ns 12 5 MHz w Light Load 1 wait stat uss transcivrs tcac s2 a s3 a s4 a sw a sw a s5 a s6 b 74AS02 Max Dlay b 74AS02 Max Dlay b Clock to AS Max b ADS Assrtd to CAS b 74AS245 Data Stup 3 Tcp12 b Tphl b Tphl b 9 b $403a b Tphl b ns b 4 5 ns b 4 5 ns b 55 ns b 75 ns b 7nsb10 ns 124 ns 12 5 MHz DESIGN 2 0 WAIT STATES DURING WRITE ACCESS Dsign 2 can b modifid to allow 0 wait stats during writs To accomplish this th chip must b programmd with th sam valu xcpt that bits R2 R3 and R6 ar changd to R2 0 DTACK of 0T from RAS R3 0 R6 0 Hold off DTACK 1 xtra clock priod Th hardwar must b modifd Th signal R W from th is invrtd and tid to th 8420 signal WAITIN This nsurs that a wait stat will only b assrtd during rad accsss (s Figur 6 ) 0 waits during writ accss timing RAS Low Tim trp Max AS Low b Clock Priod b 74AS02 Dlay b 74AS02 Dlay a 74AS02 Dlay a 74AS02 Dlay b (ADS Assrtd to RAS) b (AREQ Ngatd to RAS Ngatd) 14 b Tcp12 b Tphl b Tphl a Tphl a Tphl b $ ns b 40 ns b 0ns 120 ns 12 5 MHz CAS Low Tim tcp s2 a s3 a s4 a s5 a s6 b Max CLK to AS b 74AS02 b 74AS02 b Max AS to CAS a Min CLK to DS a Min ECAS to CAS 2 Tcp12 b 9 b Tphl b Tphl b $403a a 12 a $ ns b 55 ns b 4 5 ns b 4 5 ns b 82 ns a 0nsa0ns 54 ns 12 5 MHz 9

10 Dsign 2 Programming Bits Bits Dscription Valu R0 R1 RAS Low Tim 2T R0 0 RAS Prcharg Tim 2T R1 1 R2 R3 DTACK Gnration Mods R2 0 for Non-Burst Accsss R3 1 R4 R5 DTACK Gnration Mods R4 0 for Burst Accsss R5 1 R6 Add Wait Stats with WAITIN R6 0 R7 DTACK Mod Slct R7 1 R8 Non Intrlavd Mod R8 1 R9 Staggrd or All RAS REFRESH R9 u C0 C1 C2 Divisor for DELCLK C0 u C1 u C2 u C3 a30 REFRESH C3 0 C4 C5 C6 RAS CAS Configuration Mod C4 u Choos All CAS Mod C5 u C6 u C7 Slct 15 ns Column Addrss Stup C7 1 C8 Slct 15 ns Row Addrss Stup C8 1 C9 CAS is Dlayd to th Nxt Rising C9 1 CLK Edg During Writs B0 Th Row Column Bank Latchs B0 1 Ar Fall Through Mod B1 Accss Mod 1 B1 1 ECAS0 CAS Not Extndd Byond RAS ECAS0 0 u usr dfind s prvious pag for 0 WAIT STATES during writs 10

11 FIGURE Dsign 2 up to 12 5 MHz TL F

12 FIGURE 6 Dsign 2 Timing with Zro Wait Stats during Writs TL F

13 DESIGN 3 DESCRIPTION Dsign 3 is a simpl circuit to intrfac th running 16 MHz to th DP8420A 21A 22A and up to 32 Mbyts of DRAM Th DP8420A 21A 22A is opratd in Mod 1 An accss cycl bgins whn th placs a valid addrss on th addrss bus and assrts AS AS is thn clockd with a 74AS74 flip-flop Th output of th flip-flop is usd to produc ADS to th DP8420A 21A 22A Chip Slct (CS) is gnratd by a 74AS138 dcodr If a rfrsh or Port B accss had bn in progrss th 8420A 21A 22A would hold off th accss by insrting wait stats in th accss cycl Th DP8420A 21A 22A will plac th row addrss on th DRAM s addrss bus and assrt RAS Aftr guaranting th row addrss hold tim trah th DP8420A 21A 22A will plac th column addrss on th DRAM s addrss bus and assrt CAS DESIGN 3 TIMING AT MHz Clock Priod Tcp16 60 ns MHz $400b ADS Assrtd Stup to CLK High Clock Priod b 74AS74 Dlay Max Tcp16 b Tphl 60 ns b 9ns 51 ns MHz $401 CS Assrtd Stup to ADS Assrtd 1 Clock Priods a Min 74AS74 Dlay b Max Clock to Addrss b 74AS138 Dlay 1 Tcp16 a Tphl b 6 b Tphl 90 ns a 4 5 ns a 50 ns b 9ns 35 5 ns MHz $407 $404 Addrss Valid Stup to ADS Assrtd 1 Clock Priods a Min 74AS74 Dlay b Max Clock to Addrss 1 Tcp16 a Tphl b 6 $ ns a 4 5 ns b 50 ns 44 5 ns MHz ADS Ngatd Hld from CLK High Min 74AS74 Dlay 4 5 ns MHz trp (Programmd Clocks b 1) b (AREQ to RAS Ngatd) b (CLK to RAS Assrtd) Tcp16 a Tcp16 b $ ns b 16 ns 104 ns MHz RAS PRECHARGE PARAMETERS trp Programmd Clocks b Clock to AS Ngatd b (AREQ to RAS Ngatd) b (CLK to RAS Assrtd) trac AND tcac FOR DRAMs Timing is supplid for th systm shown in Figur 7 Sinc systm and DRAM tims vary th usr is ncouragd to chang th following quations to match his systm rquirmnts Timing has bn supplid for systms with 2 wait stats If DELCLK is not a multipl of 2 MHz th timing for trah and tasc will incras or dcras according to th tims givn in th data sht Th ADS to RAS and ADS to CAS will also hav to b changd dpnding on th capacitanc of th DRAM array 1 wait stat using 1 BANK with no transcivrs trac s4 a sw a sw a s5 a s6 b 74AS74 Dlay b ADS to RAS b Data Stup 2 Tcp16 b Tphl b $402 b ns b 9nsb25 ns b 10 ns Using ns MHz w Light Load 2 wait stats uss 4 banks with trancivrs trac s4 a sw a sw a sw a sw a s5 a s6 b 74AS74 Dlay b ADS to RAS b Data Stup b Transcivrs 3 Tcp16 b Tphl b $402 b 27 b Tphl 210 ns b 9nsb29 ns b 10 ns b 7ns 155 ns MHz 47 DTACK Stup Tim Clock Priod b 74AS74 Dlay Max Tcp16 b Tphl 60 ns b 9ns 51 ns MHz RAS LOW DURING REFRESH tras Programmd Clocks b (CLK High to Rfrsh RAS Assrtd) b (CLK High to Rfrsh RAS Ngatd) Tcp16 a Tcp16 a Tcp16 a Tcp16 b $ ns b 6ns 234 ns MHz 13

14 1 wait stat using 1 BANK with no transcivrs tcac s4 a sw a sw a s5 a s6 b 74AS74 Dlay b ADS to CAS b Data Stup 2 Tcp16 b Tphl b $403a b ns b 9nsb75 ns b 10 ns 56 ns 16 MHz 2 wait stats using 4 banks with transcivrs tcac s4 a sw a sw a sw a sw a s5 a s6 b 74AS74 Dlay b ADS to CAS b Data Stup b Transcivr 3 Tcp16 b Tphl b $403a b 27 b Tphl 210 ns b 9nsb82 ns b 10 ns b 7ns 102 ns 16 MHz Dsign 3 Programming Bits Bits Dscription Valu R0 R1 RAS Low Tim 2T R0 0 RAS Prcharg Tim 2T R1 1 R2 R3 DTACK Gnration Mods R2 1 for Non-Burst Accsss R3 0 R4 R5 DTACK Gnration Mods R4 u for Burst Accsss R5 u R6 Add Wait Stats with WAITIN R6 u R7 DTACK Mod Slct R7 1 R8 Non Intrlavd Mod R8 1 R9 Staggrd or All RAS REFRESH R9 u C0 C1 C2 Divisor for DELCLK C0 0 (a8 for 16 MHz) C1 1 C2 0 C3 a30 REFRESH C3 0 C4 C5 C6 RAS CAS Configuration Mod C4 u Choos All CAS Mod C5 u C6 u C7 Slct 15 ns Column Addrss Stup C7 1 C8 Slct 15 ns Row Addrss Stup C8 1 C9 CAS is Dlayd to th Nxt Rising C9 1 CLK Edg During Writs B0 Th Row Column Bank Latchs B0 1 Ar Fall Through Mod B1 Accss Mod 1 B1 1 ECAS0 CAS Not Extndd Byond RAS ECAS0 0 u usr dfind s prvious pag for 0 WAIT STATES during writs 14

15 FIGURE Dsign 3 Works up to 16 MHz TL F Additional Circuitry for Dsign 1 Using th DMA Controllr TL F

16 AN-538 Intrfacing th DP8420A 21A 22A to th Bcaus th sampls DTACK on a positiv dg of CLK and th sampls DTACK on th ngativ dg additional circuitry must b addd to produc th two DTACK signals Th DTACKs must b producd diffrnt to nsur RAS low tim aftr an accss dlayd by a rfrsh Th programming bits must also b changd as follows For 0 WAITSTATES R2 4 0 R3 4 1 FOR DTACK OF 1 2 For 1 WAITSTATE R2 4 0 R3 4 1 R6 4 0 FOR DTACK OF Ti th DP8420 signal WAITIN low for 1 waitstat and high for 0 waitstats All timing xcpt for th following should still apply Tims with a rfr to th data sht Tims with a rfr to th data sht and tims with a $ rfr to th DP8420A 21A 22A data sht LIFE SUPPORT POLICY $47 DTACK Stup Tim CLOCK Priod b 74AS74 CLOCK to Q b 74AS32 Tcp10 b Tphl b Tphl 50 ns b 9nsb6ns 35 ns 10 MHz Tcp8 b Tphl b Tphl 62 5 ns b 9nsb6ns 47 ns 8 MHz 6 DTACK Stup Tim (68450) CLOCK Priod b CLOCK to DTACK Tcp10 b $18 50 ns b 28 ns 22 ns 10 MHz Tcp8 b $ ns b 33 ns 29 ns 8 MHz All othr tims ar th sam as th DRAM Spd Vrsus Procssor Spd (DRAM Spd Rfrncs th RAS Accss Tim trac of th DRAM Using DP8422A-25 Timing Spcifications) TL F Lit NATIONAL S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As usd hrin 1 Lif support dvics or systms ar dvics or 2 A critical componnt is any componnt of a lif systms which (a) ar intndd for surgical implant support dvic or systm whos failur to prform can into th body or (b) support or sustain lif and whos b rasonably xpctd to caus th failur of th lif failur to prform whn proprly usd in accordanc support dvic or systm or to affct its safty or with instructions for us providd in th labling can ffctivnss b rasonably xpctd to rsult in a significant injury to th usr National Smiconductor National Smiconductor National Smiconductor National Smiconductor Corporation Europ Hong Kong Ltd Japan Ltd 1111 Wst Bardin Road Fax (a49) th Floor Straight Block Tl Arlington TX cnjwg tvm2 nsc com Ocan Cntr 5 Canton Rd Fax Tl 1(800) Dutsch Tl (a49) Tsimshatsui Kowloon Fax 1(800) English Tl (a49) Hong Kong Fran ais Tl (a49) Tl (852) Italiano Tl (a49) Fax (852) National dos not assum any rsponsibility for us of any circuitry dscribd no circuit patnt licnss ar implid and National rsrvs th right at any tim without notic to chang said circuitry and spcifications