Design Methodologies and Tools

Transcription

1 Dsign Mthodologis and Tools Dsign styls Full-custom dsign Standard-cll dsign Programmabl logic Gat arrays and fild-programmabl gat arrays (FPGAs) Sa of gats Systm-on-a-chip (mbddd cors) Dsign tools 1 Full-Custom Dsign Evry gat is carfully dsignd and optimizd Hirarchical dsign may b usd, plac-and-rout tools typically usd Advantags: High dnsity, idal for high volums Prformanc optimization Disadvantags: High dsign tim, cumbrsom Applications: Datapaths in microprocssors High-paying jobs! 2

2 Full-Custom Dsign (Contd.) Simpl CAD tools suffic Dsign ntry Schmatic ditor Layout ditor DRC, LVS, Spic No nd for sophisticatd synthsis and dsign partitioning tools 3 Standard Cll Dsign Us pr-optimizd SSI or MSI library clls NAND gats, multiplxrs, addr slics, dcodrs, comparators, RAM, ROM Rducs dsign tim Lowr dnsity and lowr prformanc Standardizd at th logic or function lvl Pitch-matchd clls Routing channl 4

3 Standard Clls (Contd) CAD tools ndd for partitioning dsign Tchnology mapping Dsign ntry, DRC, LVS, simulations tools ndd Plac and rout tools Good for modrat volums, as in ASICs, typically usd for non-critical portions of a CPU 5 Programmabl Logic Programmabl logic blocks PLDs, PALs Fusibl links (fuss) blown whn currnt is xcdd Programmabl intrconncts Mask-programmd gat-arrays (MPGAs) Fild-programmabl gat-arrays (FPGAs) Sa of gats 6

4 PLDs Programmabl Logic Wid fan-in, 2-lvl SOP, optional flip-flops on output Bst known: 22V10 with 22 inputs, 10 outputs, from AMD Programmd by usrs Fusibl links MPGAs Also calld gat arrays Mor dns than PLDs Prdsignd transistors with customizd wiring Wiring don during manufactur (not usr) FPGAs: complx dsigns, usr programmabl 7 MPGAs vs FPGAs Numbr of dsigns 25K 20K 15K 10K 5K No. of gats 25, FPGA Standard cll MPGA PLD Prfrrd implmntation options Volum 8

5 FPGAs FPGAs Xilinx Altra Lucnt Actl Antifus programmd channl SRAMprogrammd EPROMprogrammd array Xilinx Altra (similar to PALs) Analog FPGAs (FPAAs) now commrcially availabl 9 FPGAs Advantags Low dsign cost (custom masks not ndd) Rapid turnaround Low risk Effctiv dsign vrification Low tsting costs-tst program sam for all dsigns Disadvantags Programming circuitry: ara pnalty, tn tims largr for sam gat capacity as MPGA Spd: 2-3 tims slowr than MPGA Dsign mthodology: too asy to us, ncourags tryit-and-s-what-happns mthodology 10

6 Programmabl Intrconncts Program th routing PLICE: Programmabl Low-Impdanc Circuit Elmnt, antifus Normally high rsistanc (> 100MΩ) Antifus can b prmanntly changd to a lowrsistanc ( Ω) structur, i.. form links Low gat utilization E.g. 32-bit addr using Actl FPGAs: 160 logic moduls, 65 ns for addition bit addrs on an FPGA chip 11 Commnts on Gat Utilization for FPGAs 32-bit addr using Actl FPGAs: 160 logic moduls, 65 ns for addition bit addrs on an FPGA chip Dsign tim: on aftrnoon, $5-$10 dsign cost Lot of wastd logic 32-bit full-custom addr (1 micron) 1300 addrs on on chip, 33 ns addition tim Dsign tim: 6 months, $200,000 12

7 Actl Logic Cll A 0 B 1 0 SA Y C D SB S0 S All 2-input functions ar ralizd (slct inputs carfully) All 3-input functions ar ralizd (if?) Which 4-input functions? How to implmnt a latch? 13 Xilinx FPGAs Configurabl logic blocks (contain SRAMs), CLBs Programmabl intrconnct 500 CLBs on a chip 100K bits of RAM pr chip 32-bit addr xampl: 62 CLBs, 8 addrs pr chip Spd: MHz 14

8 Sa of Gats Dsign Goal: rduc dsign cost of IC, rapid prototyping, fast turnaround tim Not usful for high-volum production (mor ara pr IC) Cor of chip (bas array) contains continuous array of n and p transistors Polysilicon laid a-priori (transistors formd in advanc) Prsonalization don by using dsign-spcific mtallization and contacts Highly automatd procss: sophisticatd CAD tools usd 15 Sa of Gats Routing possibl ovr unusd rows 16

9 Sa of Gats Poly gats Dsign Dcisions How many n and p rows pr strip? Siz and ratio of transistors Numbr, dirction of routing tracks V DD p-diff n-diff Gnd 17 Embddd Cors Complx off-th-shlf, optimizd, pr-dsignd circuits: procssors, ASICs, mmoris, controllrs Usd for systm-on-a-chip (SOC) dsigns Hot intllctual proprty (IP) IC consists of svral mbddd cors along with customdsignd blocks ASIC CPU DSP Custom logic Embddd DRAM Controllr 18

10 Synthsis tools Bhavioral synthsis Logic synthsis Dsign captur Dsign vrification Dsign Tools 19 Synthsis Tools Bhavior Rgistr-transfr (RT) lvl Logic lvl Layout Schmatic Spcify systm bhavior without implmntation dtails Allows fast simulation/vrification Tchnology-indpndnt Esp. succssful for signal procssing architcturs Silicon compilrs 20

11 Bhavioral Synthsis Bhavior (VHDL, Vrilog) Compilr (synthsis tool) Layout Rsourc constraints Parts library Tchnology paramtrs Dcid upon and assign rsourcs (schduling and binding) Insrt piplin rgistrs to mt timing constraints Crat microcod and control logic 21 Logic Synthsis Optimization Ntlist gnration Tchnology mapping Logic quation Extract Ntlist Input Input Tchnology-indpndnt: us Boolan and/or algbraic tchniqus Ntwork optimization, two-lvl and multi-lvl minimization Tchnology-mapping phas: cll binding 22

12 a f b f c g a b f c g Logic Optimization Exampl t1 f1 Extract common subxprssion f f1 a g b g d f a g b g d f2 f2 f1 = af + bf + cg f2 = ag + bg + df Litral count = 17 f1 = (a+b)t1 + cg f2 = ag + bg + dt1 Litral count = Dsign Captur Tools How to dscrib th bhavior/structur of a systm? HDLs: VHDL, Vrilog High-lvl languags (HLLs): C, Pascal, Lisp HDLs diffr from HLLs by catring for hardwar concpts: bit vctors, signals, timing Lik HLLs, HDLs provid structur, paramtrization, conditionals, looping, hirarchy Structur spcification: HDL, ntlist ditor Bhavior spcification: HDL, finit-stat machins, Ptri nts 24

13 Txtual ditor Easy to modify, mak changs Suitabl for mor complx dsigns Schmatic Entry Intractiv graphics ditor Exampl: Mntor DA Diagrams ar asily undrstood ( A pictur is worth a thousand words ) 25 Layout Editors Capturd via cod: (cll/layout gnrators), silicon compilation Intractiv graphics ditors (Mntor IC) Mans for turning off dtail or zooming Dsign rul chcking programs (DRC) Layout xtraction programs Dtrmin ntlist from layout 26

14 Back annotation Dsign Vrification Functional spcification RTL/logic Layout Ida = = Equivalnc chck Equivalnc chck Silicon Vrify th tool? 27 Dsign Vrification Simulation Gat-lvl Transistor, schmatic-lvl (Qsim) Circuit lvl (HSpic): high accuracy but high simulation tims, O(N m ), N transistors, 0<m<1 Formal vrification: Mathmatical modls 28