Section II. PCB Layout Guidelines

Transcription

1 Sction II. PCB Layout Guidlins This sction provids information for board layout dsignrs to succssfully layout thir boards for MAX II dvics. It contains th rquird printd circuit board (PCB) layout guidlins, dvic pin tabls, and packag spcifications. This sction includs th following chaptrs: Chaptr 7, Packag Information Chaptr 8, Using MAX II vics in Multi-Voltag Systms Rvision History Rfr to ach chaptr for its own spcific rvision history. For information about whn ach chaptr was updatd, rfr to th Chaptr Rvision ats sction, which appars in th complt handbook. Octobr 2008 Altra Corporation MAX II vic Handbook

2 II 2 Sction II: PCB Layout Guidlins Rvision History MAX II vic Handbook Octobr 2008 Altra Corporation

3 7. Packag Information MII Introduction This chaptr provids packag information for Altra s MAX II dvics, and includs ths sctions: Board coupling Guidlins on pag 7 1 vic and Packag Cross Rfrnc on pag 7 1 Thrmal Rsistanc on pag 7 2 Packag Outlins on pag 7 3 In this chaptr, packags ar listd in ordr of ascnding pin count. S Figur 7 1 through Board coupling Guidlins coupling rquirmnts ar basd on th amount of logic usd in th dvic and th output switching rquirmnts. As th numbr of I/O pins and th capacitiv load on th pins incras, mor dcoupling capacitanc is rquird. As many as possibl 0.1- mf powr-supply dcoupling capacitors should b connctd to th VCC and GN pins or th VCC and GN plans. Ths capacitors should b locatd as clos as possibl to th MAX II dvic. ach VCCINT/GNINT and VCCIO/GNIO pair should b dcoupld with a 0.1-mF capacitor. Whn using high-dnsity packags, such as ball-grid array (BGA) packags, it may not b possibl to us on dcoupling capacitor pr VCC/GN pair. In this cas, you should us as many dcoupling capacitors as possibl. For lss dns dsigns, a rduction in th numbr of capacitors may b accptabl. coupling capacitors should hav a good frquncy rspons, such as monolithic-cramic capacitors. vic and Packag Cross Rfrnc Tabl 7 1 shows which Altra MAX II dvics ar availabl in thin quad flat pack (TQFP), FinLin BGA (FBGA), and Micro Finlin BGA (MBGA) packags. Tabl 7 1. MAX II vics in TQFP, FinLin BGA, and Micro FinLin BGA Packags (Part 1 of 2) vic Packag Pin PM240Z MBGA (1) 68 PM240 PM240G FBGA (1) 100 PM240 PM240G PM240Z PM240 PM240G MBGA (1) 100 TQFP 100 Octobr 2008 Altra Corporation MAX II vic Handbook

4 7 2 Chaptr 7: Packag Information Thrmal Rsistanc Tabl 7 1. MAX II vics in TQFP, FinLin BGA, and Micro FinLin BGA Packags (Part 2 of 2) vic Packag Pin PM570 FBGA (1) 100 PM570G PM570 MBGA (1) 100 PM570G PM570Z PM570 TQFP 100 PM570G PM570Z MBGA (1) 144 PM570 TQFP 144 PM570G PM570 FBGA 256 PM570G PM570 MBGA (1) 256 PM570G PM570Z PM1270 TQFP 144 PM1270G FBGA 256 MBGA (1) 256 PM2210 FBGA 256 PM2210G FBGA 324 Not to Tabl 7 1: (1) Packags availabl in lad-fr vrsions only. Thrmal Rsistanc Tabl 7 2 provids θ JA (junction-to-ambint thrmal rsistanc) and θ JC (junction-tocas thrmal rsistanc) valus for Altra MAX II dvics. Tabl 7 2. Thrmal Rsistanc of MAX II vics (Part 1 of 2) vic Pin Count Packag θ JC ( C/W) θ JA ( C/W) Still Air θ JA ( C/W) 100 ft./min. θ JA ( C/W) 200 ft./min. θ JA ( C/W) 400 ft./min. PM240Z 68 MBGA PM240 PM240G 100 FBGA PM240 PM240G PM240Z PM240 PM240G PM570 PM570G 100 MBGA TQFP FBGA MAX II vic Handbook Octobr 2008 Altra Corporation

5 Chaptr 7: Packag Information 7 3 Packag Outlins Tabl 7 2. Thrmal Rsistanc of MAX II vics (Part 2 of 2) vic Pin Count Packag θ JC ( C/W) PM570 PM570G PM570Z PM570 PM570G Packag Outlins 100 MBGA TQFP PM570Z 144 MBGA PM TQFP PM570G PM570 PM570G PM570 PM570G PM570Z PM1270 PM1270G PM2210 PM2210G θ JA ( C/W) Still Air 256 FBGA MBGA TQFP FBGA MBGA FBGA FBGA Th packag outlins on th following pags ar listd in ordr of ascnding pin count. Altra packag outlins mt th rquirmnts of JC Publication No Pin Micro FinLin Ball-Grid Array (MBGA) Wir Bond All dimnsions and tolrancs conform to ASM Y14.5M 1994 Controlling dimnsion is in millimtrs θ JA ( C/W) 100 ft./min. θ JA ( C/W) 200 ft./min. θ JA ( C/W) 400 ft./min. Pin A1 may b indicatd by an I dot, or a spcial fatur, in its proximity on packag surfac Packag Information (Part 1 of 2) Packag Outlin imnsion Tabl (Part 1 of 2) scription Spcification Millimtrs Symbol Ordring Cod Rfrnc M Min. Nom. Max. Packag Acronym MBGA A 1.20 Substrat Matrial BT A Soldr Ball Composition Pb-fr: Sn:3Ag:0.5Cu (Typ.) A JC Outlin Rfrnc MO-195 Variation: AB A RF Octobr 2008 Altra Corporation MAX II vic Handbook

6 7 4 Chaptr 7: Packag Information Packag Outlins Packag Information (Part 2 of 2) Packag Outlin imnsion Tabl (Part 2 of 2) Maximum Lad Coplanarity inchs (0.08 mm) 5.00 BSC Wight 0.1 g 5.00 BSC Moistur Snsitivity Lvl Printd on moistur barrir bag b BSC Figur Pin Micro FinLin BGA Packag Outlin TOP VIW BOTTOM VIW Pin A1 Cornr A Pin A1 I B C F G H J b A A2 A3 A1 MAX II vic Handbook Octobr 2008 Altra Corporation

7 Chaptr 7: Packag Information 7 5 Packag Outlins 100-Pin Plastic Thin Quad Flat Pack (TQFP) All dimnsions and tolrancs conform to ANSI Y14.5M 1994 Controlling dimnsion is in millimtrs Pin 1 may b indicatd by an I dot, or a spcial fatur, in its proximity on packag surfac Packag Information Packag Outlin imnsion Tabl scription Spcification Millimtrs Symbol Ordring Cod Rfrnc T Min. Nom. Max. Packag Acronym TQFP A 1.20 Ladfram Matrial Coppr A Lad Finish (Plating) Rgular: 85Sn:15Pb (Typ.) Pb-fr: Matt Sn A BSC JC Outlin Rfrnc MS-026 Variation: A BSC Maximum Lad Coplanarity inchs (0.08mm) BSC Wight 0.6 g BSC Moistur Snsitivity Lvl Printd on moistur barrir bag L L RF S 0.20 b c BSC θ Octobr 2008 Altra Corporation MAX II vic Handbook

8 7 6 Chaptr 7: Packag Information Packag Outlins Figur Pin TQFP Packag Outlin Pin Pin 1 Pin 1 I 1 Pin 25 A2 A S tail A A1 TAIL A C Gag Plan b S L 0.25mm L1 MAX II vic Handbook Octobr 2008 Altra Corporation

9 Chaptr 7: Packag Information 7 7 Packag Outlins 100-Pin Micro FinLin Ball-Grid Array (MBGA) All dimnsions and tolrancs conform to ASM Y Controlling dimnsion is in millimtrs. Pin A1 may b indicatd by an I dot, or a spcial fatur, in its proximity on packag surfac Packag Information Packag Outlin imnsion Tabl scription Spcification Millimtrs Symbol Ordring Cod Rfrnc M Min. Nom. Max. Packag Acronym MBGA A 1.20 Substrat Matrial BT A Soldr Ball Composition Pb-fr: Sn:3Ag:0.5Cu (Typ.) A JC Outlin Rfrnc MO-195 Variation: AC A RF Maximum Lad Coplanarity inchs (0.08 mm) 6.00 BSC Wight 0.1 g 6.00 BSC Moistur Snsitivity Lvl Printd on moistur barrir bag b BSC Octobr 2008 Altra Corporation MAX II vic Handbook

10 7 8 Chaptr 7: Packag Information Packag Outlins Figur Pin Micro FinLin BGA Packag Outlin TOP VIW BOTTOM VIW Pin A1 Cornr A Pin A1 I B C F G H J K L b A A2 A3 A1 100-Pin FinLin Ball-Grid Array (FBGA) All dimnsions and tolrancs conform to ASM Y Controlling dimnsion is in millimtrs Pin A1 may b indicatd by an I dot, or a spcial fatur, in its proximity on packag surfac Packag Information Packag Outlin imnsion Tabl scription Spcification Millimtrs Symbol Ordring Cod Rfrnc F Min. Nom. Max. Packag Acronym FBGA A 1.55 Substrat Matrial BT A MAX II vic Handbook Octobr 2008 Altra Corporation

11 Chaptr 7: Packag Information 7 9 Packag Outlins Packag Information Packag Outlin imnsion Tabl Soldr Ball Composition Rgular: 63Sn:37Pb (Typ.) Pb-fr: Sn:3Ag:0.5Cu (Typ.) A RF A JC Outlin Rfrnc MO-192 Variation: AC BSC Maximum Lad Coplanarity inchs (0.20 mm) BSC Wight 0.6 g b Moistur Snsitivity Lvl Printd on moistur barrir bag 1.00 BSC Figur Pin FinLin BGA Packag Outlin TOP VIW BOTTOM VIW Pin A1 Cornr A Pin A1 I B C F G H J K b A A2 A3 A1 Octobr 2008 Altra Corporation MAX II vic Handbook

12 7 10 Chaptr 7: Packag Information Packag Outlins 144-Pin Plastic Thin Quad Flat Pack (TQFP) All dimnsions and tolrancs conform to ANSI Y14.5M 1994 Controlling dimnsion is in millimtrs Pin 1 may b indicatd by an I dot, or a spcial fatur, in its proximity on packag surfac Packag Information Packag Outlin Figur Rfrnc scription Spcification Millimtrs Symbol Ordring Cod Rfrnc T Min. Nom. Max. Packag Acronym TQFP A 1.60 Ladfram Matrial Coppr A Lad Finish (Plating) Rgular: 85Sn:15Pb (Typ.) Pb-fr: Matt Sn A BSC JC Outlin Rfrnc MS-026 Variation: BFB BSC Maximum Lad Coplanarity inchs (0.08 mm) BSC Wight 1.1 g BSC Moistur Snsitivity Lvl Printd on moistur barrir bag L L RF S 0.20 b c BSC θ MAX II vic Handbook Octobr 2008 Altra Corporation

13 Chaptr 7: Packag Information 7 11 Packag Outlins Figur Pin TQFP Packag Outlin 1 Pin 144 Pin 1 Pin 1 I 1 Pin 36 A2 A S tail A A1 TAIL A C Gag Plan b S L L1 0.25mm Octobr 2008 Altra Corporation MAX II vic Handbook

14 7 12 Chaptr 7: Packag Information Packag Outlins 144-Pin Micro FinLin Ball-Grid Array (MBGA) Wir Bond All dimnsions and tolrancs conform to ASM Y14.5M Controlling dimnsion is in millimtrs. Pin A1 may b indicatd by an I dot, or a spcial fatur, in its proximity on packag surfac Packag Information Packag Outlin imnsion Tabl scription Spcification Millimtrs Symbol Ordring Cod Rfrnc M Min. Nom. Max. Packag Acronym MBGA A 1.20 Substrat Matrial BT A Soldr Ball Composition Pb-fr: Sn:3Ag:0.5Cu (Typ.) A JC Outlin Rfrnc MO-195 Variation: A A RF Maximum Lad Coplanarity inchs (0.08 mm) 7.00 BSC Wight 0.1 g 7.00 BSC Moistur Snsitivity Lvl Printd on moistur barrir bag b BSC MAX II vic Handbook Octobr 2008 Altra Corporation

15 Chaptr 7: Packag Information 7 13 Packag Outlins Figur Pin Micro FinLin BGA Packag Outlin TOP VIW BOTTOM VIW Pin A1 Cornr A Pin A1 I B C F G H J K L M N A3 A2 A b A1 256-Pin Micro FinLin Ball-Grid Array (MBGA) All dimnsions and tolrancs conform to ASM Y Controlling dimnsion is in millimtrs Pin A1 may b indicatd by an I dot, or a spcial fatur, in its proximity on packag surfac Packag Information (Part 1 of 2) Packag Outlin imnsion Tabl (Part 1 of 2) scription Spcification Millimtrs Symbol Ordring Cod Rfrnc M Min. Nom. Max. Packag Acronym MBGA A 1.20 Substrat Matrial BT A Soldr Ball Composition Pb-fr: Sn:3Ag:0.5Cu (Typ.) A JC Outlin Rfrnc MO-192 Variation: BH A RF Maximum Lad Coplanarity inchs (0.08 mm) BSC Wight 0.3 g BSC Octobr 2008 Altra Corporation MAX II vic Handbook

16 7 14 Chaptr 7: Packag Information Packag Outlins Packag Information (Part 2 of 2) Packag Outlin imnsion Tabl (Part 2 of 2) Moistur Snsitivity Lvl Printd on moistur barrir bag b BSC Figur Pin Micro FinLin BGA Packag Outlin TOP VIW BOTTOM VIW Pin A1 Cornr Pin A1 I b A A2 A3 A1 MAX II vic Handbook Octobr 2008 Altra Corporation

17 Chaptr 7: Packag Information 7 15 Packag Outlins 256-Pin FinLin Ball-Grid Array (FBGA) All dimnsions and tolrancs conform to ANSI Y14.5M 1994 Controlling dimnsion is in millimtrs Pin A1 may b indicatd by an I dot, or a spcial fatur, in its proximity on packag surfac Packag Information Packag Outlin imnsion Tabl scription Spcification Millimtrs Ordring Cod Rfrnc F Min. Nom. Max. Packag Acronym FBGA A 2.20 Substrat Matrial BT A Soldr Ball Composition Rgular: 63Sn:37Pb (Typ.) Pb-fr: Sn:3Ag:0.5Cu (Typ.) A A RF JC Outlin Rfrnc MS-034 Variation: AAF BSC Maximum Lad Coplanarity inchs (0.20 mm) BSC Wight 1.5 g b Moistur Snsitivity Lvl Printd on moistur barrir bag 1.00 BSC Octobr 2008 Altra Corporation MAX II vic Handbook

18 7 16 Chaptr 7: Packag Information Packag Outlins Figur Pin FinLin BGA Packag Outlin TOP VIW BOTTOM VIW Pin A1 Cornr Pin A1 I b A A2 A3 A1 324-Pin FinLin Ball-Grid Array (FBGA) All dimnsions and tolrancs conform to ANSI Y14.5M 1994 Controlling dimnsion is in millimtrs Pin A1 may b indicatd by an I dot, or a spcial fatur, in its proximity on packag surfac Packag Information (Part 1 of 2) Packag Outlin imnsion Tabl (Part 1 of 2) scription Spcification Millimtrs Symbol Ordring Cod Rfrnc F Min. Nom. Max. Packag Acronym FBGA A 2.20 Substrat Matrial BT A Soldr Ball Composition Rgular: 63Sn:37Pb (Typ.) Pb-fr: Sn:3Ag:0.5Cu (Typ.) A A RF JC Outlin Rfrnc MS-034 Variation: AAG BSC Maximum Lad Coplanarity inchs (0.20 mm) BSC Wight 1.6 g b MAX II vic Handbook Octobr 2008 Altra Corporation

19 Chaptr 7: Packag Information 7 17 Packag Outlins Packag Information (Part 2 of 2) Packag Outlin imnsion Tabl (Part 2 of 2) Moistur Snsitivity Lvl Printd on moistur barrir bag 1.00 BSC Figur Pin FinLin BGA Packag Outlin TOP VIW BOTTOM VIW Pin A1 Cornr Pin A1 I b A3 A2 A A1 Octobr 2008 Altra Corporation MAX II vic Handbook

20 7 18 Chaptr 7: Packag Information ocumnt Rvision History ocumnt Rvision History Tabl 7 3. ocumnt Rvision History Tabl 7 3 shows th rvision history for this chaptr. at and Rvision Changs Mad Summary of Changs Octobr 2008, Updatd Nw ocumnt Format. vrsion 2.1 cmbr 2007, Updatd Tabl 7 1 and Tabl 7 2. Updatd documnt with vrsion 2.0 MAX IIZ information. cmbr 2006, vrsion 1.4 July 2006, vrsion 1.3 August 2005, vrsion 1.2 cmbr 2004, vrsion 1.1 Addd 68-Pin Micro FinLin Ball-Grid Array (MBGA) Wir Bond and 144-Pin Micro FinLin Ball-Grid Array (MBGA) Wir Bond sctions. Rplacd Figur 7 9 with corrct diagram. Addd information about 68-Pin Micro FinLin Ball-Grid Array and 144- Pin Micro FinLin Ball-Grid Array. Addd documnt rvision history. Updatd packaging information. Updatd th 100-pin plastic thin quad flat pack (TQFP) information. Updatd Board coupling Guidlins sction (changd th 0.2 valu to 0.1.) MAX II vic Handbook Octobr 2008 Altra Corporation

21 8. Using MAX II vics in Multi-Voltag Systms MII Introduction Tchnological advancmnts in dp submicron procsss hav lowrd th supply voltag lvls of smiconductor dvics, crating a dsign nvironmnt whr dvics on a systm board may potntially us many diffrnt supply voltags such as 5.0, 3.3, 2.5, 1.8, and 1.5 V, which can ultimatly lad to voltag conflicts. To accommodat intrfacing with a varity of dvics on systm boards, MAX II dvics hav MultiVolt I/O intrfacs that allow dvics in a mixd-voltag dsign nvironmnt to communicat dirctly with MAX II dvics. Th MultiVolt intrfac sparats th powr supply voltag (V CCINT ) from th output voltag (V CCIO ), nabling MAX II dvics to intrfac with othr dvics using a diffrnt voltag lvl on th sam printd circuit board (PCB). Additionally, th MAX II dvic family supports th MultiVolt cor fatur. For 1.8-V opration, us th MAX IIG or MAX IIZ dvics. Th 1.8-V input dirctly powrs th cor of th dvics. For 2.5-V or 3.3-V opration, us th MAX II dvics. MAX II dvics that support 2.5-V and 3.3-V opration hav an intrnal voltag rgulator that rgulats at 1.8 V. This chaptr discusss svral faturs that allow you to implmnt Altra dvics in multipl-voltag systms without damaging th dvic or th systm, including: Hot Sockting Insrt or rmov MAX II dvics to and from a powrd-up systm without affcting th dvic or systm opration Powr-Up Squnc Flxibility MAX II dvics can accommodat any possibl powr-up squnc Powr-On Rst MAX II dvics maintain a rst stat until voltag is within oprating rang This chaptr contains th following sctions: I/O Standards on pag 8 2 MultiVolt Cor and I/O Opration on pag V vic Compatibility on pag 8 3 Rcommndd Oprating Condition for 5.0-V Compatibility on pag 8 7 Hot Sockting on pag 8 8 Powr-Up Squncing on pag 8 8 Powr-On Rst on pag 8 8 Octobr 2008 Altra Corporation MAX II vic Handbook

22 8 2 Chaptr 8: Using MAX II vics in Multi-Voltag Systms I/O Standards I/O Standards Th I/O buffr of MAX II dvics is programmabl and supports a wid rang of I/O voltag standards. ach I/O bank in a MAX II dvic can b programmd to comply with a diffrnt I/O standard. All I/O banks can b configurd with th following standards: 3.3-V LVTTL/LVCMOS 2.5-V LVTTL/LVCMOS 1.8-V LVTTL/LVCMOS 1.5-V LVCMOS Th Schmitt triggr input option is supportd by th 3.3-V and 2.5-V I/O standards. Th I/O Bank 3 also includs 3.3-V PCI I/O standard intrfac capability on th PM1270 and PM2210 dvics. S Figur 8 1. Figur 8 1. I/O Standards Supportd by MAX II vic (Not 1), (2), (3), (4), (5) I/O Bank 2 I/O Bank 3 also supports th 3.3-V PCI I/O Standard I/O Bank 1 All I/O Banks support 3.3-V LVTTL/LVCMOS 2.5-V LVTTL/LVCMOS 1.8-V LVTTL/LVCMOS 1.5-V LVCMOS I/O Bank 3 Individual Powr Bus I/O Bank 4 Nots to Figur 8 1: (1) Figur 8 1 is a top viw of th silicon di. (2) Figur 8 1 is a graphical rprsntation only. Rfr to th pin list and th Quartus II softwar for xact pin locations. (3) PM240 and PM570 dvics only hav two I/O banks. (4) Th 3.3-V PCI I/O standard is only supportd in PM1270 and PM2210 dvics. (5) Th Schmitt triggr input option for 3.3-V and 2.5-V I/O standards is supportd for all I/O pins. MAX II vic Handbook Octobr 2008 Altra Corporation

23 Chaptr 8: Using MAX II vics in Multi-Voltag Systms 8 3 MultiVolt Cor and I/O Opration MultiVolt Cor and I/O Opration MAX II dvics includ MultiVolt cor I/O opration capability, allowing th cor and I/O blocks of th dvic to b powrd-up with sparat supply voltags. Th VCCINT pins supply powr to th dvic cor and th VCCIO pins supply powr to th dvic I/O buffrs. Th VCCINT pins can b powrd-up with 1.8 V for MAX IIG and MAX IIZ dvics or 2.5/3.3 V for MAX II dvics. All th VCCIO pins for a givn I/O bank that hav MultiVolt capability should b supplid from th sam voltag lvl (for xampl, 5.0, 3.3, 2.5, 1.8, or 1.5 V). S Figur 8 2. Figur 8 2. Implmnting a Multipl-Voltag Systm with a MAX II vic (Not 1), (2), (3), (4) 1.8 V/2.5 V/3.3 V Powr Supply V CCINT 5.0-V vic V CCIO MAX II vic VCCIO 3.3-V vic V CCIO 2.5-V vic Nots to Figur 8 2: (1) For MAX IIG and MAX IIZ dvics, VCCINT pins will only accpt a 1.8-V powr supply. (2) For MAX II dvics, VCCINT pins will only accpt a 2.5-V or 3.3-V powr supply. (3) MAX II dvics can driv a 5.0-V TTL input whn V CCIO = 3.3 V. To driv a 5.0-V CMOS, an opn-drain stting with intrnal I/O clamp diod and xtrnal rsistor ar rquird. (4) MAX II dvics can b 5.0-V tolrant with th us of an xtrnal rsistor and th intrnal I/O clamp diod on PM1270 and PM2210 dvics. 5.0-V vic Compatibility A MAX II dvic can driv a 5.0-V TTL dvic by conncting th V CCIO pins of th MAX II dvic to 3.3 V. This is possibl bcaus th output high voltag (V OH ) of a 3.3- V intrfac mts th minimum high-lvl voltag of 2.4 V of a 5.0-V TTL dvic. A MAX II dvic may not corrctly introprat with a 5.0-V CMOS dvic if th output of th MAX II dvic is connctd dirctly to th input of th 5.0-V CMOS dvic. If th MAX II dvic s V OUT is gratr than V CCIO, th PMOS pull-up transistor still conducts if th pin is driving high, prvnting an xtrnal pull-up rsistor from pulling th signal to 5.0 V. To mak MAX II dvic outputs compatibl with 5.0-V CMOS dvics, configur th output pins as opn-drain pins with th I/O clamp diod nabld, and us an xtrnal pull-up rsistor. S Figur 8 3. Octobr 2008 Altra Corporation MAX II vic Handbook

24 8 4 Chaptr 8: Using MAX II vics in Multi-Voltag Systms 5.0-V vic Compatibility Figur 8 3. MAX II vic Compatibility with 5.0-V CMOS vics 3.3 V 5.0 V ± 0.5 V V CCIO V CCIO V CCIO (1) R XT Modl as R INT Opn rain V OUT A 5.0-V CMOS vic V IN VSS Not to Figur 8 3: (1) This diod is only activ aftr powr-up. MAX II dvics rquir an xtrnal diod if drivn by 5.0 V bfor powr-up. Th opn-drain pin nvr drivs high, only low or tri-stat. Whn th opn-drain pin is activ, it drivs low. Whn th opn-drain pin is inactiv, th pin is tri-statd and th trac pulls up to 5.0 V by th xtrnal rsistor. Th purpos of nabling th I/O clamp diod is to protct th MAX II dvic s I/O pins. Th 3.3-V V CCIO supplid to th I/O clamp diods causs th voltag at point A to clamp at 4.0 V, which mts th MAX II dvic s rliability limits whn th trac voltag xcds 4.0 V. Th dvic oprats succssfully bcaus a 5.0-V input is within its input spcification. 1 Th I/O clamp diod is only supportd in th PM1270 and PM2210 dvics I/O Bank 3. An xtrnal protction diod is ndd for othr I/O banks in PM1270 and PM2210 dvics and all I/O pins in PM240 and PM570 dvics. Th pull-up rsistor valu should b small nough for sufficint signal ris tim, but larg nough so that it dos not violat th I OL (output low) spcification of MAX II dvics. Th maximum MAX II dvic I OL dpnds on th programmabl driv strngth of th I/O output. Tabl 8 1 shows th programmabl driv strngth sttings that ar availabl for th 3.3-V LVTTL/LVCMOS I/O standard for MAX II dvics. Th Quartus II softwar uss th maximum currnt strngth as th dfault stting. Th PCI I/O standard is always st at 20 ma with no altrnat stting. Tabl V LVTTL/LVCMOS Programmabl riv Strngth I/O Standard I OH /I OL Currnt Strngth Stting (ma) 3.3-V LVTTL V LVCMOS 8 4 MAX II vic Handbook Octobr 2008 Altra Corporation

25 Chaptr 8: Using MAX II vics in Multi-Voltag Systms V vic Compatibility To comput th rquird valu of R XT, first calculat th modl of th opn-drain transistors on th MAX II dvic. This output rsistor (R XT ) can b modld by dividing V OL by I OL (R XT = V OL /I OL ). Tabl 8 2 shows th maximum V OL for th 3.3-V LVTTL/LVCMOS I/O standard for MAX II dvics. f For mor information about I/O standard spcifications, rfr to th C and Switching Charactristics chaptr in th MAX II vic Handbook. Tabl V LVTTL/LVCMOS Maximum V OL I/O Standard Voltag (V) 3.3-V LVTTL V LVCMOS 0.20 Slct R XT so that th MAX II dvic s I OL spcification is not violatd. You can comput th rquird pull-up rsistor valu of R XT by using th quation: R XT = (V CC /I OL ) R INT. For xampl, if an I/O pin is configurd as a 3.3-V LVTTL with a 16 ma driv strngth, givn that th maximum powr supply (V CC ) is 5.5 V, th valu of R XT can b calculatd as follows: quation 8 1. R ( 5.5 V 0.45 V) XT = = Ω 16 ma This rsistor valu computation assums worst-cas conditions. You can adjust th R XT valu according to th dvic configuration driv strngth. Additionally, if your systm dos not s a wid variation in voltag-supply lvls, you can adjust ths calculations accordingly. Bcaus MAX II dvics ar 3.3-V, 32-bit, 66-MHz PCI compliant, th input circuitry accpts a maximum high-lvl input voltag (V IH ) of 4.0 V. To driv a MAX II dvic with a 5.0-V dvic, you must connct a rsistor (R 2 ) btwn th MAX II dvic and th 5.0-V dvic. S Figur 8 4. Octobr 2008 Altra Corporation MAX II vic Handbook

26 8 6 Chaptr 8: Using MAX II vics in Multi-Voltag Systms 5.0-V vic Compatibility Figur 8 4. riving a MAX II PCI-Compliant vic with a 5.0-V vic 5.0 V ± 0.5 V 5.0-V vic MAX II vic 3.3 V V CCIO V CC PCI Clamp (1) V CCIO I R 2 I Modl as R 1 B Not to Figur 8 4: (1) This diod is only activ aftr powr-up. MAX II dvics rquir an xtrnal diod if drivn by 5.0 V bfor powr-up. If V CCIO for MAX II dvics is 3.3 V and th I/O clamp diod is nabld, th voltag at point B in Figur 8 4 is 4.0 V, which mts th MAX II dvics rliability limits whn th trac voltag xcds 4.0 V. To limit larg currnt draw from th 5.0-V dvic, R 2 should b small nough for a fast signal ris tim and larg nough so that it dos not violat th high-lvl output currnt (I OH ) spcifications of th dvics driving th trac. To comput th rquird valu of R 2, first calculat th modl of th pull-up transistors on th 5.0-V dvic. This output rsistor (R 1 ) can b modld by dividing th 5.0-V dvic supply voltag (V CC ) by th I OH : R 1 = V CC /I OH Figur 8 5 shows an xampl of typical output driv charactristics of a 5.0-V dvic. Figur 8 5. Output riv Charactristics of a 5.0-v vic Typical I O Output Currnt (ma) I OL V CCINT = 5.0 V V CCIO = 5.0 V I OH V O Output Voltag (V) 5 MAX II vic Handbook Octobr 2008 Altra Corporation

27 Chaptr 8: Using MAX II vics in Multi-Voltag Systms 8 7 Rcommndd Oprating Condition for 5.0-V Compatibility As shown abov, R 1 = 5.0 V/135 ma. Th valus usually shown in data shts rflct typical oprating conditions. Subtract 20% from th data sht valu for guard band. This subtraction applid to th abov xampl givs R 1 a valu of 30. Slct R 2 so that th MAX II dvic s I OH spcification is not violatd. For xampl, if th abov dvic has a maximum I OH of 8 ma, givn th I/O clamp diod, V IN = V CCIO V = 3.7 V. Givn that th maximum supply load of a 5.0-V dvic (V CC ) is 5.5 V, th valu of R 2 can b calculatd as follows: quation 8 2. R ( 5.5 V 3.7 V) ( 8 ma 30 Ω) 2 = = 194 Ω 8 ma This analysis assums worst-cas conditions. If your systm dos not s a wid variation in voltag-supply lvls, you can adjust ths calculations accordingly. Bcaus 5.0-V dvic tolranc in MAX II dvics rquirs us of th I/O clamp, and this clamp is activatd only aftr powr-up, 5.0-V signals may not b drivn into th dvic until it is configurd. Th I/O clamp diod is only supportd in th PM1270 and PM2210 dvics I/O Bank 3. An xtrnal protction diod is ndd for othr I/O banks for PM1270 and PM2210 dvics and all I/O pins in PM240 and PM570 dvics. Rcommndd Oprating Condition for 5.0-V Compatibility As mntiond arlir, a 5.0-V tolranc can b supportd with th I/O clamp diod nabld with xtrnal sris/pull-up rsistanc. To guarant long trm rliability of th dvic s I/O buffr, thr ar rstrictions on th signal duty cycl that driv th MAX II I/O, which is basd on th maximum clamp currnt. Tabl 8 3 shows th maximum signal duty cycl for 3.3-V V CCIO givn a PCI clamp currnt-handling capability. Tabl 8 3. Maximum Signal uty Cycl V IN (V) (1) I CH (ma) (2) Max uty Cycl (%) Nots to Tabl 8 3: (1) V IN is th voltag at th packag pin. (2) Th I CH is calculatd with a 3.3-V V CCIO. A highr V CCIO valu will hav a lowr I CH valu with th sam V IN. Octobr 2008 Altra Corporation MAX II vic Handbook

28 8 8 Chaptr 8: Using MAX II vics in Multi-Voltag Systms Hot Sockting For signals with duty cycl gratr than 30% on MAX II input pins, Altra rcommnds a V CCIO voltag of 3.0 V to guarant long-trm I/O rliability. For signals with duty cycl lss than 30%, th V CCIO voltag can b 3.3 V. Hot Sockting Powr-Up Squncing Powr-On Rst For information about hot sockting, rfr to th Hot Sockting and Powr-On Rst in MAX II vics chaptr in th MAX II vic Handbook. MAX II dvics ar dsignd to oprat in multipl-voltag nvironmnts whr it may b difficult to control powr squncing. Thrfor, MAX II dvics ar dsignd to tolrat any possibl powr-up squnc. ithr V CCINT or V CCIO can initially supply powr to th dvic, and 3.3-V, 2.5-V, 1.8-V, or 1.5-V input signals can driv th dvics without spcial prcautions bfor V CCINT or V CCIO is applid. MAX II dvics can oprat with a V CCIO voltag lvl that is highr than th V CCINT lvl. Whn V CCIO and V CCINT ar supplid from diffrnt powr sourcs to a MAX II dvic, a dlay btwn V CCIO and V CCINT may occur. Normal opration dos not occur until both powr supplis ar in thir rcommndd oprating rang. Whn V CCINT is powrdup, th I Std Joint Tst Action Group (JTAG) circuitry is activ. If th TMS and TCK ar connctd to V CCIO and V CCIO is not powrd-up, th JTAG signals ar lft floating. Thus, any transition on TCK can caus th stat machin to transition to an unknown JTAG stat, lading to incorrct opration whn V CCIO is finally powrd-up. To disabl th JTAG stat during th powr-up squnc, TCK should b pulld low to nsur that an inadvrtnt rising dg dos not occur on TCK. For information about Powr-On Rst (POR), rfr to th Hot Sockting and Powr-On Rst in MAX II vics chaptr in th MAX II vic Handbook. Conclusion MAX II dvics hav MultiVolt I/O support, allowing 1.5-V, 1.8-V, 2.5-V, and 3.3-V dvics to intrfac dirctly with MAX II dvics without causing voltag conflicts. In addition, MAX II dvics can intrfac with 5.0-V dvics by slightly modifying th xtrnal hardwar intrfac and nabling I/O clamp diods via th Quartus II softwar. This MultiVolt capability also nabls th dvic cor to run at its cor voltag, V CCINT, whil maintaining I/O pin compatibility with othr dvics. Altra has takn furthr stps to mak systm dsign asir by dsigning dvics that allow V CCINT and V CCIO to powr-up in any squnc and by incorporating support for hot sockting. MAX II vic Handbook Octobr 2008 Altra Corporation

29 Chaptr 8: Using MAX II vics in Multi-Voltag Systms 8 9 Rfrncd ocumnts Rfrncd ocumnts ocumnt Rvision History Tabl 8 4. ocumnt Rvision History This chaptr rfrncs th following documnts: C and Switching Charactristics chaptr in th MAX II vic Handbook Hot Sockting and Powr-On Rst in MAX II vics chaptr in th MAX II vic Handbook Tabl 8 4 shows th rvision history for this chaptr. at and Rvision Changs Mad Summary of Changs Octobr 2008, Updatd Figur 8 2. vrsion 1.7 Updatd 5.0-V vic Compatibility and Conclusion sctions. cmbr 2007, vrsion 1.6 cmbr 2006, vrsion 1.5 August 2006, vrsion 1.4 Fbruary 2006, vrsion 1.3 January 2005, vrsion 1.2 cmbr 2004, vrsion 1.1 Updatd Nw ocumnt Format. Updatd Introduction sction. MultiVolt Cor and I/O Opration sction. Updatd (Not 1) to Figur 8 2. Addd Rfrncd ocumnts sction. Updatd documnt with MAX IIZ information. Addd documnt rvision history. Updatd 5.0-V vic Compatibility sction. Updatd Figur 8 3. Prviously publishd as Chaptr 9. No changs to contnt. Corrctd typographical rrors in Not 3 of Figur 8 2. Octobr 2008 Altra Corporation MAX II vic Handbook

30 8 10 Chaptr 8: Using MAX II vics in Multi-Voltag Systms ocumnt Rvision History MAX II vic Handbook Octobr 2008 Altra Corporation