Cell-phone ASIC complexity and cost

Transcription

1 Memories Cell-phone ASIC compleity and cost Viktor Öwall Dept. of Electrical and Information Technology Lund University Parts of this material was adapted from the instructor material to Jan M. Rabaey, Digital Integrated Circuits: A Design Perspective Viktor Öwall, ASIC/DSP, CCCD, Dept. of Applied Electronics, Lund University, Sweden- Courtesy: Sven Mattisson, EMP Market for Memories According to a new technical market research report, semiconductor Memory: Technologies and Global Markets, the value of the global semiconductor memory industry was nearly $46.2 billion in 29, but is epected to increase to nearly $79 billion in 24, for a 5-year compound annual growth rate (CAGR) of.3%. The largest segment of the market, DRAM, or dynamic random access memory, is projected to increase at a CAGR of.4% to $4.5 billion in 24, after being valued at nearly $ billion in 29. NAND, or nonvolatile/nano RAM, which is the second-largest segment of the market, is estimated t at $2.8 billion in 29, and is epected to increase at a 5-year CAGR of 5% to reach more than $25.7 billion in 24. Source: Semiconductor ctor Memory: Technologies and Global Markets, April 2 From Semiconductor-Memory-To-Be-Worth-79-Billion-In-24/Page.html Report Price: Price:USD $4,85.!!!!!! Motivation behind the quest for new memory technologies! RAMs ROMs Echo Canceller Chip Size ca. 5 6 mm 2 RAMs 25kbits 2 ROMs 3kbits.35 m, 5 Metal Layer CMOS, >2 million transistors. Anders Berkeman 22

2 Semiconductor Memory Classification Read-Write Memories Nonvolatile Read-Only (RWM) RWM Memories Random Non-Random (NVRWM) (Nonvolatile) Access Access SRAM FIFO PROM ROM DRAM Register- Bank LIFO(Stack) Shiftregister CAM EPROM E 2 PROM FLASH PLA CAM = contents addressable memory Nonvolatile = data kept when supply voltage turned off PROM = Programmable rom EPROM = erasable programmable ROM E 2 PROM & Flash= electrically erasable programmable ROM XXPROM & Flash Nonvolatile = data kept when supply voltage turned of PROM = EPROM = EEPROM or E 2 PROM = Flash= Fuse based One time programmable Usually erasable by UV-light Usually high voltage for programming removed from circuit when programmed Individual bytes can be erased slow but versatile Larger than EPROM Larger sections are erased faster than EEPROM Emerging Technologies We have registers, why memories? MRAM = Magnetoresistive RAM Electric current switches the magnetic polarity and Change in magnetic polarity sensed as resistance change D Flip-flop : 252µm 2 Memory element : 3µm 2 FeRAM or FRAM = Ferroelectric RAM Crystal polarize when electric field applied Polarization will lead to different charge when read Polymer memories Change in resistance due to ionic transport with applied electric field AND MORE...

3 Flip-flops vs. SRAM Alcatel Microelectronics.35µm CMOS technology process Process and library dependent..8 Memory Classification by ports Single port: Read & Write.6.4 Flip-flops Dual port memory Single port memory Double width memory Dual Port: Read and Write separate Dual address port squa are mm memory elements Multiple ports More ports makes more efficient addressing schemes es possible but increase the cost of the memory, i.e. cost, compleity,... Dual Port Functionality by using Single Port Memories a) 2 single port memories b) single port memory with double word length a) b) Single port RAM 326 Single port RAM 326 3:6 3:6 Single port RAM : ADDR 5: nwe Memory essing N Words = N Ad ddress bits S S S 2 S N-3 S N-2 S N- M bits Word Word Word N-3 Word N-2 Word N- Storage Cell bits N Words = log 2 N ess b es ss Decod der S M bits Word Word Word N-3 Word N-2 Word N- Storage Cell ess counter ess counter Input-Output t t (M bits) Input-Output t t (M bits) Decoder reduce number of address bits from N to log2 N

4 ress bits ess s Decode er S Large Memories Mbit bits Word Word Word N-3 Word N-2 Word N- Sense Amplifiers/ Drivers Input-Output (M bits) Large memories Disproportional height and width bizarre shape long delays A K A K+ A L- ress Deco oder Reduced to 2 L-K A A K- Column Decoding 2 K Columns Sense Amplifiers/ Drivers Column Decoder Input-Output (M bits) Bit Line () Reduced d Height by Column Decoding One complete word line is accessed Word Line () Long Wordline Wasted power (unless all words are used through memory management) Row Col Block Hierarchical Memory Enable single memory Global Data Bus A smaller memory is accessed Large Buffers to drive bus Length of and are reduced Hierarchical Memory, contd. Row Col Block Mu/Drivers Memory Bus Global Data Bus Variations of hierarchical memory structure reduced size of buffers

5 Eample of Splitting Memories Lookup table of ca. 3 words split into 3 memory blocks (PLAs) Lookup table of ca. 3 words split into 6 memory blocks (PLAs) Signal Properties within Memory ress bits ess s Decode er S M bits Word Storage Word Cell Word N-3 Word N-2 Word N- Sense Amplifiers/ Di Drivers Memory Core Dominant Register cells >tran/bit Simpler storage cells degradation of signal properties p but within confined environment Reduced voltage swing reduced delay & power consumption Sense amplifiers to convert to full swing Difference in size due to PLA minimization! Input-Output (M bits) Memory Generators ROM array Silicon Vendors and/or cell library usually offers a memory generators to handle internal memory issues. Row Word Word Pull Up Col Block Mu/Drivers Memory Bus Word Word bit bit bit bit Global Data Bus The placements of transistors decide memory content.

6 MOS ROM Cells Initially pulled up pulled out out down when = [] [] [2] [3] Pseudo NMOS NOR ROM [] [] [2] [3] Pull Up No transitors = always pulled up A B Q One transistor ON pulls down Bit Line NMOS NOR ROM lines overhead Area Reduced by Mirroring Pseudo NMOS NOR ROM []= []= [2]= [3]= Pull Up A B Q One transistor ON pulls down Bit Line NMOS NOR ROM lines overhead Area Reduced by Mirroring Select [2] [,,3]= and [2] = Cell ( 7 ) MOS NOR ROM Layout One layer to program memory ROM programming can be delayed until last programming steps (Reprogramming g with same layout) Polysilicon Metal Diffusion Metal on Diffusion

7 [] [] [2] [3] Pseudo NMOS NAND ROM [] [] [2] on on off A B Q Pull Up [3] on off All transistors ON pulls down Bit Line Non-selected = lines reversed Select [2] [,,3]= and[2]= Transistor on selected line shuts off path to [] [] [3] [2] Pseudo NMOS NAND ROM [] [] [2] A B Q Pull Up [3] All transistors ON pulls down Bit Line Non-selected = ess lines reversed NMOS NAND ROM No Supply lines by series transistors Large Pull-Up device Long delay MOS NAND ROM Layout Cell (8 7 ) Programmming using the Metal- Layer Only No contact to VDD or necessary; drastically reduced d cell size Loss in performance compared to NOR ROM Polysilicon Diffusion Metal on Diffusion Equivalent Transient Model for MOS NOR ROM [] [] [2] [3] [] [] [2] [3] Pull Up c word Word line parasitics Wire capacitance and gate capacitance Wire resistance (polysilicon) Bit line parasitics Resistance not dominant (metal) Drain and Gate-Drain capacitance Model for NOR ROM r word C bit

8 Equivalent Transient Model for MOS NAND ROM Pull Up Model for NAND ROM Decreasing Word Line Delay [] [] [2] [3] Driving the word line from both ends [] Driver [] r bit C L Polysilicon Word Line [3] r word c bit [2] c word Metal Word Line Word line parasitics Similar to NOR ROM Bit line parasitics Resistance of cascaded transistors dominates Drain/Source and complete gate capacitance Contact Using Metal Bypass Metal Word Line Polysilicon Word Line Pseudo NMOS Pre-charged NOR ROM Problems V OL depends on transistor ratios Static power consumption Alternative Fully complimentary Large area Pre-charged memories pre ch [] [] [2] [3] [] [] [2] [3] NOR field Pre-charge One transistor ON devices pulls down Bit Line 4 4 NMOS NOR Precharged ROM Clocked Reduced d static ti power consumption

9 What is a Flash memory? What is a Flash memory? ROM Read Only Memory RAM Random Access Memory FLASH ROM Read Only Memory data doesn t change data remain when powered down RAM Random Access Memory data can be both read and stored data disappears when powered down FLASH data can be both read and stored data remain when powered down Floating Gate Transistor (FAMOS) electrically programmable V TH Floating gate n + n + Control gate Control gate is connected to wordline Floating gate is left unconnected If charged heavily negative High V TH No channel If charged removed Low V TH Channel erasure Flash EEPROM Control gate n source n drain programming p-substrate Floating gate Thin tunneling oide EPROM, EEPROM and Flash has different ways of controlling the charge of the floating gate

10 FLASH stucture Pull Up FLASH write, e.g. trap charge Pull Up word word word word word2 word3 word2 word3 Floating gate transistors everywhere! = trapped charge. Transitor is always off Same content as ROM. Basic Operations in a NOR Flash Memory Write Basic Operations in a NOR Flash Memory Read S 2 V G 6 V D 2 V V S 5 V G V D 5 V V V V 6 V V V V

11 Basic Operations in a NOR Flash Memory Erase NOR and NAND Flash 2 V cell G V array NOR fast read access slow erasure and programming are slow Samsung: 52Mbit/33MHz S D 2 V V open open NAND slower read access larger storage density fast erasure and programming 28 Samsung: 32 Gbit/2MHz 29 Samsung: 64 Gbit/2MHz - 32 Gbit/4MHz (from Living in the stage of 2GB memory after passing through the dark-ageage of GB in Cross-sections of Floating Gates from Flash Courtesy Intel EPROM

12 Read-Write Memories (RAM) Static (SRAM) Data stored as long as supply is applied Large cells (6 transistors/cell) Fast Differential Dynamic (DRAM) Periodic refresh required Small cells (-3 transistors/bit) Slower Single Ended M5 6-transistor SRAM Cell M2 Q M V dd M4 Q M3 M6 Transistor sizing important to ensure functionality Write: 6-transistor SRAM Cell V dd M4 Write when Q=: Q Pull Q below switching M6 threshold, V dd /2, for M toggle. Q=V dd Q= M5 Q= = = For writing use Transistor sizing important to ensure functionality V dd Read: 6-transistor SRAM Cell Q= M5 Q= M V Read : dd M4 and Q precharged to Q=V dd M6 Vdd V dicharged through M-M5 Important not to change Q! Transistor sizing important to ensure functionality

13 6-transistor SRAM Cell, layout Content-addressable memory (CAM) The time required to find an item stored in memory can be reduced considerably if the item can be identified for access by its content rather than by its address. A memory that is accessed in this way is called content-addressable memory or CAM. CAM provides a performance advantage over other memory search algorithms, such as binary or tree-based searches or look-aside tag buffers, by comparing the desired information against the entire list of pre-stored entries simultaneously, often resulting in an order-of-magnitude reduction in the search time. CAM is ideally suited for several functions, including Ethernet address lookup, data compression, pattern-recognition, cache tags, high-bandwidth address filtering, and fast lookup of routing, user privilege, security or encryption information on a packetby-packet basis for high-performance data switches, firewalls, bridges and routers. For eample, the search key could be the IP address of a network user, and the associated information could be user s access privileges and his location on the network. Source: Content-essable memory (CAM) and its network applications Midas Peng and Sherri Azgomi, Altera International Ltd. EE Times Asia -transistor CAM Cell V dd M2 M4 Q Q M5 M6 M M3 match match precharged If Q = e.g. = & Q= match is pulled down match remains high if Q = for all bits Priority if several lines are valid? For instance in switches and routers W R 3 transistor DRAM Cell R Write cycle W M W X 3 X V M M DD -V T 2 C S Read cycle R 2 V -V V 2 DD T Write Read Inversed Value is Read

14 3 transistor DRAM Cell, layout W R M M 3 C S M 2 transistor t DRAM Cell M X Write 2 Read C S : Gate capacitance of M 2 Nondestructive read Charge loss due to Leakage C S C Destructive Read, needs restore! Write: Data placed on raised and CS charged or discharged Read: precharged Charge distribution gives stored value Restore of transistor t DRAM Cell transistor DRAM Cells V V() M V Pre V() = small change C C S V() Sense amp. activated Word line activated Destructive Read, needs restore! Feedback of sense amplifier output to

15 Sense Amplifier Differential Sensing PC DD S.A. EQ Operation Pre-charge (PC) bitlines and Equalize (EQ) Signal Restoration Low swing in core Reduced power consumption Requires signal restoration Differential input Common Mode rejection (Only in 6-transistor cell) Sense Memory cell Differential Sense Amplifier y y Disable PC and EQ Enable Turn on Sense Sense Amplifiers Analog Amplifiers. EQ SE Sense Amplifiers Cross Coupled Inverters Initialized to metastable point by equalization (EQ) y y y SE SE Very fast Rail-to-rail swing on Bit Lines () increased power consumption Good for T-cell restore V V() SE V Pre V() V() Sense amp. activated Word line activated

16 2-to-4 Dynamic NOR Decoder OFF 3 = ess Decoders ON 2 = = s are precharged A A A A = A A = All but one is pulled down Consumes power 2-to-4 Dynamic NAND Decoder 2-to-4 Dynamic NAND Decoder 3 = OFF 3 = 2 = Series Transistors = ON 2 = = Slow = = A A A A A A A A A A = All but one stays high Less Consumed power

17 PLA versus s ROM PLA- Programmable Logic Array Structured approach to random logic, i.e. implementing Boolean function Two level logic, NOR-NOR or NAND-NAND PLA = Programmable Logic Array AND plane X X X 2 Product terms OR plane Functionality Identical to ROM Main difference: ROM fully populated PLA: One element per minterm, several valid Importance reduced due to Multi-level-logic synthesis (Synopsys) X X X 2 f f f f PLA Pull upp Pre-charged PLA, NOR-NOR Pull upp NAND - NAND AND - OR NOR - NOR DD f f f f

18 Pull upp Pre-charged PLA, NOR-NOR DD f 2 f f f f f f Pull upp Espresso= Boolean Minimization i i.i 7.o 2 Input.type f.phase e.i 7 Minimized.o 2 #.phase.p e AND Plane OR Plane Embedded RAM Is it a problem? Why is it a problem? FFT Design 8k points FFT for DVB (Digital Video Broadcasting) Line memories for efficient dataflow In total t 75 distributed ib t d memories, (5/core + 5 line) Several embedded memories who s properties and size is crucial to the implementation

19 OFDM Synchronization Frame Memories are a dominant part of the construction Stefan Johansson Funding: INTELECT