Mridula Allani Fall Fall
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1 Mridula Allani Fall 2010 Fall
2 Model and document digital systems Hierarchical models System, RTL (Register Transfer Level), gates Different levels of abstraction Behavior, structure Verify circuit/system design via simulation Synthesize circuits from HDL models ELEC / Lecture 2 Fall 2010 (from Prof. Nelson's and Prof. Stroud's course material) 2
3 VHDL = VHSIC Hardware Description Language (VHSIC = Very High Speed Integrated Circuits) Developed by DOD from 1983 based on ADA IEEE Standard /1993/200x Based on the ADA language Verilog created in 1984 by Philip Moorby of Gateway Design Automation (merged with Cadence) IEEE Standard /2001/2005 Based on the C language IEEE P1800 System Verilog in voting stage & will be merged with 1364 ELEC / Lecture 2 Fall 2010 (from Prof. Nelson's and Prof. Stroud's course material) 3
4 Entity describes the external view of a design/component Architecture describes the internal behavior/structure of the component Example: 1-bit full adder A B Full Adder Sum Cin Cout ELEC / Lecture 2 Fall 2010 (from Prof. Nelson's and Prof. Stroud's course material) 4
5 External view comprises input/output signals ( ports ) A port is defined by its signal name, direction and type: port_name: direction data_type; direction: in - driven into the entity from an external source out - driven from within the entity inout - bidirectional drivers within the entity and external data_type: any scalar or aggregate signal type ELEC / Lecture 2 Fall 2010 (from Prof. Nelson's and Prof. Stroud's course material) 5
6 Type std_logic data values: U, X uninitialized/unknown 0, 1 strongly-driven 0/1 L, H weakly-driven 0/1 (resistive) Z, W - strong/weak floating - - don t care Type std_logic_vector is array of std_logic Include package: library IEEE; use IEEE.std_logic_1164.all; ELEC / Lecture 2 Fall 2010 (from Prof. Nelson's and Prof. Stroud's course material) 6
7 ENTITY entity_name IS GENERIC (optional) (generic_name: type :=default_value; generic_name: mode signal_type); PORT (signal_name: mode signal_type; signal_name: mode signal_type); END ENTITY entity_name; ELEC / Lecture 2 Fall 2010 (from Prof. Nelson's and Prof. Stroud's course material) 7
8 A B Full Adder Sum Cin ENTITY Full_adder IS PORT ( -- I/O ports a: IN STD_LOGIC; -- a input b: IN STD_LOGIC; -- b input cin: IN STD_LOGIC; -- carry input sum: OUT STD_LOGIC; -- sum output cout: OUT STD_LOGIC); -- carry output END Full_adder ; Cout ELEC / Lecture 2 Fall 2010 (from Prof. Nelson's and Prof. Stroud's course material) 8
9 ARCHITECTURE architecture_name OF entity_name IS -- data type definitions (ie, states, arrays, etc.) -- internal signal declarations -- component declarations -- function and procedure declarations -- behavior of the model is described here using: -- component instantiations -- concurrent statements -- processes END ARCHITECTURE architecture_name; ELEC / Lecture 2 Fall 2010 (from Prof. Nelson's and Prof. Stroud's course material) 9
10 ARCHITECTURE dataflow OF Full_adder IS sum <= a xor b xor cin; cout <= (a and b) or (a and cin) or (b and cin); END dataflow; ELEC / Lecture 2 Fall 2010 (from Prof. Nelson's and Prof. Stroud's course material) 10
11 ARCHITECTURE structure OF Full_adder IS COMPONENT xor IS -- declare component to be used PORT (x,y: IN BIT; z: OUT BIT); END COMPONENT xor; SIGNAL x1: bit; -- signal internal to this component G1: xor PORT MAP (A, B, X1); -- instantiate 1 st xor gate G2: xor PORT MAP (X1, Cin, Sum); -- instantiate 2 nd xor gate add circuit for carry output END structure; A Cin X1 Sum ELEC / Lecture 2 Fall 2010 (from Prof. Nelson's and Prof. Stroud's course material) 11
12 ARCHITECTURE structural OF Full_adder IS COMPONENT half_adder PORT(a,b : IN STD_LOGIC; sum, carry : OUT STD_LOGIC); END COMPONENT; COMPONENT or_2 PORT(a,b : IN STD_LOGIC; c : OUT STD_LOGIC); END COMPONENT; SIGNAL s1, s2, s3 : STD_LOGIC; H1: half_adder port map(a=>in1, b=>in2, sum=>s1, carry=>s3); H2: half_adder port map(a=>s1, b=>c_in, sum=>sum, carry=>s2); O1: or_2 port map(a=> s2, b=>s3, c=>c_out); END structural; ENTITY half_adder IS PORT (a,b : IN BIT ; sum,carry : OUT BIT); END half_adder; ARCHITECTURE dataflow OF half_adder IS sum<= a xor b; carry <= a and b; END dataflow; ENTITY or_2 IS PORT (a,b : IN BIT ; c : OUT BIT); END or_2; ARCHITECTURE dataflow OF or_2 IS c<= a or b; END dataflow; Fall
13 library ieee; use ieee.std_logic_1164.all; ENTITY adder_4bit IS PORT (a, b: IN STD_LOGIC_VECTOR(3 DOWNTO 0); Cin : IN STD_LOGIC; sum: OUT STD_LOGIC_VECTOR (3 DOWNTO 0); Cout: OUT STD_LOGIC); END adder_4bit; ARCHITECTURE structural OF adder_4bit IS SIGNAL c: STD_LOGIC_VECTOR (4 DOWNTO 0); FA0: Full_adder PORT MAP (a(0), b(0), Cin, sum(0), c(1)); FA1: Full_adder PORT MAP (a(1), b(1), C(1), sum(1), c(2)); FA2: Full_adder PORT MAP (a(2), b(2), C(2), sum(2), c(3)); FA3: Full_adder PORT MAP (a(3), b(3), C(3), sum(3), c(4)); Cout <= c(4); END structural; COMPONENT Full_adder PORT(a, b, c: IN STD_LOGIC; sum, carry: OUT STD_LOGIC); END COMPONENT; Fall
14 ARCHITECTURE behavioral OF Full_adder IS Sum: PROCESS(a, b, cin) sum <= a xor b xor cin; END PROCESS Sum; Carry: PROCESS(a, b, cin) cout <= (a and b) or (a and cin) or (b and cin); END PROCESS Carry; END behavioral; ARCHITECTURE behavioral OF Full_adder IS PROCESS(a, b, cin) sum <= a xor b xor cin; cout <= (a and b) or (a and cin) or (b and cin); END PROCESS; END behavioral; Fall
15 Allows conventional programming language methods to describe circuit behavior Supported language constructs ( sequential statements ) only allowed within a process: variable assignment if-then-else (elsif) case statement while (condition) loop for (range) loop ELEC / Lecture 2 Fall 2010 (from Prof. Nelson's and Prof. Stroud's course material) 15
16 [label:] process (sensitivity list) declarations begin sequential statements end process; Process statements executed once at start of simulation Process halts at end until an event occurs on a signal in the sensitivity list ELEC / Lecture 2 Fall 2010 (from Prof. Nelson's and Prof. Stroud's course material) 16
17 ENTITY dff IS PORT (d,clk: IN STD_LOGIC; q: OUT STD_LOGIC); END dff; ARCHITECTURE behavioral OF dff IS PROCESS(clk) -- process sensitivity list IF (clk event and clk= 1 ) THEN q <= d after 1 ns; END IF; END PROCESS; END behavioral; Process statements executed sequentially (sequential statements) clk event is an attribute of signal clk which is TRUE if an event has occurred on clk at the current simulation time D CLK Q ELEC / Lecture 2 Fall 2010 (from Prof. Nelson's and Prof. Stroud's course material) 17
18 ENTITY dff IS PORT (d,clk: IN STD_LOGIC; q: OUT STD_LOGIC); END dff; D ARCHITECTURE behavioral OF dff IS CLK PROCESS -- no sensitivity list WAIT ON clk; -- suspend process until event on clk IF (clk= 1 ) THEN q <= d AFTER 1 ns; END IF; END PROCESS; END behavioral; Other wait formats: WAIT UNTIL (clk event and clk= 1 ) WAIT FOR 20 ns; Process executes endlessly if no sensitivity list or wait statement! ELEC / Lecture 2 Fall 2010 (from Prof. Nelson's and Prof. Stroud's course material) 18 Q
19 if-then-elsif-else statement if condition then (... sequence of statements...) elsif condition then (... sequence of statements...) else (... sequence of statements...) end if; case statement case expression is when choices => sequence of statements when choices => sequence of statements... when others => sequence of statements end case; ELEC / Lecture 2 Fall 2010 (from Prof. Nelson's and Prof. Stroud's course material) 19
20 while loop [label:] while condition loop... sequence of statements... end loop [label]; for loop [label:] for loop_variable in range loop... sequence of statements... end loop [label]; ELEC / Lecture 2 Fall 2010 (from Prof. Nelson's and Prof. Stroud's course material) 20
21 ARCHITECTURE functional OF Full_adder IS PROCESS(A,B,Cin) If (Cin = '0' and A = '0' and B = '0' ) then sum<= '0'; Cout <= '0'; elsif(cin = '0' and A = '0' and B = '1') then sum <= '1' ; Cout <= '0'; elsif(cin = '0' and A = '1' and B = '0' ) then sum <= '1' ; Cout <= '0'; elsif(cin = '0' and A = '1' and B = '1' ) then sum<= '0'; Cout <= '1'; elsif(cin = '1' and A = '0' and B = '0' ) then sum <= '1' ; Cout <= '0'; elsif(cin = '1' and A = '0' and B = '1' ) then sum<= '0'; Cout <= '1'; elsif(cin = '1' and A = '1' and B = '0' ) then sum<= '0'; Cout <= '1'; elsif(cin = '1' and A = '1' and B = '1' ) then sum <= '1' ; Cout <= '1'; else sum <= 'X' ; Cout <= 'X'; end if; END PROCESS; END functional; Fall
22 ENTITY counter_4bit IS PORT(Ld, Clr, Clk: IN STD_LOGIC; D: IN STD_LOGIC_VECTOR (3 DOWNTO 0); Cout: OUT STD_LOGIC; Qout: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)); END counter_4bit; ARCHITECTURE behavioral OF counter_4bit IS SIGNAL Q: STD_LOGIC_VECTOR(3 DOWNTO 0); Qout <= Q; Cout <= Q(3) and Q(2) and Q(1) and Q(0); PROCESS(Clk) IF Clk'event and Clk = '1' THEN IF Clr = '0' THEN Q <= "0000"; ELSIF Ld = '0' THEN Q <= D; ELSE Q <= Q + 1; END IF; END IF; END PROCESS; END behavioral; Fall
23 VHDL mini-reference on Prof. Nelson s website VHDL resources on Prof. Stroud s website Toc s/m12_23/sld006.htm Fall
24 Modelsim PE (Student Edition) can be downloaded from Modelsim is installed on the Windows7 platform in Lab 310, Broun Hall. Fall
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