Develop ment of Critical Area Research Met hod for Integrated Circuit s and It s Challenges

Transcription

1 Microelect ronics Vol139, No. 5 Oct. 2009,,, (, ) : (DFM),Monte Carlo Voronoi ; : ; ; ; : TN401 :A : (2009) Develop ment of Critical Area Research Met hod for Integrated Circuit s and It s Challenges ZHAN G Guoxia, MA Peijun, ZHAN G Xu, HAO Yue ( I nstit ute of Microelect ronics, X i dian Universit y, X i an , P. R. China) Abstract : Critical area research method is one of the most important research subjects of design for manufacturability (DFM). The mainstream critical area algorithms were summarized and analyzed. Advantages and limitations in Monte Carlo method, polygon operator method and Voronoi diagram were discussed. In addition, challenges to critical area research for deep submicron ICs using new lithography technology were analyzed and discussed in particular. Key words : Integrated circuits ; Critical area ; Critical area algorithm ; Deep submicron lithography EEACC : 2570A 1, [1 ], ( SSI) (MSI) (L SI), (VL SI) ( UL SI) ( GL SI) ITRS2006 [2 ], 3 30 %,32 nm 2020, 14 nm,,, (yield),, : M Y F = 7 i = ( c) Di A i i 2 i,, Y F, i, i,, Di, A ( i c) [3 ], DFM (design for manufact ur2 ing) DF Y(design for yield),dfm : ; : : ( ) ; (SJ082ZT13)

2 5 705, ;DF Y [4 ],,, IC, IC,,,, [ 6 ],, [5 ], (CA), CA,,, ;,,, [ 7 ] 2 : ( A ( i c) ),,, : A ( i c) = R max A ( R) h( R) d R R min, A ( R) R, h( R), Rmin, Rmax [3 ], (pin hole),, (metal island) (imp urties), :,, 1 3, [ 7 ] IC (CAA), ( ) ( ), 3 30, 20

3 ,EDA, Monte Carlo Voronoi 3. 1 Monte Carlo Monte Carlo,,,, Monte Carlo,,, [8. 9 ], (DRC), [18 ] Monte Carlo CA,,,Monte Carlo,, [10 ],, 3. 2, [11 ] Boolean (AND OR ANDNO T EXOR) /,,,,,, [12 ] 4, [13 ] Monte Carlo,,,, [14 ],, DRC, [15 ] 4 R [28] Fig. 4 Extra material and missing material critical areas of defects with diameter R 3. 3 Voronoi, Papadopoulou Voronoi [ 16, 17 ],,, 5 Voronoi, L,p q x y Voronoi + 1 (a) Voronoi (a) Exterior Voronoi diagram

4 5 707 (b) Voronoi [18 ] ( b) Interior Voronoi diagram 5 Voronoi [18 ] Fig. 5 Exterior and interior Voronoi diagrams 21 Voronoi 1/ 3 2/ 3, 245, Voronoi,,, Voronoi,,,2 r, r,, IBM,,, CA E, Voronoi Voronoi, L, Monte Carlo 60, Voronoi,, DRC [ 18 ] 3. 4 Monte Carlo,,, [26 ], Monte Carlo,E YE E YE EYE Cadence, ( hierarchy) Voronoi,, Voronoi VL SI, DFM,,,, virt ual artwork [19 ] scan line [20 ] heuristic analytical [21 ] Wagner Koren [22 ],, 4 ( Process Variation) [7 ] 6 [ 23 ],, 6 [23 ] Fig. 6 Changing wave length for photolithography vs. device feature size,

5 ,,, [24 ],, ( Reticle Enhancement Technology, RET),, (Off2Axis Illumination,OA I) (OPC),,,,, (p hase shif2 ted mask, PSM), [25 ] 7 O PC 7 OPC [29 ] Fig. 7 OPC counteracts lithography distortions,,, 7,,, Monte Carlo Voronoi,:, ;,, 2 2,,, 5, 20 nm (, ),,DFM,, Monte Carlo,, [26 ], Monte Carlo, ( hierarchy),,voronoi,,,,, [3 ], :,, ;, Layout MAS K Silicon,, ; RET,,,,, : [1 ] MOORE G E. Cramming more components onto inte2

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