Taming the Challenges of Advanced-Node Design. Tom Beckley Sr. VP of R&D, Custom IC and Signoff, Silicon Realization Group ISQED 2012 March 20, 2012
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1 Taming the Challenges of Advanced-Node Design Tom Beckley Sr. VP of R&D, Custom IC and Signoff, Silicon Realization Group ISQED 2012 March 20, 2012
2 The custom design community Designers ( Relaxed attitude on physical rules and methodology) CAD Engineers (Not relaxed about rules. Whole different attitude, too) Cadence Design Systems, Inc. All rights reserved.
3 Agenda 1. Market trend and overview 2. The 20nm custom challenges 3. What do we need to do? 4. Open decisions: color and patterns 5. Summary Cadence Design Systems, Inc. All rights reserved.
4 Evolving industry custom design trend Mobility rules: very short time before next generation More connected devices per person: 6x in next 10 years Mobility is the driver and 20nm/14nm nodes will be key Expected 25-30% improvement in power consumption Desired 15-18% improvement in performance Predicted ~2x in density Cadence Design Systems, Inc. All rights reserved.
5 Challenge: investment in 20nm technology 32/28nm node 22/20nm node Breakeven 30-40M units Breakeven M units EDA Costs Finances mandate careful risk considerations Cadence Design Systems, Inc. All rights reserved.
6 Challenge: manufacturing complexity It s all new again compared to 28nm design Double patterning New transistors Layoutdependent effects 20nm Device variation New interconnect layers Difficult design rules Cadence Design Systems, Inc. All rights reserved.
7 Challenge: design enablement All the usual suspects are still present and causing trouble Cost And don t forget: Multi-source IP Mixed-signal and RF 3D-IC methods System-in-package Cadence Design Systems, Inc. All rights reserved.
8 Agenda 1. Market trend and overview 2. The 20nm custom challenges 3. What do we need to do? 4. Open decisions: color and patterns 5. Summary Cadence Design Systems, Inc. All rights reserved.
9 Double patterning technique A must-have at wire pitches smaller than 80nm Geometry features disappearing due to lithography distortion Enables printing of images below minimum spacing design rules w (64nm) (64nm) (64nm) Conventional Lithography Double Patterning (128nm+w) (128nm+w) Not feasible due to optical resolution limits Pitch between images is effectively doubled by printing alternately Cadence Design Systems, Inc. All rights reserved.
10 Double patterning problems It s easy to create design rule violations without even trying Two nets, colored for double pattern Create three wires Conflict created Re-colored conflict remains DPT DRC It isn t just a matter of flipping a shape THINK about the ripple effect throughout the entire design Cadence Design Systems, Inc. All rights reserved.
11 Layout-dependent effects at adv custom nodes Layout-dependent effects 45nm 32nm 20nm and below WPE Well proximity effect x x x PSE Poly spacing effect x X LOD Length of diffusion x X X OSE OD to OD spacing effect x X LPC Layout patterning check x x OP/PO Density OD/poly density X X Foundries insist that new verification standards are met by the customer prior to agreeing to manufacture Cadence Design Systems, Inc. All rights reserved.
12 LDE example: well proximity effect Threshold voltages aren t what they use to be V TH Distance to Well Now the layout is the design Additional physical effects: Shallow trench isolation Interconnect parasitics Dummy fill usage Lithography Cadence Design Systems, Inc. All rights reserved.
13 Increased device-rule complexity For custom design: ~4x new rules vs 90nm What we know so far: Total of about 5000 DRC checks for 20nm Double patterning alone requires checks Layout directional orientation rules Very specific rules governing L/W and varying transistor proximity New rules regarding legal interdigitation patterns 1 2 L 1 L 2 2 fingers in U-channel Cadence Design Systems, Inc. All rights reserved.
14 New routing layers (local interconnect / middle-of-line) Allows very dense local routing below 1st metal Local Interconnect (Li) layers are contactless metal layers that connect by shape overlap without need of a cut layer MOL Metal1 V0 Metal1 V0 Metal1 V0 Metal1 V0 Metal1 V0 Li2 LiPo Li2 Li2 LiPo Li2 Li1 Poly Li1 Li1 Li1 Active (-) Active (+) Active(+) Active (+) Nwell Li1 connects to Active LiPo connects to Poly Substrate Li2 connects Li1 to LiPo Substrate Cadence Design Systems, Inc. All rights reserved.
15 Agenda 1. Market trend and overview 2. The 20nm custom challenges 3. What do we need to do? 4. Open decisions: color and patterns 5. Summary Cadence Design Systems, Inc. All rights reserved.
16 What do we need to do? A mixture of tools and techniques New devices and tools New custom methodology Cadence Design Systems, Inc. All rights reserved.
17 New Devices and Tools
18 New 3D devices (FinFET, Tri-gate) Alternative to planar Planar FET Tri-gate, FinFET FinFET advantages: Smaller area (50%) Higher frequency (40%) Less power (up to 50%) Less leakage Higher drive current Noise and latch-up are minimized No reverse-biased diodes to substrate Tri-gate, FinFET Independent double-gate FinFET Cadence Design Systems, Inc. All rights reserved.
19 Extraction technology New structures necessitate more complex analysis Must address the growing electrical challenges plus unique structures in 20nm M1 V0 M1 V0 New: Fracture_vias Raised source/diffusion New parasitic structures for flash memories Double patterning requires more corner verification files STI Li1 Li2 RSD OD LiPo Poly STI Via fracturing for MOL routing Cadence Design Systems, Inc. All rights reserved.
20 DFM innovation: 100x faster than simulation Pattern-based litho hotspot identification Litho hotspot identified by simulation Printability Simulation automated layout analysis 2D Patterns Courtesy: From Cadence Webinar, DRC+ Now: Early DFM Signoff in the Digital Implementation Process Dr. Vito Dai, GLOBALFOUNDRIES Cadence Design Systems, Inc. All rights reserved.
21 New Custom Methodology
22 New custom methodology No more tossing over the wall Parasitic-Aware Design Schematic entry MODGEN creation Constraint entry Device placement SCHEMATIC Test creation and Initial simulations Rapid information exchange Net routing LAYOUT Pre-layout parasitic And LDE estimation In-design signoff Design centering Extraction Pre and post Layout comparisons Cadence Design Systems, Inc. All rights reserved.
23 Rapid layout prototyping Create layout building blocks for better electrical understanding P&R engine support for 20nm design rules Complex abutment rule support Local interconnect routing Array-based FinFET configurations Coloring higher-level abstraction Incremental device-level extraction LDE-aware device placement Cadence Design Systems, Inc. All rights reserved.
24 The key to speed: in-design signoff A requirement at 20nm design Design Platform Layout Seat In-design real-time signoff In Memory In-design batch signoff Std Interfaces Standalone signoff GOOD: Traditional standalone signoff using standard interfaces BETTER: Batch in-design signoff executing off in-memory data BEST: Dynamic in-design signoff tightly integrated into layout seat Cadence Design Systems, Inc. All rights reserved.
25 Agenda 1. Market trend and overview 2. The 20nm custom challenges 3. What do we need to do? 4. Open decisions: color and patterns 5. Summary Cadence Design Systems, Inc. All rights reserved.
26 Good pattern vs bad pattern matching An ounce of prevention is worth a pound of cure Today, it s all about finding and fixing but what if we could prevent in the first place? This pattern is DRC correct according to the minspacing rule, but what color is chosen? What color??? Cadence Design Systems, Inc. All rights reserved.
27 Good pattern vs bad pattern matching An ounce of prevention is worth a pound of cure This pattern is DRC correct according to the minspacing rule, but what color is chosen? Correction method: Split the shape and stitch back together making sure the overlap is sufficient tricky Cadence Design Systems, Inc. All rights reserved.
28 Good pattern vs bad pattern matching An ounce of prevention is worth a pound of cure This pattern is DRC correct according to the minspacing rule, but what color is chosen? Correction method: Split the shape and stitch back together making sure the overlap is sufficient tricky Build it right the first time by adding some extra space at the time of creation develop a larger pattern for the auto-router Cadence Design Systems, Inc. All rights reserved.
29 Other lingering manufacturing questions Each answer seems to raise five new questions Is DPT sufficient for 14nm? Will you need to move to MPT at 10nm? Use simultaneous ebeams for multi/double pattern? Will EUV ever be ready? What about Directed Self-Assembly (DSA)? Cadence Design Systems, Inc. All rights reserved.
30 Agenda 1. Market trend and overview 2. The 20nm custom challenges 3. What do we need to do? 4. Open decisions: color and patterns 5. Summary Cadence Design Systems, Inc. All rights reserved.
31 Where will the future take you? We can have more than Moore Industry collaboration New methodologies March 17, 2012 Andy Beckley; March Madness Ohio State vs Gonzaga tip-off in Pittsburgh; taken with Apple iphone 4s with dual core A5 processor; 40nm lowpower process. New tools Cadence Design Systems, Inc. All rights reserved.
32 Cadence 20nm solution Tools + ecosystem + methodology = design success Virtuoso Custom/Analog Encounter Digital Extraction and Simulation Cadence QRC and MMSIM Extraction Timing Power Cadence QRC, ETS, and EPS Physical verification for DRC and LVS (Cadence Physical Verification System) Design for Manufacturing (DFM) (Cadence Litho Physical Analyzer, CMP Predictor) ARM GLOBALFOUNDRIES IBM Samsung STMicroelectronics TSMC Cadence IP Custom Mixed Signal Variability 3D-IC Cadence Design Systems, Inc. All rights reserved.
33 Summary Measure early and often for first-pass success Mobility trends will continue to push the technology A combination of new tools, devices and methodologies will manage the complex physics Industry collaboration will be central to 20nm success 20nm is still evolving but don t let that stop you from the exploration Get ready 14nm will be upon us before you know it Cadence Design Systems, Inc. All rights reserved.
34 Cadence Design Systems, Inc. All rights reserved.
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