OpenDFM Targeting Functions. Bob Sayah June 6, 2011 IBM Corporation Si2 Targeting Working Group Chair

Transcription

1 OpenDFM Targeting Functions Bob Sayah June 6, 2011 IBM Corporation Si2 Targeting Working Group Chair

2 Targeting Design Drawn Shapes Mfg. Targeting Targeting takes the Drawn Shapes provided by the layout designer in the layout and turns them into the Target Shapes that manufacturing intends to achieve on the wafer. It does NOT include: OPC, etch bias, SRAFs and decomposition. These operations modify the Mask Shapes for the purposes of creating the intended wafer shapes which are Target Shapes. No Match Target Shapes Etch Comps, SRAFs, decomp, etc. Litho Target Shapes OPC Target Shapes represent what we intend to put on the wafer at the nominal process conditions 2 Match No Match Mask Shapes Mfg Processes On Wafer Geometries

3 Targeting The designer and PDK view Drawn Shapes Target Shapes At 20nm, what you draw is not what you get When the difference between the design shapes and target shapes is significant, the electrical performance of the circuit is impacted. Therefore, targeting modifications must be modeled, since they affect the extraction of both normal devices (MOSFETs) and all of the parasitic RLC devices. Technology Node Max % line width change N-2 28% N-1 56% N 75% N+1 100%??? 3

4 Question: Why Targeting? Answer: Capturing all of the requirements of the on-wafer shapes via design rules Increases Complexity or has unacceptable Lower Density. Example: Via Coverage Nested Line Ends vs. Isolated Line Ends During the patterning process (litho transfer) isolated line ends tend to foreshorten much more than nested line ends. We have several possible approaches for dealing with this context dependent behavior 1. Use a simple DRC rule which covers the worst case pattern Density 2. Obey several complex and context dependent DRC rules Complexity 3. OR use a simple DRC rule followed by a context dependent Targeting Function that optimally adjusts the drawn via cover. 4

5 Solution 1: Use a Simple DRC rule for the Worst Case This configuration needs more via coverage at the end of an isolated line. Line End Pull Back of an isolated line This configuration exhibits a nested pattern with less end of line pullback. If we add more metal coverage than necessary, it makes the density less competitive. 5

6 Solution 2: Use Complex, Context Dependent DRC rules Rule 5XXa applies; if there is no passing line Rule 5XXc applies; if there is a passing line and no adjacent lines Rule 5XXb applies; if there is a passing line and adjacent lines DRC complexity increases due to: Increase in the number of rules Increase in complexity of each rule Hand layout takes longer to craft when multiple rules must be obeyed Routers struggle with new, complex rules 6

7 Solution 3: Use Simple DRC Rules followed by Targeting Draw the simple DRC rule Use the Targeting Rule: adjust_eol_via_cover Create a via cover that exactly matches the available space All three configurations are drawn exactly the same way. All three follow a simple DRC rule, resulting in both faster layout and much simpler DRC checks Simple DRC Rule + Targeting is the best solution 7 Targeting adds the context specific via covers as seen within the dotted line area.

8 adjust_eol_via_cover() The targeting function adjusts the sides of the via cover to increase the metal overlap of via when any economy of space exists 8 Example from OpenDFM v1.1 documentation Adjust EOL Via Cover Function has more than a dozen parameters to define it 8

9 More Targeting examples using litho_bias functions Sub resolution litho requirements are difficult to capture in design rules Lithography requires complex width-dependent spacing and spacingdependent width rules. Extra rules/exceptions necessary for dealing with 2D structures. Environment-specific layout rules lead to a breakdown of the useful hierarchical design methodologies we have used for decades Wires inside of a cell may be isolated in the context of one instance but heavily nested in the context of another instance It is undesirable to produce multiple physical implementations of the same layout just because of the differences of its local environment. 9

10 Lithographic simulation of drawn layout Bridging concerns Pinching concerns Wider Process Variation Bands Greater line width variation across the process window 10

11 Modified layout from OpenDFM litho_bias function Widening of isolated and semiisolated lines Litho Bias targeting operation is applied before the actual OPC operation to provide a better target for OPC 11

12 Litho contours of Modified layout show Improvement No longer any pinching or bridging concerns Narrower PV Bands Less line width variation over the process window 12

13 Silicon Foundry A Of course, our DRM has an official description of Targeting But how do I make sure that all of the different implementations are exactly the same? Official Design Rule Manual Silicon Foundry B DRC Sign-off List DRC Sign-off List DRC Sign-off List DRC Sign-off List Proprietary Input Language Proprietary Input Language Proprietary Input Language Proprietary Input Language PEX Engine A PEX Engine B PEX Engine C PEX Engine D 13

14 Targeting implementation using OpenDFM TCL (OpenDFM) Source Code Device Length Adj Line Width Adj. Via Map/Restep Defined in the design manual, implemented as the OpenDFM program Open Community TCL Parser Provided by Si2 EDA Vendor Proprietary Manufacturing Vendor X Vendor Y Vendor Z Data Prep Targeting Deck Vendor X Targeting Deck for PDK Vendor Y Targeting Deck for PDK Vendor Z Targeting Deck for PDK 14

15 Extending the extraction flow to account for Targeting Design Oasis / GDS Targeting operations generated by OpenDFM translation Device recog., Connectivity, LVS compare, annotation Extraction extracted netlist Schematic Netlisting 15

16 The OpenDFM approach has Multiple Advantages For the Designer: Conforming targeting specifications to standardized functionality leads to better agreement of results between design and manufacturing. For the PDK developer: A single OpenDFM program can drive the creation of multiple implementations in multiple EDA vendor tools. For the EDA tool vendor: Owning the implementation assures the following of best practices for optimal tool performance. 16

17 Summary Targeting reduces design rule complexity while achieving higher layout densities As the complexity of manufacturing technology increases, the relative electrical impact of targeting operations is increasing even faster Standardizing on a set of targeting operations via OpenDFM Improves the agreement between extracted parameters and onwafer dimensions Reduces the opportunity for human error during PDK development Reduces PDK development time, especially when supporting multiple vendor extraction tools. 17

18 Thanks Jake Buurma, Si2 DFMC Program Director Jim Culp, IBM DFMC Chair Matthew Graf, Cole Zemke, Arnie Baizley IBM PDK development Cathy Rodgers, Louis Schaffer and their team at Synopsys David Abercrombie and his team at MGC All Si2 DFMC and Targeting Working Group Members 18

19 19