Xylem: Enhancing Vertical Thermal Conduction in 3D Processor-Memory Stacks

Transcription

1 Xylem: Enhancing Vertical Thermal Conduction in 3D Processor-Memory Stacks Aditya Agrawal, Josep Torrellas and Sachin Idgunji University of Illinois at Urbana Champaign and Nvidia Corporation MICRO, October 2017

2 Xylem 2 Image source:

3 Motivation: Thermal Issues in 3D Stacking Processor-Memory Stacks: Reduced interconnect length and power Higher memory bandwidth Smaller form factors Heterogeneous integration 2.5D processor-memory stacks exist 3D processor-memory stacking is the future Major challenge: Thermals 3

4 TSV TTSV Lower Die (Back) 2 μm 20 μm 2 μm Upper Die (Face) TTSV TSV 3D Stacking Technologies Silicon Devices M1 Mn Frontside Metal Layers Electrical μbump BM1 Dummy μbump Backside Metal Layers D2D Layer Silicon Face-to-back (f2b) die interface (not to scale) 4

5 Stack Organization: Memory on Top Processor power and I/O signals do not traverse TSVs Processor IR drop similar to current designs DRAM and processor die floorplans are independent because TSV count and location are governed by stacked DRAM standards Thermal challenges Heat Sink Integrated Heat Spreader (IHS) Thermal Interface Material (TIM) DRAM Silicon Die to Die (D2D) Layer DRAM Frontside Metal (Al) Through Silicon Vias (TSVs) Processor Silicon Processor Frontside Metal (Cu) C4 pads Package 5

6 Contributions Identify the thermal bottleneck in 3D stacks: Die-to-Die(D2D) layers Improve vertical conduction through the D2D layer: Align and short dummy μbumps with Thermal TSVs Generic and custom TTSV placement schemes Use the resulting thermal headroom: Boost processor frequency ( MHz) & performance (11-18%) Exploit thermal heterogeneity: cores closer to TTSVs conduct heat better Conductivity-aware thread placement and migration, and frequency boosting 6

7 Thermal resistance per unit area: Thermal Resistance in the Stack Layer R th (mm 2 -K/W) Bulk Silicon 0.83 Proc. Metal 1.00 D2D D2D layer is 13-16x more resistive than bulk silicon or metal layers 7

8 Shortcomings of Prior Work Underestimated the thermal resistance of D2D layer by assuming: High conductivity Small thickness Focused on increasing the conductivity of the bulk silicon using TTSVs Concluded that TTSVs alone are effective Our approach: Combine TTSVs with a mechanism to reduce D2D resistance 8

9 Lower Die (Back) D2D Lower Die (Back) D2D Upper Die (Face) Upper Die (Face) Propose: Dummy μbump-ttsv Alignment & Shorting Before Proposed TTSV Silicon Frontside Metal Layers Frontside Metal Layers TTSV Silicon Dummy μbump Underfill Dummy μbump Underfill TTSV Silicon Backside Metal Layers Backside Metal Layers TTSV Silicon 9

10 TTSV Placement: Constraints TTSVs: Cannot disrupt regular DRAM arrays: Place in the DRAM peripheral logic Distribute TTSVs and avoid TTSV farms Maintain Keep Out Zone (KOZ) around each TTSV Dummy μbumps: Anywhere in the D2D layer except the electrical μbump locations 10

11 IL1 Core 5 DL1 IL1 Core 6 DL1 DL1 Core 7 IL1 DL1 Core 8 IL1 IL1 Core 1 DL1 IL1 Core 2 DL1 DL1 Core 3 IL1 DL1 Core 4 IL1 DRAM and Processor Baseline Floorplans TSV Bus L2 L2 L2 L2 Memory Controllers Coherent Bus Logic L2 L2 L2 L2 TSV Bus Bank DRAM (Wide IO) die floorplan Processor die floorplan 11

12 Proposal: TTSV Placement Schemes TTSV TSV Bus TTSV TSV Bus Bank Bank Generic (oblivious to hotspots) Custom (aligned with hotspots) 12

13 Proposal: Frequency Boosting TTSV placement & TTSV-μbump alignment and shorting: Increases thermal conduction from the processor die to the heat sink Reduces the temperature of the processor die Proposal: Increase processor frequency to consume the thermal headroom Increase application performance 13

14 Proposal: Conductivity (λ) Aware Techniques TTSV-μbump alignment and shorting creates high conductivity paths Areas closer to TTSVs dissipate heat more easily Result is thermal spatial heterogeneity in the stack Proposal: Three λ-aware optimizations to further improve performance λ-aware thread placement λ-aware frequency boosting λ-aware thread migration 14

15 Evaluation Setup 8-core OoO processor 2.4 GHz 8 high Wide IO memory on top Processor timing and power: SESC & McPAT DRAM timing and power: DRAMSim2 Thermal analysis: 3D HotSpot Applications: SPLASH-2, PARSEC & NAS Memory-on-top configuration Heat Sink IHS TIM DRAM Silicon D2D Layer DRAM Metal TSVs Proc. Silicon Proc.Metal C4 pads Motherboard 15

16 Result Summary TTSV Placement Generic Custom Area Overhead 0.63% 0.81% Proc. Temp. Reduction 5.0 o C 8.4 o C Avg. Frequency Boost 400 MHz 720 MHz Avg. Performance Gain 11% 18% λ-aware techniques enable further MHz improvements 16

17 Conclusion Identified that D2D layer is the thermal bottleneck in 3D stacks Improved vertical conduction through the D2D layer: Align and short dummy μbumps with TTSVs Generic and custom TTSV placement schemes Used the resulting thermal headroom to Boost processor frequency ( MHz) & performance (11-18%) Exploited thermal heterogeneity: cores closer to TTSVs conduct heat better Conductivity-aware thread placement and migration, and frequency boosting Enable further MHz improvements 17

18 Xylem: Enhancing Vertical Thermal Conduction in 3D Processor-Memory Stacks Aditya Agrawal, Josep Torrellas and Sachin Idgunji University of Illinois at Urbana Champaign and Nvidia Corporation 18