Stacked IC Analysis Modeling for Power Noise Impact

Transcription

1 Si2 Open3D Kick-off Meeting June 7, 2011 Stacked IC Analysis Modeling for Power Noise Impact Aveek Sarkar Vice President Product Engineering & Support

2 Stacked IC Design Needs Implementation Electrical-, thermal-, and mechanical-aware design Power impact: power consumed, dissipated and noise generated Cross-domain/organization/ company collaboration Inter-die thermal interplay Verification - Exploration and planning - Analysis, optimization and sign-off Apache Design Solutions

3 Stacked IC Design Needs: Analysis Approaches Power Model based Compact, IP protection Simplified and open format Thermal ESD Signal Concurrent Simultaneous analysis Multiple layout/result display Apache Design Solutions

4 Apache s Comprehensive Power Analysis & Optimization Solutions Architecture Intellectual Property System-on-Chip Package System (PCB) Power Budgeting Ultra-low-power Methodology Power Delivery Integrity IP Integration, SoC Sign-off Power Induced Noise Immunity Chip-Package-System Convergence Apache Design Solutions

5 Apache Technologies for Stacked Die Analysis Power noise Full layout detail or model based multi-die simulations Support for IR / EM / DvD / Low power Support for TSV and copper pillar models Thermal - Integrated thermal analysis for stacked die - Feedback to RedHawk/Totem for EM and leakage estimation - Thermal model generation for system simulation Apache Design Solutions

6 Concurrent setup Stacked IC Design Needs: Analysis Apache Model based setup Apache Design Solutions Singh et al, Design and optimization of a power delivery network for 3D stacked die designs, DesignCon 2011, submitted

7 Stacked IC Design PI Analysis Results so Far Comparing concurrent versus model based Concurrent analysis: Voltage drop on both dies Apache Design Solutions Singh et al, Design and optimization of a power delivery network for 3D stacked die designs. DesignCon 2011, submitted

8 Model Requirements for Stacked Die Analysis Contain self-consistent electrical data Enable seamless connections to other models or to chip/interposer layout Be in open (e.g. Spice) format Simplified topology to enable analysis Die 1 Die 2 Interposer Package Power estimation Power noise: DC and time-domain Impedance analysis (frequency/dc) Reliability analysis (EM, ESD) Similar or integrated model for thermal Contain technology / design parameters Die 1 Model Die 2 Layout Interposer Layout Package netlist (RLCK / S-parameter) Apache Design Solutions

9 Model Based Stacked Die Analysis Data Content Parasitic of the PDN network (feed-throughs or shared networks) Provide RLC parasitic information for PDN IR, EM, dynamic noise Frequency domain analysis of stacked die Power signature at the ports of the die Domain specific Used for power estimation Stacked die IR, EM, dynamic noise calculation Thermal model Separate model (?) Power vs Temperature Metal density, etc Apache Design Solutions

10 Model Based Stacked Die Analysis Self-Consistency of Model Full layout based analysis Model based analysis IC Model (e.g. CPM) e.g. using RedHawk e.g. using Spice Sarkar, System level power distribution noise closure: Looking beyond the SoC power integrity challenge. DAC Apache Design Solutions

11 CIP Header Model Based Stacked Die Analysis Interface Protocol Needs S/P DMA uc RAM Die Model with Chip Interface Protocol (CIP) Die 1 Model Die 2 Layout Interposer Layout DSP ASIC Package netlist (RLCK / S-parameter) Detailed Chip Layout Streamlined import and hookup Define model creation options (static, dynamic VCD/V-less) Define content for stacked die power analysis (estimation, drop, ) Apache Design Solutions

12 Model Based Stacked Die Analysis Interface Protocol Needs Die 3 Die 2 Chip Interface Protocol (CIP) Chip Interface Protocol (CIP) Die 1 Chip Interface Protocol (CIP) (also to package modeling tools) Package Apache Design Solutions

13 Model Based Stacked Die Analysis Interface Protocol Needs Die 1 Die 2 Chip Interface Protocol (CIP) Chip Interface Protocol (CIP) Interposer Chip Interface Protocol (CIP) (also to package modeling tools) Package Apache Design Solutions

14 Model Based Stacked Die Analysis Interface Protocol Requirements Goal Global parameters Pin Specific Parameters Enables Chip Model to connect to: Die/interposer (layout or model with CIP) Package layout tool Package model (with PCP) Protocol type / version Tool used / version Reference designator (or unique part name) Unit definition Pad type (WB/FC) Chip information (tech/type/pvt) Options used to generate model, activity used, etc Half-node scaling factor Pad name Pad type (P, G, S) Pad location Pad landing metal Node name Net name Grouping Port type (die2die, die2pkg, internal) Apache Design Solutions

15 Next Steps Define first draft of CIP definition to Open3D group Contact Aveek for feedbacks Initiate discussion Apache Design Solutions 6/17/2011, 15