Congestion-Aware Power Grid. and CMOS Decoupling Capacitors. Pingqiang Zhou Karthikk Sridharan Sachin S. Sapatnekar

Transcription

1 Congestion-Aware Power Grid Optimization for 3D circuits Using MIM and CMOS Decoupling Capacitors Pingqiang Zhou Karthikk Sridharan Sachin S. Sapatnekar University of Minnesota 1

2 Outline Motivation A new CAD solution to 3D power grid optimization Experimental results Summary 2

3 3D IC Design Detailed view Generalized view Interlayer Via Layer 5 Inter-layer bonds Layer 4 Layer 3 Layer 2 Metal level of wafer 1 Layer 1 Device level 1 Bulk Substrate SOI wafers with bulk substrate removed 1m Bulk wafer 10m 500m Adapted from [Das et al., ISVLSI, 2003] by B. Goplen 3

4 3D Integration: Driving forces Improved global interconnect performance Reduce footprint / improve packing density al. 1998] [Al-Sarawi et Mixed-signal integration 4

5 Power Supply Integrity in 3D Higher current density, faster current transients worsen supply noise Greater challenge in 3D due to via resistance, limited number of supply pins Pins 2D 3D per Power Pin (m ma) Current Current The Trend per of Current power per pin Power (2D) Pin from ITRS Power bottleneck: a major problem for 3D Year 3D Circuit [IBM] 5

6 Traditional power delivery Requirements V dd, GND signals should be at correct levels (low V drop) Electromigration constraints Current density must never exceed a specification For each wire, I i /w i < J spec di/dt constraints Need to manage di/dt to reduce inductive effects Techniques for meeting constraints Widening wires Using appropriate topologies Adding decoupling capacitances Already challenged for 2D technologies Reliable power delivery hard Decaps get leaky New CAD approaches necessary 6

7 Decoupling capacitances (decaps) The most powerful method to reduce transient noise Conventional decap technology: CMOS decap New considerations for CMOS decaps in 3D Compete for area on device layer with landing pads of 3D vias May increase footprint size Get more leaky, due to T-leakage feedback Block CMOS decap Any other option? 7

8 MIM decaps rts 2005] [Rober Decap *Capacitance *Leakage density Congestion density (ff/µm 2 ) (A/cm 2 ) CMOS e-4 - MIM e-8 routing blockage * Numbers deduced from Roberts et al., IEDM05 and PTM simulations 8

9 Our Contributions Apply newer decap technology - MIM decap Develop CAD solutions for inserting both MIM and CMOS decaps: Sequence of linear progamming based problem formulation Linearized noise model based on adjoint sensitivity analysis 3D congestion analysis and linear congestion model 9

10 Overall Algorithm Flow Initial setup 3D layout info. Build 3D power grid Technology parameters Transient power grid analysis Optimization i loop Noise metric S 0? NO Stop YES LP based allocation of CMOS and MIM decaps 10

11 Power network modeling and analysis Power Network Modeling + Modified Nodal Analysis G x(t) + C x (t) = b(t) - x(t): time varying vector of voltages and currents - b(t): () time varying vector of independent current sources Adjoint Sensitivity Analysis - Based on Tellegen s theorem: the instantaneous power in any circuit is zero - An approach to calculate l the sensitivity i i of one objective function w.r.t all the parameters in the circuit 11

12 Power Noise Metric S Noise: optimize the integral of noise violation over time s(j) V j + 0 t Waveform of node j on VDD grid te S( j) 1 ( vth v j (, p)) dt ts S S ( j ) j 12

13 Decap optimization: problem formulation Noise metric minimize α S(x k, y k ) + (1-α) P(x k, y k ) subject to 0 x k C 0 y C k CMOS k MIM Congestion in grid k 1 -x k : CMOS decap added to grid k -y k : MIM decap added to grid k k Leakage power Decap resource constraint Congestion constraint Grid k Nonlinear optimization problem! 13

14 Sequence of linear programs: formulation Objective min α S + (1-α) P S = k (a k x k +b k y k ) = change of violation area S P = k (c k x k +d k y k ) = change in leakage x k : Newly added CMOS decap to grid k y k : Newly added MIM decap to grid k Constraints Congestion constraint Cong Cong k Decap resource constraint k 0x min{, C } k CMOS CMOS k 0y min{, C } k MIM MIM k Grid k 14

15 Congestion Analysis and Linear Model 3D congestion analysis - Extension of Estimation routing congestion using probabilistic analysis, [Lou, et al. TCAD 02]. F( p, q, r) F( p 1, q, r) F( p, q 1, r) F( p, q, r 1) F( p,1,1) F(1, q,1) F(1,1, r) 1 Linear congestion model W k i k k k i R k, i k Cap k, Cong ( ) y ir k ( y ) - y i : the small MIM decap added to grid i i i Grid Gidkk - w k,i : the # of routes moved out of grid i to grid k caused by y i - Cap i : the capacity of grid k [Details in the paper] R k Grid i 15

16 90nm technology node 6 metal layers for each 2D tier Supply voltage: 1.2 V Experimental Setup Voltage drop threshold: 0.12 V (10%) 3D Benchmarks Ckt # Nodes Worst V droop (V) # nodes with noise violations Violation Area S (V ns) Ibm123 18, Ibm05 12, ibm08 17, ibm10 29, ibm18 75,

17 Experimental Results Comparison of three optimization strategies Ckt CMOS only MIM only CMOS + MIM VNs S (V ns) Lkg (ma) Decap (pf) maxc (%) avgc (%) Decap (pf) Lkg (ma) maxc (%) avgc (%) Decap (pf) Ibm Ibm ibm ibm ibm VNs: number of violating nodes - Lkg: leakage current - maxc: maximum increment of congestion - avgc: average increment of congestion CMOS+MIM can achieve a good tradeoff between leakage power and routing congestion 17

18 Experimental results: ibm18 (cont.) Violation Area 5 0 log10 (S) CMOS MIM CMOS+MIM Iteration number Leakage Leakage cur rrent (ma) CMOS CMOS+MIM MIM Iteration number 18

19 Experimental Results (cont.) Optimization results of power grid densities Cases Power #Nodes # nodes Worst V Violation Decap Lkg maxc avgc Time Grid with noise droop Area S (pf) (ma) (%) (%) (s) Density violations (V) (V ns) Case1 Normal Case2 Denser Case3 Densest Lkg: leakage current - maxc: maximum increment of congestion - avgc: average increment of congestion 1. Denser power grid smaller voltage droop 2. Denser power grid increased congestion 19

20 Summary Power delivery into a 3D chip is a critical problem for next-generation designs MIM decap is an efficient option for 3D power grid optimization A LP based decap allocation approach using both MIM and CMOS decaps Our algorithm can also be used to solve the 2D power grid optimization problem 20

21 Thank You! 21