EECS150. Implement of Processor FSMs

Transcription

1 EECS5 Section Controller Implementations Fall Implement of Processor FSMs Classical Finite State Machine Design Divide and Conquer Approach: Time-State Method Partition FSM into multiple communicating FSMs Exploit MSI Functionality: Jump Counters Counters, Multiplexers, Decoders Microprogramming: ROM-based methods Direct encoding of next states and outputs EECS5 - Fall -

2 Processor / Memory Interface Problem: The processor and memory often do not share the same clock. Solution: Use appropriate handshaking EECS5 - Fall -3 Moore RES Reset PC IF PC MAR, PC + PC Note capture of MBR in these states IF IF MAR Mem, Read/Write, Request, Mem MBR IF3 MBR IR OD LD LD LD = = IR MAR ST IR MAR, AC MBR MAR Mem, Read/Write, ST Request, Mem MBR MBR AC MAR Mem, Read/Write, Request, MBR Mem = AD AD AD = IR MAR MAR Mem, Read/Write, Request, Mem MBR MBR + AC AC BR = BR = IR PC EECS5 - Fall -4

3 Memory-Register Interface Timing IF IF IF IF IF3 CLK WAIT Mem Bus Data Valid Latch MBR Invalid Data Latched Invalid Data Latched Valid Data Latched Valid data latched on IF to IF3 transition because data must be valid before Wait can go low EECS5 - Fall -5 Processor Signal FLow EECS5 - Fall -6

4 Moore Machine Diagram Reset Wait IR<5> IR<4> AC<5> Clock Next State Logic State 6 states, 4 bit state register Next State Logic: 9 Inputs, 4 Outputs Output Logic: 4 Inputs, 8 Outputs Output Logic Read/Write Request PC PC + PC PC ABUS IR ABUS ABUS MAR ABUS PC MAR Memory Address Bus Memory Data Bus MBR MBR Memory Data Bus MBR MBUS MBUS IR MBUS ALU B MBUS AC RBUS AC RBUS MBR ALU ADD These can be implemented via ROM or PAL/PLA Next State: 5 x 4 bit ROM Output: 6 x 8 bit ROM EECS5 - Fall -7 Moore Machine State Table Reset Wait IR<5> IR<4> AC<5> Current State Next State Register Transfer Ops X X X X X RES () X X X X RES () IF () PC X X X X IF () IF () PC MAR, PC + PC X X X IF () IF () X X X IF () IF () X X X IF () IF () MAR Mem, Read, X X X IF () IF3 () { Request, Mem MBR X X X IF3 () IF3 () MBR IR X X X IF3 () OD () X X OD () LD () X X OD () ST () X X OD () AD () X X OD () BR () X X X X LD () LD () IR MAR X X X LD () LD () MAR Mem, Read, X X X LD () LD (){ Request, Mem MBR X X X X LD () IF () MBR AC X X X X ST () ST () IR MAR, AC MBR X X X ST () ST () MAR Mem, Write, X X X ST () IF (){ Request, MBR Mem X X X X AD () AD () IR MAR X X X AD () AD () MAR Mem, Read, X X X AD () AD (){ Request, Mem MBR X X X X AD () IF () MBR + AC AC X X X BR () IF () X X X BR () BR () X X X X BR () IF () IR PC EECS5 - Fall -8

5 Observations: State Transition Table Extensive use of Don't Cares Inputs used only in a small number of state e.g., AC<5> examined only in BR state IR<5:4> examined only in OD state Some outputs always asserted in a group ROM-based implementations cannot take advantage of don't cares However, ROM-based implementation can skip state assignment step EECS5 - Fall -9 Synchronous Mealy Machines Standard Mealy Machine has asynchronous outputs These change in response to input changes, independent of clock Revise Mealy Machine design so outputs change only on clock edges One approach: non-overlapping clocks Synchronizer Circuitry at at Inputs Inputs and and Outputs A D Q A' ƒ D Q ƒ' Output Logic STATE A STATE A STATE A' ƒ D Q Output Logic Output Logic EECS5 - Fall - ƒ D Q ƒ'

6 Synchronous Mealy Machines Case I: Synchronizers at Inputs and Outputs CLK A A' cycle cycle cycle S S A/ƒ ƒ ƒ' S A asserted in Cycle, ƒ becomes asserted after cycle delay! This is clearly overkill! EECS5 - Fall - Synchronous Mealy Machine Case II: Synchronizers on Inputs CLK cycle cycle cycle S A/ƒ S A S S A' A'/ƒ ƒ A asserted in Cycle, ƒ follows in next cycle Same as using delayed signal (A') in Cycle! EECS5 - Fall -

7 Synchronous Mealy Machines Case III: Synchronized Outputs CLK A ƒ cycle cycle cycle S S A/ƒ ƒ' A asserted during Cycle, ƒ' asserted in next cycle Effect of ƒ delayed one cycle EECS5 - Fall -3 Synchronous Mealy Machines Implications for Processor FSM Already Derived Consider inputs: Reset, Wait, IR<5:4>, AC<5> Latter two already come from registers, and are sync'd to clock Possible to load IR with new instruction in one state & perform multiway branch on opcode in next state Best solution for Reset and Wait: synchronized inputs Place D flipflops between these external signals and the control inputs to the processor FSM Sync'd versions of Reset and Wait delayed by one clock cycle EECS5 - Fall -4

8 Time State Divide and Conquer Overview Classical Approach: Monolithic Implementations Alternative "Divide & Conquer" Approach: Decompose FSM into several simpler communicating FSMs Time state FSM (e.g., IFetch, Decode, Execute) Instruction state FSM (e.g., LD, ST, ADD, BRN) Condition state FSM (e.g., AC <, AC ) EECS5 - Fall -5 Time State (Divide & Conquer) Time State FSM Most instructions follow same basic sequence Differ only in detailed execution sequence Time State FSM can be parameterized by opcode and AC states Instruction State: stored in IR<5:4> Condition State: stored in AC<5> = = IR = = LD ST ADD BRN AC<5>= AC BRN + (ST Wait)/ (LD + ADD) Wait AC < T7 AC<5>= EECS5 - Fall -6 T T T T3 T4 T5 T6 BRN AC / (LD + ST + ADD)

9 Time State (Divide & Conquer) Generation of Microoperations PC: Reset PC + PC: T PC MAR: T MAR Memory Address Bus: T + T6 (LD + ST + ADD) Memory Data Bus MBR: T + T6 (LD + ADD) MBR Memory Data Bus: T6 ST MBR IR: T4 MBR AC: T7 LD AC MBR: T5 ST AC + MBR AC: T7 ADD IR<3:> MAR: T5 (LD + ST + ADD) IR<3:> PC: T6 BRN Read/Write: T + T6 (LD + ADD) Read/Write: T6 ST Request: T + T6 (LD + ST + ADD) EECS5 - Fall -7 Jump Counter Concept Implement FSM using MSI functionality: counters, mux, decoders Pure jump counter: only one of four possible next states N HOLD LOAD CLR CNT N+ XX Single "Jump State" function of the current state Hybrid jump counter: Multiple "Jump States" function of current state + inputs EECS5 - Fall -8

10 Jump Counters Pure Jump Counter Inputs Count, Load, Clear Logic Clear Load Count CLOCK Jump State Logic Synchronous Counter State Register NOTE: No inputs to jump state logic Logic blocks implemented via discrete logic, PALs/PLAs, ROMs EECS5 - Fall -9 Jump Counters Problem with Pure Jump Counter Difficult to implement multi-way branches OD 4 OD Extra States: 5 8 OD BR LD ST AD BR Logical State Diagram 6 OD 9 AD 7 LD ST Pure Jump Counter State Diagram EECS5 - Fall -

11 Jump Counters Hybrid Jump Counter Inputs Count, Load, Clear Logic Clear Load Count CLOCK Jump State Logic Synchronous Counter State Register Load inputs are function of state and FSM inputs EECS5 - Fall - Jump Counters Implementation Example Reset RES IF IF State assignment attempts to take advantage of sequential states IF OD 3 4 LD 5 ST 8 AD BR 3 LD 6 ST 9 AD LD 7 AD EECS5 - Fall -

12 Jump Counters Implementation Example, Continued CNT = (s + s5 + s8 + s) + Wait (s + s3) + Wait (s + s6 + s9 + s) CNT = Wait (s + s3) + Wait (s + s6 + s9 + s) CLR = Reset + s7 + s + s3 + (s9 Wait) CLR = Reset s7 s s3 (s9 + Wait) LD = s4 Contents of Jump State ROM Address Contents (Symbolic State) (LD) (ST) (AD) (BR) EECS5 - Fall -3 Jump Counters Implementation Example, continued /S9 Wait Wait /S /S9 /S6 /S3 /S /S OR IR5 IR4 /Reset /S7 /S /S3 Cnt PAL Wait S S9 S6 HOLD S3 S S Jump State IR<5> IR<4> AND 3 CNT /S4 7 P T CLK 6 D 5 C B A LOAD CLR Implement CNT using active lo PAL 63 5 RCO QD QC QB 3 QA 4 /Reset Wait /Wait NOTE: Active lo Implement CLR outputs from EECS5 - Fall decoder G G D C B 3 A /S5 /S4 /S3 /S /S /S /S9 /S8 /S7 /S6 /S5 /S4 /S3 /S /S /S

13 Jump Counter CLR, CNT, LD implemented via Mux Logic CLR = CLRm + Reset CLR = CLRm + Reset /CLRm /Reset Reset Wait /CLR Jump State IR5 IR<5> 3 IR4 IR<4> /Reset /Wait CNT /LD /CLR P T CLK D C B A LOAD CLR 63 RCO QD QC QB QA 54 G G D C B A \S3 \S \S \S \S9 \S8 \S7 \S6 \S5 \S4 \S3 \S \S \S Active Lo outputs: hi input inverted at the output Note that CNT is active hi on counter so invert MUX inputs! S3 S S S G E5 5 E4 + E3 + E E E E9 E8 E7 E6 E5 E4 E3 Wait E /Wait E E S3 S S S G G E5 5 E5 5 E4 E4 E3 E3 E E E E E E /Wait E9 E9 EOUT E8 E8 EOUT CNT /CLRm EOUT E7 E6 E5 E4 E3 E E E + S3 S S S E7 E6 E5 E4 E3 E E E /LD EECS5 - Fall -5 Jump Counters Microoperation implementation PC = Reset PC + PC = S PC MAR = S MAR Memory Address Bus = Wait (S + S + S5 + S6 + S8 + S9 + S + S) Memory Data Bus MBR = Wait (S + S6 + S) MBR Memory Data Bus = Wait (S8 + S9) MBR IR = Wait S3 MBR AC = Wait S7 AC MBR = IR5 IR4 S4 AC + MBR AC = Wait S IR<3:> MAR = (IR5 IR4 + IR5 IR4 + IR5 IR4) S4 IR<3:> PC = AC5 S3 Read/Write = Wait (S + S + S5 + S6 + S + S) Read/Write = Wait (S8 + S9) Request = Wait (S + S + S5 + S6 + S8 + S9 + S + S) Jump Counters: CNT, CLR, LD function of current state + Wait Why not store these as outputs of the Jump State ROM? Make Wait and Current State part of ROM address 3 x as many words, 7 bits wide EECS5 - Fall -6

14 Branch Sequencers Concept Implement Next State Logic via ROM Address ROM with current state and inputs Problem: ROM doubles in size for each additional input Note: Jump counter trades off ROM size vs. external logic Only jump states kept in ROM Even in hybrid approach, state + input subset form ROM address Branch Sequencer: between the extremes Next State stored in ROM Each state limited to small number of next states Always a power of Observe: only a small set of inputs are examined in any state EECS5 - Fall -7 Branch Sequencers I n p u t s 4 Way Branch Sequencer Mux Mux β α a a a a3 a4 a5 x x x x 64 Word ROM Z Y X W C S o i n g t n r a o l l s N α β α β α β α β W X Y Z state Current State selects two inputs to form part of ROM address These select one of four possible next states (and output sets) Every state has exactly four possible next states EECS5 - Fall -8

15 Branch Sequencer Processor CPU Design Example s<3> s<> s<> s<> S3 S S S G E5 E4 AC<5> E3 AC<5> E E E E9 E8 EOUT E7 \α E6 E5 IR<5> E4 IR<4> E3 E + Wait E Wait E + S3 S S S 5 E5 5 G E4 E3 E E E E9 E8 E7 E6 E5 E4 E3 E E E EOUT Alpha, Beta multiplexer input setup EECS5 - Fall -9 \β Example Processor FSM ROM ADDRESS ROM CONTENTS (Reset, Current State, a, b) Next State Register Transfer Operations RES X X (IF) PC MAR, PC + PC IF (IF) (IF) MAR Mem, Read, Request IF (IF) MAR Mem, Read, Request (IF) Mem MBR IF (IF) (OD) MBR IR OD (LD) IR MAR (ST) IR MAR, AC MBR (AD) IR MAR (BR) IR MAR LD X X (LD) MAR Mem, Read, Request LD (LD) Mem MBR (LD) MAR Mem, Read, Request LD X X (RES) MBR AC ST X X (ST) MAR Mem, Write, Request, MBR Mem ST (RES) (ST) MAR Mem, Write, Request, MBR Mem AD X X (AD) MAR Mem, Read, Request AD (AD) (AD) MAR Mem, Read, Request AD X X (RES) MBR + AC AC BR (RES) (RES) IR PC EECS5 - Fall -3

16 Branch Sequencers α and β MUX Control Alternative Horizontal Implementation α β α β α β α β A A A A3 n- n- n- n- Datapath Control Signals I N P U T S M U M X U X α β bit n : MUX 4: MUX bit bit n bit state register Input MUX controlled by encoded signals, not state Much fewer inputs than unique states! In example FSM, input MUX can be :! Adding length to ROM word saves on bits vs. doubling words Vertical format: (4 + 4) x 64 = 5 ROM bits Horizontal format: (4 + 4 x 4 + ) x 6 = 5 ROM bits EECS5 - Fall -3 Microprogramming How to organize the control signals Implement control signals by storing 's and 's in a ROM Horizontal vs. vertical microprogramming Horizontal: ROM output for each control signal Vertical: encoded control signals in ROM, decoded externally some mutually exclusive signals can be combined helps reduce ROM length EECS5 - Fall -3

17 Microprogramming Register Transfer/Microoperations 4 Register Transfer operations become Microoperations: PC ABUS IR ABUS MBR ABUS RBUS AC AC ALU A MBUS ALU B ALU ADD ALU PASS B MAR Address Bus MBR Data Bus ABUS IR ABUS MAR Data Bus MBR RBUS MBR MBR MBUS PC PC + PC ABUS PC Read/Write Request AC RBUS ALU Result RBUS EECS5 - Fall -33 Horizontal Microprogramming Horizontal Branch Sequencer α, β Mux bits 4 x 4 Next State bits Control operation bits 4 bits total α mux β mux Next States A A A A3 PC ABUS IR ABUS MBR ABUS RBUS AC AC ALU A MBUS ALU B ALU ADD ALU PASS B MAR Address Bus MBR Data Bus ABUS IR ABUS MAR Data Bus MBR RBUS MBR MBR MBUS PC PC + PC ABUS PC Read/Write Request AC RBUS ALU Result RBUS EECS5 - Fall -34

18 Horizontal Microprogramming Moore Processor ROM Current State (Address) RES () IF () IF () IF () IF3 () OD () LD () LD () LD () ST () ST () AD () AD () AD () BR () BR () α mux β mux Next States A A A A3 Alpha inputs: = Wait, Beta inputs: = AC<5>, PC ABUS IR ABUS MBR ABUS RBUS AC AC ALU A MBUS ALU B = IR<5> = IR<4> ALU ADD ALU PASS B MAR Address Bus MBR Data Bus ABUS IR ABUS MAR Data Bus MBR RBUS MBR MBR MBUS PC PC + PC ABUS PC Read/Write Request AC RBUS ALU Result RBUS EECS5 - Fall -35 Horizontal Microprogramming Advantages: most flexibility -- complete parallel access to datapath control points Disadvantages: very long control words -- + bits for real processors NOTE: Not all microoperation combinations make sense! Output Encodings: Group mutually exclusive signals Use external logic to decode Example: PC, PC + PC, ABUS PC mutually exclusive Save ROM bit with external :4 Decoder EECS5 - Fall -36

19 Horizontal Microprogramming Partially Encoded Control Outputs C O N T R O L R O M ALU ADD ALU PASS B MAR Address Bus MBR Data Bus ABUS MAR RBUS MBR Read/Write Request AC RBUS RBUS AC AC ALU A MBUS ALU B MBR MBUS ALU Result RBUS MBR ABUS ABUS IR PC :4 PC + PC DEC ABUS PC :4 DEC PC ABUS IR ABUS Data Bus MBR EECS5 - Fall -37 Vertical Microprogramming More extensive encoding to reduce ROM word length Typically use multiple microword formats: Horizontal microcode -- next state + control bits in same word Separate formats for control outputs and "branch jumps" may require several microwords in a sequence to implement same function as single horizontal word In the extreme, very much like assembly language programming EECS5 - Fall -38

20 Vertical Microprogramming Branch Jump Compare indicated signal to or Branch Jump Format Type Condition Select Condition Compare 6 Next Address = Wait = AC<5> = IR<5> = IR<4> Register Transfer Source, Destination, Operation ROM Bits Register Transfer Format Source Destination Operation : NO OP : PC ABUS : IR ABUS : MBR MBUS : MAR M : AC RBUS : ALU Res RBUS : NO OP : RBUS AC : MBUS IR : ABUS MAR : M MBR : RBUS MBR : ABUS PC : NO OP : ALU ADD : ALU PASS B : PC : PC + PC : Read : Write : MBR M EECS5 - Fall -39 Vertical Microprogramming ROM ADDRESS SYMBOLIC CONTENTS BINARY CONTENTS RES RT PC MAR, PC + PC IF RT MAR M, Read BJ Wait=, IF IF RT MAR M, M MBR, Read BJ Wait=, IF IF RT MBR IR BJ Wait=, IF RT IR MAR OD BJ IR<5>=, OD BJ IR<4>=, ST LD RT MAR M, Read LD RT MAR M, M MBR, Read BJ Wait=, LD LD RT MBR AC BJ Wait=, RES BJ Wait=, RES EECS5 - Fall -4

21 Vertical Microprogramming ROM ADDRESS SYMBOLIC CONTENTS BINARY CONTENTS ST RT AC MBR RT MAR M, MBR M, Write ST RT MAR M, MBR M, Write BJ Wait=, RES BJ Wait=, ST OD BJ IR<4>=, BR AD RT MAR M, Read AD RT MAR M, M MBR, Read BJ Wait=, AD AD RT AC + MBR AC BJ Wait=, RES BJ Wait=, RES BR BJ AC<5>=, RES RT IR PC BJ AC<5>=, RES 3 words x ROM bits = 3 bits total versus 6 x 38 = 68 bits horizontal EECS5 - Fall -4 Vertical Programming Controller Block Diagram ROM Address T SRC DST OP Reset ALU ADD ALU PASS B 3:8 3 DEC 4 PC + PC 5 Read 6 Write Enb 7 3:8 3 DEC Enb RBUS AC ABUS IR ABUS MAR M MBR RBUS MBR ABUS PC MBR M PC Read/Write Request Wait AC<5> IR<5> IR<4> Cond Logic LD CLR µpc CNT PC ABUS IR ABUS 3:8 3 MBR ABUS DEC 4 MAR M 5 AC RBUS 6 ALU Res RBUS Enb 7 Reset Clk EECS5 - Fall -4

22 Vertical Microprogramming Condition Logic Condition Selector Wait AC<5> IR<5> IR<4> 4: MUX Condition Comparator Microinstruction Type Microinstruction Type LD CNT EECS5 - Fall -43 Vertical Microprogramming Writeable Control Store Part of control store addresses map into RAM Allows assembly language programmer to implement own instructions Extend "native" instruction set with application specific instructions Requires considerable sophistication to write microcode Not a popular approach with today's processors Make the native instruction set simple and fast Write "higher level" functions as assembly language sequences EECS5 - Fall -44