Caches I. CSE 351 Autumn 2018
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1 Cches I CSE 351 Autumn 2018 Instructors: Mx Willsey Luis Ceze Teching Assistnts: Britt Henderson Luks Joswik Josie Lee Wei Lin Dniel Snitkovsky Luis Veg Kory Wtson Ivy Yu Alt text: I looked t some of the dt dumps from vulnerble sites, nd it ws... bd. I sw emils, psswords, pssword hints. SSL keys nd session cookies. Importnt servers brimming with visitor IPs. Attck ships on fire off the shoulder of Orion, c-bems glittering in the drk ner the Tnnhäuser Gte. I should probbly ptch OpenSSL.
2 Administrivi v Homework 3 due tonight v Lb 3 due next Fridy (2/22) v Midterm grding soon You will be ble to mke regrde requests on Grdescope 2
3 Rodmp C: cr *c = mlloc(sizeof(cr)); c->miles = 100; c->gls = 17; flot mpg = get_mpg(c); free(c); Assembly lnguge: Mchine code: get_mpg: pushq movq... popq ret %rbp %rsp, %rbp %rbp Jv: Cr c = new Cr(); c.setmiles(100); c.setgls(17); flot mpg = c.getmpg(); OS: Memory & dt Integers & flots x86 ssembly Procedures & stcks Executbles Arrys & structs Memory & cches Processes Virtul memory Memory lloction Jv vs. C Computer system: 3
4 How does execution time grow with SIZE? int rry[size]; int sum = 0; for (int i = 0; i < ; i++) { for (int j = 0; j < SIZE; j++) { } } sum += rry[j]; Time Plot SIZE 6
5 Actul Dt Time SIZE 7
6 Mking memory ccesses fst! v Cche bsics v Principle of loclity v Memory hierrchies v Cche orgniztion v Progrm optimiztions tht consider cches 8
7 Processor-Memory Gp Moore s Lw µproc 55%/yer (2X/1.5yr) Processor-Memory Performnce Gp (grows 50%/yer) 1989 first Intel CPU with cche on chip 1998 Pentium III hs two cche levels on chip DRAM 7%/yer (2X/10yrs) 9
8 Problem: Processor-Memory Bottleneck Processor performnce doubled bout every 18 months CPU Bus ltency / bndwidth evolved much slower Reg Core 2 Duo: Cn process t lest 256 Bytes/cycle Min Memory Core 2 Duo: Bndwidth 2 Bytes/cycle Ltency cycles (30-60ns) Problem: lots of witing on memory cycle: single mchine step (fixed-time) 10
9 Problem: Processor-Memory Bottleneck Processor performnce doubled bout every 18 months CPU Reg Bus ltency / bndwidth evolved much slower Cche Core 2 Duo: Cn process t lest 256 Bytes/cycle Min Memory Core 2 Duo: Bndwidth 2 Bytes/cycle Ltency cycles (30-60ns) Solution: cches cycle: single mchine step (fixed-time) 11
10 Cche v Pronuncition: csh We bbrevite this s $ v English: A hidden storge spce for provisions, wepons, nd/or tresures v Computer: Memory with short ccess time used for the storge of frequently or recently used instructions (i-cche/i$) or dt (d-cche/d$) More generlly: Used to optimize dt trnsfers between ny system elements with different chrcteristics (network interfce cche, file cche, etc.) 12
11 Generl Cche Mechnics Cche Smller, fster, more expensive memory Cches subset of the blocks Dt is copied in block-sized trnsfer units Memory Lrger, slower, cheper memory. Viewed s prtitioned into blocks
12 Generl Cche Concepts: Hit Cche Request: Dt in block b is needed Block b is in cche: Hit! Dt is returned to CPU Memory
13 Generl Cche Concepts: Miss Cche Request: Dt in block b is needed Block b is not in cche: Miss! 12 Request: 12 Block b is fetched from memory Memory Block b is stored in cche Plcement policy: determines where b goes Replcement policy: determines which block gets evicted (victim) Dt is returned to CPU 15
14 Why Cches Work v Loclity: Progrms tend to use dt nd instructions with ddresses ner or equl to those they hve used recently 16
15 Why Cches Work v Loclity: Progrms tend to use dt nd instructions with ddresses ner or equl to those they hve used recently v Temporl loclity: Recently referenced items re likely to be referenced gin in the ner future block 17
16 Why Cches Work v Loclity: Progrms tend to use dt nd instructions with ddresses ner or equl to those they hve used recently v Temporl loclity: Recently referenced items re likely to be referenced gin in the ner future v Sptil loclity: Items with nerby ddresses tend to be referenced close together in time block block v How do cches tke dvntge of this? 18
17 Exmple: Any Loclity? sum = 0; for (i = 0; i < n; i++) { sum += [i]; } return sum; v Dt: Temporl: sum referenced in ech itertion Sptil: rry [] ccessed in stride-1 pttern v Instructions: Temporl: cycle through loop repetedly Sptil: reference instructions in sequence 19
18 Loclity Exmple #1 int sum_rry_rows(int [M][N]) { int i, j, sum = 0; for (i = 0; i < M; i++) for (j = 0; j < N; j++) sum += [i][j]; } return sum; 20
19 Loclity Exmple #1 int sum_rry_rows(int [M][N]) { int i, j, sum = 0; } for (i = 0; i < M; i++) for (j = 0; j < N; j++) sum += [i][j]; return sum; Lyout in Memory [3] [3] Note: 76 is just one possible strting ddress of rry [3] M = 3, N=4 [3] [3] [3] Access Pttern: stride =? 1) 2) 3) 4) [3] 5) 6) 7) 8) [3] 9) 10) 11) 12) [3] 21
20 Loclity Exmple #2 int sum_rry_cols(int [M][N]) { int i, j, sum = 0; for (j = 0; j < N; j++) for (i = 0; i < M; i++) sum += [i][j]; } return sum; 22
21 Loclity Exmple #2 int sum_rry_cols(int [M][N]) { int i, j, sum = 0; } for (j = 0; j < N; j++) for (i = 0; i < M; i++) sum += [i][j]; return sum; Lyout in Memory [3] [3] [3] M = 3, N=4 [3] [3] [3] Access Pttern: stride =? 1) 2) 3) 4) 5) 6) 7) 8) 9) 10) [3] 11) [3] 12) [3] 23
22 Loclity Exmple #3 int sum_rry_3d(int [M][N][L]) { int i, j, k, sum = 0; } for (i = 0; i < N; i++) for (j = 0; j < L; j++) for (k = 0; k < M; k++) sum += [k][i][j]; return sum; v Wht is wrong with this code? v How cn it be fixed? [3] [3] [3] [3] [3] [3] [3] [3] [3] m = 0 m = 2 m = 1 24
23 Loclity Exmple #3 int sum_rry_3d(int [M][N][L]) { int i, j, k, sum = 0; } for (i = 0; i < N; i++) for (j = 0; j < L; j++) for (k = 0; k < M; k++) sum += [k][i][j]; return sum; v Wht is wrong with this code? v How cn it be fixed? Lyout in Memory (M =?, N = 3, L = 4) [3] [3] [3] [3] [3] [3]
24 Cche Performnce Metrics v Huge difference between cche hit nd cche miss Could be 100x speed difference between ccessing cche nd min memory (mesured in clock cycles) v Miss Rte (MR) Frction of memory references not found in cche (misses / ccesses) = 1 - Hit Rte v Hit Time (HT) Time to deliver block in the cche to the processor Includes time to determine whether the block is in the cche v Miss Penlty (MP) Additionl time required becuse of miss 26
25 Cche Performnce v Two things hurt the performnce of cche: Miss rte nd miss penlty v Averge Memory Access Time (AMAT): verge time to ccess memory considering both hits nd misses AMAT = Hit time + Miss rte Miss penlty (bbrevited AMAT = HT + MR MP) v 99% hit rte cn be twice s good s 97% hit rte! Assume HT of 1 clock cycle nd MP of 100 clock cycles 97%: AMAT = 99%: AMAT = 27
26 Peer Instruction Question v Processor specs: 200 ps clock, MP of 50 clock cycles, MR of 0.02 misses/instruction, nd HT of 1 clock cycle AMAT = v Which improvement would be best? A. 190 ps clock B. Miss penlty of 40 clock cycles C. MR of misses/instruction 28
27 Cn we hve more thn one cche? v Why would we wnt to do tht? Avoid going to memory! v Typicl performnce numbers: Miss Rte L1 MR = 3-10% L2 MR = Quite smll (e.g. < 1%), depending on prmeters, etc. Hit Time L1 HT = 4 clock cycles L2 HT = 10 clock cycles Miss Penlty P = cycles for missing in L2 & going to min memory Trend: incresing! 29
28 An Exmple Memory Hierrchy <1 ns Smller, fster, costlier per byte 100 ns Lrger, slower, cheper 150,000 ns per byte 10,000,000 ns (10 ms) ms 1 ns 5-10 ns registers 5-10 s on-chip L1 cche (SRAM) off-chip L2 cche (SRAM) 1-2 min min memory (DRAM) SSD Disk locl secondry storge (locl disks) min 31 dys 66 months = 5.5 yers remote secondry storge (distributed file systems, web servers) 1-15 yers 30
29 Summry v Memory Hierrchy Successively higher levels contin most used dt from lower levels Exploits temporl nd sptil loclity Cches re intermedite storge levels used to optimize dt trnsfers between ny system elements with different chrcteristics v Cche Performnce Idel cse: found in cche (hit) Bd cse: not found in cche (miss), serch in next level Averge Memory Access Time (AMAT) = HT + MR MP Hurt by Miss Rte nd Miss Penlty 31
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