This Unit: Processor Design. What Is Control? Example: Control for sw. Example: Control for add

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1 This Unit: rocessor Design Appliction O ompiler U ory Firmwre I/O Digitl ircuits Gtes & Trnsistors pth components n timing s n register files ories (RAMs) locking strtegies Mpping n IA to tpth ontrol Exceptions from Roth EE15 9 Wht Is ontrol? s1 s Rwe Rst 9 signls control flow of t through this tpth MU selectors, or register/memory write enble signls pth of current microprocessor core hs 100s of control signls from Roth EE15 30 ALUop BR DMwe J Rw Exmple: ontrol for Exmple: ontrol for sw BR=0 J=0 BR=0 J=0 s1 s Rw=0 s1 s Rw= Rwe=1 ALUop=0 DMwe=0 Rwe=0 ALUop=0DMwe=1 Rst=1 =0 Rst= =1 Difference between sw n n is 5 signls 3 if you on t count the ( on t cre ) signls from Roth EE15 31 from Roth EE15 3

2 Exmple: ontrol for beq $1,$,trget How Is ontrol Implemente? BR=1 J=0 BR J s1 s Rw= s1 s Rw Rwe=0 ALUop=1DMwe=0 Rwe ALUop DMwe Rst= =0 Difference between store n brnch is only signls Rst ontrol? from Roth EE15 33 from Roth EE15 3 Implementing ontrol Ech instruction hs unique set of control signls Most signls re function of opcoe ome my be encoe in the instruction itself E.g., the ALUop signl is some portion of the MI Func fiel implifies controller implementtion Requires creful IA esign ontrol Implementtion: ROM ROM (re only memory): like RAM but unwritble Bits in t wors re control signls Lines inexe by opcoe Exmple: ROM control for our simple tpth Options for implementing control 1. Use instruction type to look up control signls in tble. Design FM whose outputs re control signls Either wy, gol is sme: turn instruction into control signls opcoe BR J ALUop DMwe Rwe Rst Rw i lw sw beq j from Roth EE15 35 from Roth EE15 36

3 ROM vs. ombintionl Logic A control ROM is fine for 6 insns n 9 control signls A rel mchine hs 100 insns n 300 control signls Even RI s hve lots of instructions 30,000 control bits (~KB) Not huge, but hr to mke fst ontrol must be fster thn tpth Alterntive: combintionl logic EE 5 strikes bck! Exploits observtion: mny signls hve few 1s or few 0s ontrol Implementtion: ombintionl Logic Exmple: combintionl logic control for our simple tpth opcoe i lw sw beq j BR J DMwe Rwe Rw Rst ALUop from Roth EE15 37 from Roth EE15 38 pth n ontrol Timing This Unit: rocessor Design s1 s ontrol (ROM or combintionl logic) Appliction O ompiler Firmwre U I/O ory Digitl ircuits Gtes & Trnsistors pth components n timing s n register files ories (RAMs) locking strtegies Mpping n IA to tpth ontrol Exceptions Re I Re s Re DMEM Write DMEM (Re ontrol ROM) Write s Write from Roth EE15 39 from Roth EE15 0

4 Exceptions Exceptions n interrupts Infrequent (exceptionl!) events I/O, ivie-by-0, illegl instruction, pge fult, protection fult, ctrl-, ctrl-z, timer Hnling requires intervention from operting system En progrm: ivie-by-0, protection fult, illegl insn, ^ Fix n restrt progrm: I/O, pge fult, ^Z, timer Hnling shoul be trnsprent to ppliction coe Don t wnt to (cn t) constntly check for these using insns Wnt Fix n restrt equivlent to never hppene Exception Hnling Wht oes exception hnling look like to softwre? When exception hppens ontrol trnsfers to O t pre-specifie exception hnler ress O hs privilege ccess to registers user processes o not see These registers hol informtion bout exception use of exception (e.g., pge fult, rithmetic overflow) Other exception info (e.g., ress tht cuse pge fult) of ppliction insn to return to fter exception is fixe O uses privilege (n non-privilege) registers to o its thing O returns control to user ppliction me mechnism vilble progrmmticlly vi YALL from Roth EE15 1 from Roth EE15 MI Exception Hnling MI uses registers to hol stte uring exception hnling These registers live on coprocessor 0 $1: E (hols of user progrm uring exception hnling) $13: exception type (YALL, overflow, etc.) $8: virtul ress (tht prouce pge/protection fult) $1: exception msk (which exceptions trigger O) Exception registers ccesse using two privilege instructions mfc0, mtc0 rivilege = user process cn t execute them mfc0: move (register) from coprocessor 0 (to user reg) mtc0: move (register) to coprocessor 0 (from user reg) rivilege instruction rfe restores user moe Kernel executes this instruction to restore user progrm from Roth EE15 3 Implementing Exceptions Why o rchitects cre bout exceptions? Becuse we use tpth n control to implement them More precisely to implement spects of exception hnling Recognition of exceptions Trnsfer of control to O rivilege O moe from Roth EE15

5 pth with upport for Exceptions ummry Rs R Rr Rw I R o-procesor Rwe s1 s A ALUinA B O D w We now know how to buil fully functionl processor But We re still treting memory s blck box (ctully two green boxes, to be precise) Our fully functionl processor is slow. Relly, relly slow. o-processor register (R) file neen t be implemente s RF Inepenent registers connecte irectly to pertinent muxes R (processor sttus register): in privilege moe? from Roth EE15 5 from Roth EE15 6 ingle-ycle erformnce This Unit: rocessor Design Useful metric: cycles per instruction (I) Esy to clculte for single-cycle processor: I = 1 econs/progrm = (insns/progrm) * 1 I * (N secons/cycle) IQ: How mny cycles/secon in 3.8 GHz processor? low! lock perio must be elongte to ccommote longest opertion In our tpth: lw Goes through five structures in series: insn mem, register file (re), ALU, t mem, register file gin (write) No one will buy mchine with slow clock Not even your grnprents! Appliction O ompiler Firmwre U I/O ory Digitl ircuits Gtes & Trnsistors pth components n timing s n register files ories (RAMs) locking strtegies Mpping n IA to tpth ontrol Next up: ipelining from Roth EE15 7 from Roth EE15 8