Effect of Aggressor Driver Width on Crosstalk for Static and Dynamic Switching of Victim Line

Transcription

1 ICCCT 1 Effect of Aggressor Driver Width on Crosstalk for Static and Dynamic Switching of Victim Line Devendra Kumar Sharma1, B.K.Kaushik2, and R.K.Sharma3 1 Department of Electronics and Communication Engineering, Meerut Institute of Engineering and Technology, Meerut 2 Department of Electronics and Computer Engineering, Indian Institute of Technology, Roorkee Department of Electronics and Communication Engineering, National Institute of Technology, Kurukshetra ( d_k_s197@yahoo.co.in; bkk23fec@iitr.ernet.in; mail2drrks@gmail.com) Abstract: In DSM technology, unintended interactions between signals propagating through interconnect turn out to be critical design concern. At technology nodes below.25µm, the performance and correctness of a design cannot be assured without considering noise effects. In integrated circuits, the main cause of signal integrity problems is crosstalk. This paper presents the effects of aggressor driver width variation on crosstalk noise in RLC coupled interconnects for static and dynamic switching of victim line. To demonstrate these effects, two distributed RLC interconnects coupled inductively and capacitively are taken into consideration. The length of interconnect is taken as 4mm and far end capacitive loading is 3 ff. The SPICE waveforms are generated at far end of victim line for varying width of aggressor driver PMOS from 2µm to 12µm in steps of 2µm. The corresponding NMOS width is half of PMOS. The victim driver width is kept fixed at 4µm for PMOS and 2µm for NMOS. The simulation is carried out at.13µm, 1.5V technology node. Three different cases of input switching are considered. It is observed that level of crosstalk noise for static and dynamic switching of victim line increases with driver width. Keywords: Dynamic switching, Crosstalk, Driver width I. INTRODUCTION The semiconductor industry has been fueled by enhancements in integrated circuit (IC) density and performance, resulting in information revolution for over four decades and is expected to continue in future. The periodic improvement in density (as per Moore s Law) and performance has, been mainly achieved through aggressive device scaling and/or increase in chip size. The shrinking feature size of MOSFET devices is largely responsible for growth of VLSI circuits [1, 2]. The performance parameters such as crosstalk, delay and power dissipation of a high speed chip is highly dependent on the interconnects which connect different macro cells within a VLSI chip [3-14]. To escape prohibitively large delays, designers scale down global wire dimensions more sluggishly than the transistor dimensions [7]. As technology advances, interconnects have turned out to be more and more important than the transistor resource, and it is essential to use global interconnects optimally. For high-speed high-density chips of submicron geometry, it is mostly the interconnections rather than the device performance that determines the chip performance. As per International Technology Roadmap for Semiconductors (ITRS) [15], the gap between interconnection delay and gate delay will increase to 9:1 at 65nm technology and on-chip wire length is expected to increase to 2.22 km/cm 2 by the year 21. Wide wires are frequently encountered in clock distribution networks, power and ground lines and other global interconnects such as data bus and control lines in upper metal layers. These wires, being low resistive lines exhibit significant inductive effects [16, 17] at high frequencies. So, due to the presence of these inductive effects, the RLC distributed model of interconnect equivalent to transmission line is more effective in current scenario. The RLC transmission lines, when running parallel to each other in the same plane or on different planes have capacitive and inductive coupling which causes crosstalk noise. In multilayer interconnect structures, wires on adjacent layers are routed orthogonally to minimize the crosstalk. This crosstalk noise or coupling noise depends on the spacing between interconnects, frequency of operation, length of interconnect, switching pattern and transition time of input. The crosstalk or coupled noise induces unpredictable delays and noise glitch which may lead to logical errors and can cause functional failure [18, 19]. The effect of crosstalk induced overshoot and undershoot generated at circuit node can cause false switching when the magnitude of overshoot or undershoot generated is beyond the threshold voltage of the gate. The peak overshoot and undershoot can wear out the thin oxide layer on chip resulting in its permanent failure. So, crosstalk becomes an important parameter of consideration in interconnect design. The crosstalk faults can be minimized by resizing drivers, shielding interconnects, rerouting signals, bus encoding [11] and repeater insertion techniques [2, 21]. Researchers have reported the analysis of crosstalk noise in different ways. Kaushik et al. analyzed crosstalk noise for many cases of switching interconnects [2, 22, 23]. Authors have reported the effects of aggressor driver width on crosstalk incase of static victim line [23]. Shahin et al. [24] and Verma et al. [6] analyzed crosstalk considering process variations. A comprehensive survey /1/$ IEEE 667

2 ICCCT 1 and review of noise in interconnects in UDSM technology is presented in [25]. This paper observes the effect of aggressor driver width variation on the crosstalk noise at far end of victim line for both static and dynamic switching scenarios by taking three different cases viz. (i) Aggressor is switching Fig. 1. Interconnect Model for Simulation from high to low and victim is static high. (ii) Both inputs are switching in same phase from high to 1.722μ 1.4μ low L = (iii) Both inputs are switching in opposite phase i.e. 1.4μ 1.722μ aggressor is switching from high to low and victim is switching from low to high. Fig. 2. Interconnect Parameters As an example, R a is calculated as The crosstalk noise is observed at far end of victim line at node Vout2. The peak overshoot and undershoot at different aggressor driver width is observed. The results are obtained through SPICE simulations. II. EXPERIMENTAL AND SIMULATION SETUP For our studies, two distributed coupled RLC lines model are used for the simulation as shown in Fig. 1. The distributed RLC model is the most accurate approximation of the actual behavior than the traditional lumped RLC model [2]. The interconnect length is taken as 4mm. Each line of the coupled interconnect is 2µm wide,.68µm thick and separated by.24µm [2]. Twenty distributed lumps of Gamma-type are considered for the complete interconnect length. The capacitance and inductance values are obtained from closed form expressions available in [26-28]. At far end of lines, CMOS load is replaced by 3fF capacitor. In Fig. 1, R a, L a and C a are the resistance, inductance and capacitance per lump of line-1 and R v, L v and C v are the parameters per lump of line-2 respectively. M av and C av are mutual inductance and coupling capacitance per lump of lines. The interconnect parameters for one meter length is shown in Fig ,5 R = 12,5 19p C = 64p 64p 19p 12,5 4 Ω. 1 2 Similarly, other parameters of line are obtained. Our simulations use an IBM.13µm technology with copper interconnect process (MOSIS) and V dd =1.5V. The transition time of the input ramp is 25ps. The width of victim driver PMOS and NMOS are 4 µm and 2µm respectively and the width of aggressor driver PMOS is varied from 2 to 12µm in steps of 2µm, keeping the corresponding NMOS width half of PMOS width. III. SIMULATION RESULTS AND DISCUSSIONS In this section, the effects observed by variation of aggressor driver width from 2µm to 12µm on crosstalk noise in victim line under different conditions of inputs switching are discussed. The peak overshoot and undershoot at output node in the model with varying aggressor driver width are also observed. The waveforms for all three cases considered for our study are shown in Fig. 3 to Fig. 5. It is observed from these figures that the peak (positive and negative both) of crosstalk noise increases with increasing PMOS channel width of aggressor driver in all three cases of inputs switching. This is because of the fact that with increase in driver width, the driver resistance decreases causing increase in current driving capability of the driver, so crosstalk noise increases. The interconnect designers often increase 668

3 ICCCT 1 Case (i) Aggressor is Switching from high to low and victim is static high (Fig. 3(a), 3(b), 3(c)).8 Crosstalk noise w ith varying Aggr. driver w idth Victim output Vout2, Volts Width=2u Width=4u Width=6u Width=8u Width=1u Width=12u Time (ps) Fig. 3(a) Crosstalk noise with varying aggressor driver width at far end of victim line Peak overshoot vs. Aggr. driver width Peak undershoot vs Aggr. driver width Peak overshoot (volts) Peak undershoot (volts) Width (um ) Fig. 3(b) Peak overshoot with varying aggressor driver width Fig. 3(c) Peak undershoot with varying aggressor driver width 669

4 ICCCT 1 Case (ii) Both inputs are switching from high to low (Fig. 4(a), 4(b), 4(c)) Peak overshoot vs Aggr. driver width Peak undershoot vs Aggr. driver width Peak overshoot (Vlts) Peak undershoot (Volts) Fig. 4(b) Peak overshoot with varying aggr. driver width Fig. 4(c) Peak undershoot with varying aggr. driver width 2.5 Crosstalk affected signal w ith vaying Aggr. driver w idth 2 Victim voltage Vout2, Volts Time (ps) Width=2u Width=4u Width=6u Width=8u Width=1u Width=12u Fig. 4(a) Crosstalk noise affected signal at far end of victim line 67

5 ICCCT 1 Case (iii) Aggressor is switching from high to low and victim from low to high (Fig. 5(a), 5(b), 5(c)) Peak overshoot vs Agg. driver width Peak undershoot vs Aggr. driver width Peak overshoot (Volts) Peak undershoot (Volts) Fig. 5(b) Peak overshoot with varying aggr. driver width Fig. 5(c) Peak undershoot with varying aggr. driver width 2 Crosstalk affected signal with varying Aggr. driver width Victim voltage Vout2, Volts Width=2u Width=4u Width=6u Width=8u Width=1u Width=12u -1 Time (ps) Fig. 5(a) Crosstalk noise affected signal at far end of victim line 671

6 ICCCT 1 driver width to reduce propagation delay which may lead to increase in crosstalk level. It is also observed that, in dynamic switching, peak overshoot is more pronounced in case (ii) when both inputs are switching in the same phase, however it is less in case (iii) when the inputs are switching in opposite phase. So, the propagation delay in case (iii) will be more as compared to case (ii). This is because of Miller effect. Further more, in dynamic switching of inputs, the negative peak is more in case (iii). IV. CONCLUSION For capturing the effect of driver width on crosstalk noise, SPICE simulations are run and various waveforms are obtained for different switching scenarios. The results obtained very well demonstrate the impact of aggressor driver width on crosstalk for RLC coupled interconnects. It is observed that peaks of noise in the signal increases with increase in aggressor driver width. REFERENCES [1] Sung Mo Kang, Y. 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