CMPEN 411. Spring Lecture 01: Introduction

Transcription

1 Kyusun Choi CMPEN 411 VLSI Digital Circuits Spring 2009 Lecture 01: Introduction Course Website: [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] Sp09 CMPEN 411 L01 S1

2 How Do the Pieces Fit Together? Application Operating System Memory system Compiler Firmware Instr. Set Proc. Datapath & Control Digital Design Circuit Design I/O system Instruction Set Architecture Coordination of many levels l of abstraction ti Under a rapidly changing set of forces Design, measurement, and evaluation Sp09 CMPEN 411 L01 S2

3 Course Contents Introduction to digital integrated circuits CMOS devices and manufacturing technology. CMOS logic gates and their layout. Propagation delay, noise margins, and power dissipation. Combinational (e.g., arithmetic) and sequential circuit design. Memory circuit design. Course goals Ability to design and implement CMOS digital circuits and optimize them with respect to different constraints: size (cost), speed, power dissipation, and reliability Course prerequisites EE 310. Electronic Circuit Design CMPEN 471. Logic Design of Digital Systems Sp09 CMPEN 411 L01 S3

4 Background from CMPEN 471 and EE 310 Basic circuit theory resistance, capacitance, inductance MOS gate characteristics Hardware description language VHDL or verilog Use of modern EDA tools simulation, synthesis, validation (e.g., Synopsys) schematic capture tools (e.g., LogicWorks) Logic design logical minimization, FSMs, component design Sp09 CMPEN 411 L01 S4

5 Course Structure Design and tool intensive class Industrial Standard toolset for layout - Online documentation and tutorials HSPICE for circuit simulation unix (Sun/Solaris) operating system environment Lectures: Sp09 CMPEN 411 L01 S5 2 weeks on the CMOS inverter 3 weeks on static and dynamic CMOS gates 2 weeks on C, R, and L effects 2 week on sequential CMOS circuits 2 weeks on design of datapath structures 2 weeks on memory design 1 week on design for technology scaling, trends Schedule is on-line syllabus

6 What is the most important invention for the last 50 years? Sp09 CMPEN 411 L01 S6

7 The evolution of IC When was the first transistor invented? A B C D The inventors were in which company? A. IBM B. Bell Lab C. TI D. Motorola Sp09 CMPEN 411 L01 S7

8 The evolution of IC When was the first transistor invented? Modern-day electronics began with the invention in 1947 of the transfer resistor, also known as the bi-polar transistor by Bardeen et.al at Bell Laboratories Sp09 CMPEN 411 L01 S8

9 The evolution of IC When was the first IC invented? A B C D The inventor was with which company? A. IBM B. Bell Labs C. TI D. Motorola Sp09 CMPEN 411 L01 S9

10 The evolution of IC When was the first IC (integrated circuit) invented? In 1958 the integrated circuit was born when Jack Kilby at Texas Instruments successfully interconnected, by hand, several transistors, resistors and capacitors on a single substrate Sp09 CMPEN 411 L01 S10

11 Transistor Revolution Transistor Bardeen et.al. (Bell Labs) in 1947 Bipolar transistor Schockley in 1949 First bipolar digital logic gate Harris in 1956 First monolithic IC Jack Kilby in 1958 First commercial IC logic gates Fairchild 1960 Sp09 CMPEN 411 L01 S11

12 MOSFET Technology MOSFET transistor - Lilienfeld (Canada) in 1925 and Heil (England) in 1935 CMOS 1960 s, but plagued with manufacturing problems (used in watches due to their power limitations) PMOS in 1960 s (calculators) NMOS in 1970 s (4004, 8080) for speed CMOS in 1980 s preferred MOSFET technology because of power benefits BiCMOS, Gallium-Arsenide, Silicon-Germanium SOI, Copper-Low K, strained silicon, High-k gate oxide... Sp09 CMPEN 411 L01 S12

13 Worldwide Semiconductor Revenue Source: ISSCC 2003 G. Moore No exponential is forever, but forever can be delayed Sp09 CMPEN 411 L01 S13

14 Transistors shipped per year How many transistors you can buy with 1$? Sp09 CMPEN 411 L01 S14

15 Average Transistor Price by Year Sp09 CMPEN 411 L01 S15

16 1 Wafer in 1964 vs. 300 mm (12 ) Wafer in 2003 Sp09 CMPEN 411 L01 S16

17 The IC in 1961 vs. Intel Pentium 4 in 2004 Sp09 CMPEN 411 L01 S17

18 Moore s Law In 1965, Gordon Moore predicted that the number of transistors that can be integrated on a die would double every 18 months (i.e., grow exponentially with time). Amazingly visionary million transistor/chip barrier was crossed in the 1980 s transistors, 108 KHz clock (Intel 4004) Million transistors (Ultra Sparc III) Million, 2 GHz clock (Intel P4) Million, 3.4Ghz (Intel P4 Prescott) Feb Million, IBM Cell processor, Billion, 1.6Ghz (Intel Itanium-2)-2006, Sept. Sp09 CMPEN 411 L01 S18

19 Moore s Law plot (from his original paper) 10 9 # tra ansistors integrated 10 6 circuit 10 5 invented memory 10 4 CPU year Sp09 CMPEN 411 L01 S19

20 Moore s Law in Microprocessors # transistors on lead microprocessors double every 2 years X growth in 1.96 years! Transis stors (MT) Sp09 CMPEN 411 L01 S P6 Pentium proc Year Courtesy, Intel

21 # of Transistors per Die Source: ISSCC 2003 G. Moore No exponential is forever, but forever can be delayed Sp09 CMPEN 411 L01 S21

22 Intel 4004 Microprocessor (10000 nm) transistors 13.5 mm2 108k Hz Sp09 CMPEN 411 L01 S22

23 Intel Pentium 4 Prescott (2004) 90 nm Area: 112 mm2 125 M transistors L1-Instruction: 16K L1-Data: 16K L2: 1MB Sp09 CMPEN 411 L01 S23

24 Two chips you are seeing today Microprocessor ASIC (Application Specific IC) 366MHz 40mm2 3.65M 40Mhz 10 mm2 500K Sp09 CMPEN 411 L01 S24

25 IBM Cell Overview Cell Prototype Die (Pham et al, ISSCC 2005) M I C P P U S S S S P P P P U U U U MIB B I C R R A C S S S S P P P P U U U U IBM/Toshiba/Sony joint project years, 400 designers, 3/9/2001, $400M, 234 million transistors, t 4+ Ghz, 256 Gflops (billions of floating pointer operations per second) Sp09 CMPEN 411 L01 S25

26 State-of-the Art: Lead Microprocessors Freq Transistors Die size Power Date (HZ) mm2 Server IBM Power G 180M 267 N/A 2003 Itanium 2 1.5G 410M W 2003 IBM Power 5 2G 276M 389 N/A 2004/2 PC IBM Power PC G 58M W 2003/6 Pentium 4 3.2G 55M W 2003/6 AMD Athlon G 105M W 2003/9 Pentium 4 34G 3.4G 125M W 2004/2 (Prescott) (All use 0.13 um technology except Pentium 4 Prescott, which uses 90 nm tech) Pentium nm (2001) 1.7 G Hz 42 M transistors 217 mm2 Pentium nm (2003) 3.2G Hz 55 M Transistors 131 mm2 Pentium 4 90 nm (2004) 3.4 Hz 125 M Transistors 112 mm2 Pentium on 65nm (2005/2006) 250 Million Pentium on 45nm (2007) 400 to 500 Million Sp09 CMPEN 411 L01 S26

27 State-of-the Art: Lead Microprocessors (up to date) 300mm wafer and Pentium 4 IC. Photos courtesy of Intel. Sp09 CMPEN 411 L01 S27

28 Evolution in DRAM Chip Capacity Kbit ca pacity/c c hip human memory human DNA 4X growth every 3 years! 256 1,000 book 4, μm 16, μm page 64, μm 256, μm 1,000,000 4,000,000 16,000, μm μm μm 64,000, μm 0.07 μm encyclopedia 2 hrs CD audio 30 sec HDTV Year Sp09 CMPEN 411 L01 S28

29 Die Size Growth 100 Die size grows by 14% to satisfy Moore s Law Die si ize (mm) P6 486 Pentium proc 1 Sp09 CMPEN 411 L01 S Year Courtesy, Intel

30 Clock Frequency Lead microprocessors frequency doubles every 2 years X every 2 years Freque ency (Mhz z) P6 Pentium proc Sp09 CMPEN 411 L01 S Year Courtesy, Intel

31 Power Dissipation Lead Microprocessors power continues to increase 100 atts) 10 P1 ower (Wa P6 Pentium proc Year Power delivery and dissipation will be prohibitive Sp09 CMPEN 411 L01 S31 Courtesy, Intel

32 Power Density ) Pow wer Densi ity (W/cm Rocket Nozzle Nuclear Reactor Hot Plate 486 P6 Pentium proc Year Power density too high to keep junctions at low temp Sp09 CMPEN 411 L01 S32 Courtesy, Intel

33 Power Density 2) Pow wer Densi ity (W/cm Rocket Nozzle Nuclear Reactor Hot Plate 486 P6 Pentium proc Year Power density too high to keep junctions at low temp Sp09 CMPEN 411 L01 S33 Courtesy, Intel

34 ITRS The International Technology Roadmap for Semiconductors (ITRS) is the industry s prediction for the future of semiconductors. It is mostly an extrapolation of existing trends. The ITRS is often slow. Sp09 CMPEN 411 L01 S34

35 Technology Directions: Old SIA Roadmap Year Feature size (nm) Mtrans/cm Chip size (mm 2 ) Signal pins/chip Clock rate (MHz) Wiring levels Power supply (V) High-perf power (W) Battery power (W) Sp09 CMPEN 411 L01 S35

36 Technology Scaling Technology shrinks by ~0.7 per generation With every generation can integrate t 2x more functions on a chip; chip cost does not increase significantly Cost of a function decreases by 2x But How to design chips with more and more functions? Design engineering population does not double every two years Hence, a need for more efficient design methods Exploit different levels of abstraction Sp09 CMPEN 411 L01 S36

37 Design Abstraction Levels SYSTEM + MODULE GATE CIRCUIT V in V out S n+ G DEVICE D n+ Sp09 CMPEN 411 L01 S37

38 Design Productivity Trends 10, ,000 Co mplexity Lo ogic Transis stor per Chip (M) 1, Logic Tr./Chip Tr./Staff Month. x x x x x x x x 58%/Yr. compounded Complexity growth rate 21%/Yr. compound Productivity ygrowth rate 10,000 1, Produ uctivity (K) Trans./Staff - Mo Complexity outpaces design productivity Sp09 CMPEN 411 L01 S38 Courtesy, ITRS Roadmap

39 Design Productivity Crisis Year Tech. (nm) Complexity Frequency 3 Yr. Design Staff Size Staff Costs M Tr. 400 MHz 210 $90 M M Tr. 500 MHz 270 $120 M M Tr. 600 MHz 360 $160 M M Tr. 800 MHz 800 $360 M 1996: 100 person in P6 team 2007: 1600 person in P10 team Question:?? Person in P38 team? Answer: Every inhabitant of our planet We need to improve the productivity via design automation Sp09 CMPEN 411 L01 S39

40 Major Design Challenges Microscopic issues ultra-high h speeds power dissipation and supply rail drop growing importance of interconnect noise, crosstalk reliability, manufacturability clock distribution Macroscopic issues time-to-markett t design complexity (millions of gates) high levels of abstractions reuse and IP, portability systems on a chip (SoC) tool interoperability Sp09 CMPEN 411 L01 S40

41 Next Lecture and Reminders Next lecture Design metrics - Reading assignment 1.3 Reminders Sp09 CMPEN 411 L01 S41