Use of Lock-In Thermography for non-destructive 3D Defect Localization on System in Package and Stacked-Die Technology

Transcription

1 Use of Lock-In Thermography for non-destructive 3D Defect Localization on System in Package and Stacked-Die Technology Rudolf Schlangen, S. Motegi, T. Nagatomo, DCG Systems, Fremont, CA, USA C. Schmidt, F. Altmann, Fraunhofer Institute for Mechanics of Materials Halle, Germany H. Murakami, Toshiba, Yokohama, Japan S. Hollingshead, J. West, Texas Instruments, TX, USA A. Reverdy, Sector Technologies, France 1

2 Outline Introduction of Lock-In Thermography Motivation Case studies on three different 3D defect localization approaches by local reference points in combination with 3D X-Ray based on 3D simulation SW Summary 2

3 Steady-state vs. Lock-in Thermography Steady-state Thermography Lock-In Thermography Both images acquired with cooled InSb camera, sensitive from 3-5um at identical DUT power settings 3

4 Simplified working principle of Real-Time Lock-In Thermography IR-image (V = off) on-images off-images IR-image (V = on) (frame rate 100Hz) IR Camera V detects temperature differences only tp (flock-in) t surface tsurface 0 xy defect localization t full lock-in thermal delay - defect depth (z) V 4

5 Real-Time Pixel-Wise Lock-In Algorithm Vlock-in heating power flock-in time multiplication by two weighting factors stream of incoming images two Result: in-phase 0 1 sin(t) -1 sin(t)*f(t) F(t) out of phase -90 -cos(t)*f(t) 1 -cos(t) -1 t=1/f frame Source: O. Breitenstein et al., Lock-in Thermography, Springer Verlag

6 Results and Benefits sin(t) All math is applied to every pixel individually and at real time without acquisition time limit Topography and Results based on same data no registration error!! Amplitude : - not delay sensitive - good spatial resolution Phase: - 3D localization - week spots also -cos(t) Amp (0 ) 2 (90 ) 2 arctan 90 0 Source: O. Breitenstein et al., Lock-in Thermography, Springer Verlag

7 Increasing LIT acquisition time significantly improves signal-to-noise The longer the image is acquired, the more accurate / sensitive it becomes The image may be acquired for as long as is needed The results continuously updates (every 2 seconds) 7

8 Motivation - LIT for Package Level FA Packages are black-boxes with multiple possible defect types: 1) in lead-frame removing the package 2) in bond wires may remove the defect 3) internal to the dies Electrical test often doesn t provide differentiation => Goal: non-destructive localization and differentiation through the Package A) only 1 => classification by x,y location B) 1 & 3 possible => differentiation via thermal delay t surface C) all three + edge effects more challenging; local reference needed 2 C A 3 B 1 8

9 Through-Package / Interposer Defect Hot spot location Current Leak location DIE Bad Die (46 ｘ 37 mm2) Good Die PFA revealed a particle, causing a short between VDD and GND inside interposer board. 5x 9

10 LIT for 3D Defect Localization package surface at t1 Lock-In Excitation Voltage t1 t2 t3 A t4 Time B at t2 at t3 - phase is proportional to defect depth - knowing the material parameters allows to calculate depth of defect - SW for theoretical modeling and calibration at t4 Surface Temperature above point A point B t ~ ELITE phase result ta tb Time 10

11 Stacked-Die Analysis - 3D Localization by Direct Comparison Clear localization in x & y, but z depth is unknown due to material stack forward biased IO diode can serve as direct reference points heat is knowingly generated on the die surface shorted pin A Vlock-in = 80mV, I = 6.2mA, mould upper die lower die multi-layer leadframe x B flock-in= 2Hz, t ~15min x, y localization C lower die Vlock-in = 0.8V, I = 1.49mA, flock-in= 10Hz, t ~10min x C B upper die Vlock-in = 0.75V, I = 1mA, DUT from TI (TX) flock-in= 10Hz, t ~10min 11

12 Stacked-Die Analysis - 3D Localization by Direct Comparison higher phase-shift equals higher defect depth defect must be below lower die / in uppermost lead frame layer second set of reference measurements (good DUT) shows precise match data consistent and reproducible =>> Reference measurements only once per technology!! 100 upper die A lower die x multi-layer leadframe x B phase mould fail upper die lower die upper (ref) lower (ref) x C DUT from TI (TX) flock-in8 [Hz] 12 10

13 Package Defect BGA pin-short BGA 933Pins Short between 2 pins Wire Die Resin Substrate Ball Die bonding contact Customer tried Time Domain Reflectometry (TDR) followed by high resolution 3D x-ray and failed multiple times 13

14 Package Defect BGA pin-short consistent localization from front- and backside lock-in frequency = 1Hz, V = 0.1V, I 0.1A, P 10mW ELITE acquisition time ~ １ min (each) x-ray FOV (10x) frontside backside 14

15 3D x-ray Results, Geometrical magnification 10x magnification too low, defect not resolved yet 15 15

16 3D x-ray Results, Geometrical magnification 40x 16 16

17 3D x-ray Results, Geometrical magnification 40x no PFA required, fully non-destructive root cause analysis touching bond-wires, fused during electrical test 17 17

18 Time for 3D X-Ray ONLY Volume per high resolution scan 40x): ~ 1.35 mm 3 800μm 1300μm 1300μm full scan takes: > 4 x 4 x 3 x 2h = 96h 4 Days!! + data analysis time data acquisition and 3D rendering takes 2h for the desired resolution ze i s T U D m full m 5. 6 x m m m 5 m 6. 4 x 2.!! Initial defect localization required!! 18 18

19 Stacked-Die Analysis - full 3D, First Results Challenges: parallel bonding => on DUT reference measurements are impossible too many materials => thermal properties partly unknown (glue layer) First Customer Results on 8+1 μsd technology (Toshiba Japan) meas. at only one lock-in frequency (5Hz) simple comparison to reference data via Excel spread-sheet 76% correct, 100% ± 1 layer #1 712μm #8 Very promising first results! Phase resolution is high enough to localize single layers of 8 die μsd! Goal: improve accuracy, throughput and ease of use 19

20 Stacked-Die Analysis - improved accuracy & ease of use Dedicated SW simulates phase shift per layer Input layer geometries & material parameters Adjust based on small number of known reference devices (only once) =>> clear match between theory and results phase [ ] z-resolution sufficient for 8 layer technology optimizing procedure for improved accuracy 1 simulation model 2 measurements start frequency die # bad S NR long a cquisit ion tim #8 e #1 flock-in [Hz] 20

21 Stacked-Die Analysis - improved accuracy & ease of use Dedicated SW simulates phase shift per layer Input layer geometries & material parameters Adjust based on small number of known reference devices (only once) =>> clear match between theory and results z-resolution sufficient for 8 layer technology optimizing procedure for improved accuracy Ongoing research collaboration with Fraunhofer IWM, Halle, Germany matching FOV & DUT size for initial acquisition increased camera speed for 3D analysis via sub-array => x, y & rough z => fine z; fast - improved throughput: custom wide-angle lens max. FOV* 200 x 160mm2 complete PCB board all 640x512 pixels frame rate = 100Hz * on DCG standard stage setup 1x lens & sub-array complete PCB board e.g. using 64x64 pixels frame rate ~ 950Hz => 9.5 times faster acquisition! 21

22 Summary / Conclusion real-time lock-in thermography for highest sensitivity (< 1 W) allowing through package defect localization ELITE Phase Data enabling 3D localization depth accuracy of ± 5% thru homogeneous MC successful localization in x, y & die for 8-stack SD combination of LIT & 3D x-ray fast, high-yield and fully non-destructive PFA 22

23 Thanks for your attention! 23

24 24

25 Thru-Package / Defect on DIE ATE driven LIT (exclusive to ELITE) packaged memory part - 110nm process high Icc problem (~10mA extra current) toggling Vdd via dedicated test program (ATE) clearly two separate hotspots, centric to the die => safe to de-package!! wide angle lens thru package (low frequency) (2min) (high frequency) 1x lens (6min) (2min) 10x lens root cause: die surface damage (cropped image) (1min) (cropped image) (5min) (theory & more application examples published at ESREF 2010, R. Schlangen 25et al.)

26 Thru-Package / Low Ohmic Defect R << 20 mω => very low Power dissipation wide angle lens (28mm) 5mm => long acquisition => image mosaic undesired wide angle lens adjustable field of view the full DuT can be analyzed at once macro lens with unsurpassed sensitivity higher magnification is useless if defects can t be localized with low mag. successful localization of package design bug 5mm PFA: faulty interposer layout macro lens (1x) - direct short between Vdd and Vss 26