Total Inspection Solutions Ensuring Known-Good 3DIC Package. Nevo Laron, Camtek USA, Santa Clara, CA

Transcription

1 Total Inspection Solutions Ensuring Known-Good 3DIC Package Nevo Laron, Camtek USA, Santa Clara, CA

2 Density Packaging Trends vs. Defect Costs Functionality

3 Package Yield 3DIC yield statistics Y stack P good die layer count Package yield declines rapidly with layer count in stack

4 Does Stacking Raise Yield Loss Cost? Not Necessarily! (Inspection may help ) 4

5 Cost ($) Inspection Economy High Yield Loss Cost Yield with inspection>yield without inspection Cost with inspection<cost without inspection 100% Total Cost 0 Y 0,C 0 Total Cost1 Y 1,C Outgoing Yield (%) 5

6 Undetectable by Electrical Test Deformed Bump Incomplete Via Partial Filling RDL / UBM Co-planarity Probing Damage Overlay Chipping

7 3DIC Inspection Challenges and Solutions June 13, 2011

8 The available solutions

9 Wafer level inspection Legacy method vs. Metrology Legacy method Dark anomaly Mark die bad Metrology method Mark die bad Classification Co-planarity Plating trend Etc. 9

10 Via Metrology 3D Process development and characterization 2D Process Monitoring Via First / Middle Non-destructive, sampling Destructive, Non-destructive, 100% Via Last / Post Bond D <15µm d/d < 10 15µm< D <50µm d/d < 13 > 50µm 0.5 < d/d < 3

11 Post-Thinning Filling Inspection Challenges: No alignment fiducials Backside inspection thru glass carrier, OR Thin wafer handling Solutions: Auto alignment Step-less illumination control Thin wafer handlers

12 Redistribution Layer Inspection Challenges: Line rough pattern is non-repeatable false calls Solutions: Advanced analysis technology ignores pattern variations, yet detects line integrity violations

13 RDL 3D Metrology Measure: Line width / space Line thickness Surface roughness

14 Photo Resist Overlay Error Challenge: Measure CD accurately, despite PR transparency and low contrast Solution: Color filter Edge detection

15 Overlay Offset Distribution process trend Direction Magnitude

16 µbump / Pillar Bump Integrity

17 µbump / Pillar Bump Integrity

18 µbump Defects Challenge: Inspect millions of bumps per wafer to detect every: Deformation Misplacement Size deviation Missing / extra At high throughput Hi-mag. review As scanned Solutions: Dedicated µbump algorithms Acute detection al low mag. Integrated 3D capabilities

19 µbump Metrology - SPC Histogram of over 4 million bumps: Bi-modal distribution indicates an assignable cause Bump diameter [um]

20 µbump 3D Metrology

21 µbump 3D Metrology Pre-reflow bump morphology showing volume and surface roughness

22 3D distribution

23 Package-level Inspection Use wafer inspection & metrology data for: W2W registration Via-Bump alignment Post dicing inspection Chipping Kerf location Backside cracks Die-to-wafer

24 Automated Defect Classification Auto Die level classification Auto defect level classification

25 Supporting W2W Yield Enhancement Total Yield (Unsorted): 72.6% Bad

26 Supporting W2W Yield Enhancement

27 Supporting W2W Yield Enhancement Standard and custom wafer inspection maps enable floor-wide APC/AEC Total Yield (this example): sorted 76% Unsorted was 72.6% Bad

28 Value Added Inspection & Metrology Stages Via Inspection Via Metrology Ø Process Monitor Bump Metrology and Inspection Back RDL Ball Attach Stack Dicing d (patentpending) Bumping Stacking Wafer-on-wafer Die-on-wafer Bonded Wafer inspection RDL / Bump inspection Post-dicing inspection Via Etching Via Filling Thinning (Back Grinding)

29 Tool Selection Considerations Detection ability the Truth, the whole Truth, and nothing but Versatility and flexibility Meet evolving needs Implement compatible tools along the line, around the world Fully integrated 2D + 3D in single platform High throughput Tool matching Factory support and customization

30 In Summary: Integration Yield loss costs rise with integration level Inspection data (wafer maps, ADC, metrology) support APC/AEC Optical inspection helps turn KG-Die into KG-Package

31 Thank You