ECE260B CSE241A Winter Tapeout. Website:

Transcription

1 ECE260B CSE241A Winter 2007 Tapeout Website: ECE 260B CSE 241A Tapeout 1

2 Tapeout definition What is the definition of the tapeout? There is no standard definition for the tapeout : - Generally speaking the tapeout is associated with the final verification tasks performed before the GDSII/OASIS design database is shipped to the foundry. What are the minimum requirements for a design database to be tapeout? From the foundry prospective: - Can be manufactured : DRC correct - To be functional in the process window. From the design house prospective: - The design to be functional (in spec) across PVT - Can be manufactured: DRC, LVS correct ECE 260B CSE 241A Tapeout 2

3 Tapeout definition Tapeout classification based on design type: Digital tapeout Analog (Mix-Signal/RF) tapeout System on chip: Digital +Analog RF MEMS (Micro-Electro-Mechanical-Systems) Design classification based on system/package type: System on package (SOP) Package on package (POP) Wirebond package Flip-chip package ECE 260B CSE 241A Tapeout 3

4 Tapeout implementation tasks Tapeout implementation tasks: Chip assembly Seal ring generation Chip ID/Revision ID/Hardware version generation (if necessary) GDSII data prep: - Redundant via insertion (if necessary) - Alignment markers insertion - Dummy fill generation (if necessary) - OPC shape enhancer generation (if necessary) Post-tapeout database management tasks: Database archiving Quality metrics generation reports Statistics reports generation ECE 260B CSE 241A Tapeout 4

5 Tapeout implementation tasks Seal ring insertion: All the mask layers used in the design are in the seal ring ECE 260B CSE 241A Tapeout 5

6 Tapeout verification tasks Digital tapeout verification tasks: Equivalence checking signoff Timing/Signal integrity signoff Power signoff Voltage drop signoff Physical verification signoff EMI (Electromagnetic Interference) sign-off for SOC/SOP Yield signoff (Design for manufacturing DFM) Analog tapeout verification tasks: Analog functional signoff Physical verification signoff Noise signoff Yield signoff ECE 260B CSE 241A Tapeout 6

7 Equivalence checking signoff For a digital design we need to verify that the final gate level netlist (verilog, vhdl, cdl, mix-netlist) has the same functionality as the source RTL (vhdl, verilog) netlist. Multiple types of checks must be performed: Equivalence checking Structural checks Cross clock domain checks (CDC) Cross power domain checks DFT insertion checks The equivalence checks can be performed: Bottom up flow: HM s -> Top Top: fully hierarchical RTL Netlist Gate level Final Netlist ECE 260B CSE 241A Tapeout 7

8 Timing/signal integrity signoff Based on STA + SI (Crosstalk, Glitch) tools Two different methodologies: Corner based signoff: - Across PVT guaranty 100% yield for pre-defined performance Speed binning based signoff: - Guaranty functionality across PVT - The parts are binned for performance across process window Functional corners for signoff: Hold time (min delay) : Guaranty functionality Setup time (max delay) : Guaranty performance Corner based timing signoff: Corners + OCV SSTA: Not well defined production flow. ECE 260B CSE 241A Tapeout 8

9 Timing/signal integrity signoff Corner definition: Process corners: - Front end of the line: FF, TT,SS - Back end of the line: Cw, RCw, Nom, Cb, RCb Temperature: -40C, 25C, 125C Voltage: - Min voltage - Nominal voltages: V1, V2, V3, - Max voltage Modes for signoff: Functional 1, Functional 2, Scan 1, Scan2, Modern STA tools perform MM-MC analysis. ECE 260B CSE 241A Tapeout 9

10 Timing/signal integrity signoff The results of the STA analysis are highly dependent on: Timing constraints (SDC as an industry standard) Corner definition Library modeling SPEF, BEOL RC parasitics Crosstalk/Noise engine and tool settings (filters) Voltage drop induced delay Sign off flow Flat - Flat SPEF. Flat netlist. One complete SDC. Hierarchical : - ETM models (Extracted timing models) - ILM models (Interface logic models) ECE 260B CSE 241A Tapeout 10

11 Power signoff In modern UDSM designs the power envelope is the limiting factor for performance Power: Active power: K1 X CV²f Leakage power: - F{P,V,T}, - Multiple components: Sub-threshold, GIDL, DIBL, Gate leakage Power signoff must be performed: To validate the active power budgeting To enable dynamic voltage drop vectorless analysis To guaranty across PVT standby time Different types of power analysis: Vectorless active power analysis: average power VCD based analysis: average power True time VCD analysis : instantaneous power ECE 260B CSE 241A Tapeout 11

12 Power signoff Power analysis: Performed for all the timing corners Performed for the power corners Shares the timing constraints with the STA signoff Multi power modes, multi corner analysis: Validate the clock gating implementation Validate the system power modes Active power prediction correlates well with silicon data. Leakage power prediction must be performed across PVT. The bounds of the leakage power (min, max), correlates with the silicon data, only if the corner spice models and the silicon data correlate. For signoff the nominal process corner is used as reference. ECE 260B CSE 241A Tapeout 12

13 Voltage drop signoff Multiple types of voltage drop analysis: Static IR drop EM (electromigration) signoff Dynamic IR drop: - Vectorless dynamic IR drop - VCD dynamic IR drop - True time VCD dynamic IR Voltage drop signoff with RLC package information. For low power designs: Multi voltage island analysis Dynamic, transient rush current analysis Multi mode voltage drop signoff: Functional modes (case analysis) Scan mode ECE 260B CSE 241A Tapeout 13

14 Voltage drop signoff Two types of voltage drop failures: Hard failure: VDD-VSS < min(vdd-vss)spec Soft failure: - Voltage drop induced skew variability - Voltage drop induced delay EM power mesh failure (over time, burn in) Package induced voltage drop failure For RF designs and Digital-RF/Mixed signal SOC s we can have package coupled with substrate noise induced functional failure. Dynamic voltage scaling functionality must be validated during voltage drop signoff for low power designs which employ this design technique. ECE 260B CSE 241A Tapeout 14

15 Voltage drop signoff Multi power domain design in 65nm (DEF view) ECE 260B CSE 241A Tapeout 15

16 Voltage drop signoff Static IR drop voltage drop map: 8mV max static voltage drop ECE 260B CSE 241A Tapeout 16

17 Voltage drop signoff P/G mesh total resistance instance map (VDD, GND) ECE 260B CSE 241A Tapeout 17

18 Voltage drop signoff Instance power map. ECE 260B CSE 241A Tapeout 18

19 Voltage drop signoff Voltage drop static IR histogram ECE 260B CSE 241A Tapeout 19

20 Voltage drop signoff Dynamic IR: worst voltage drop over tw. without package data 40mV max average voltage drop ECE 260B CSE 241A Tapeout 20

21 Voltage drop signoff Dynamic IR: worst voltage drop over tw. with package data 50mV max average voltage drop ECE 260B CSE 241A Tapeout 21

22 Voltage drop signoff Voltage drop dynamic IR histogram (no package) ECE 260B CSE 241A Tapeout 22

23 Voltage drop signoff Total instantaneous current without package data: Vddcx_1, vddcx_2, vssx_0 ECE 260B CSE 241A Tapeout 23

24 Voltage drop signoff Total instantaneous current with package data: Vddcx_1, vddcx_2, vssx_0 ECE 260B CSE 241A Tapeout 24

25 Physical verification signoff Multiple physical verification tasks must be performed to guaranty the manufacturability and functionality of a design: DRC (design rule checks) LVS (layout versus schematic/netlist) ERC (electrical rule checks) Softcheck connection verification Compare (XOR) Mask layers integrity checks. To transfer the database to the Foundry the database must be encrypted (PGP). Foundry will perform after receiving the encrypted db: DRC Mask db. integrity check. ECE 260B CSE 241A Tapeout 25

26 Physical verification signoff DRC verification: Top level DRC deck provided by the foundry: - Check all the core rules - Check all the Pad/ESD rules - Check density/slotting rules - Check the seal ring rules Binary pass/fail decision Distributed CPU runs. Parallel runs grouped per set of layers. Requires waiver methodology: - Very seldom the top level DRC is 100% clean. - The IP s were developed 6 months before the tapeout and a different DRC deck was used. - Some rules are not coded properly (false errors) - Some rules applies only for specific IP s (bit cells) - For density rules some errors are marginal. ECE 260B CSE 241A Tapeout 26

27 Physical verification signoff DRC verification: DRC verification requires consistency: - Same errors flagged in the design side must be flagged in the foundry side. - All the waivers MUST be approved by the foundry. - Has a direct impact in the tapeout cycle (high visibility). - The foundry data-prep and mask making process will not start until database is DRC clean. The DRC results MUST be tool independent and database hierarchy independent. LVS verification: Is performed only in the design side. The netlist is not transferred to the foundry. Transistor level verification which will guaranty that the GDSII database represents the design netlist. Mandatory step before the database is hand off to the foundry. ECE 260B CSE 241A Tapeout 27

28 Physical verification signoff LVS verification: Multiple step process: - Netlist translation: Gate level physical verilog to transistor level cdl or spice. - Layout db. translation to GDSII/CIF/OASIS. - Crosscheck GDSII vs. CDL Netlist using design house LVS deck. Must checks for: - Correct connectivity. Catastrophic connectivity failures: Shorts, opens - Device property matching/miss-matching - Device property types. - LVS MUST be clean (no waivers) Hierarchical LVS is the only option to perform LVS verification for databases with hundred of millions of devices in UDSM process nodes (0.13u ->90nm ->65nm ->45nm ->32nm). Database hierarchy and the quality of the LVS deck, has a major impact in the running time and the cycle time for LVS database debugging. ECE 260B CSE 241A Tapeout 28

29 Physical verification signoff ERC (electrical rule checking) Performs structural electrical rule verification using the GDSII database Very important for low power designs which employs multiple voltage domains. Level shifter verification and cross power domain checks are performed during ERC. Very slow due to the fact that the connectivity is extracted flat. The only check which will guaranty for designs implemented in double gate and triple gate process with multi voltage domains the reliability of the product. Checks for: - Devices connected between power and ground - Devices connected at the wrong power domain - Shorts, opens - Latch-up rules - Wrong well connections. - Incorrect substrate isolations ECE 260B CSE 241A Tapeout 29

30 Physical verification signoff Softcheck verifications: Basic verification which will check that no power/ground connection is done STANDALONE trough the substrate (nwell/pwell). All the P/G connection must be propagated from the P/G pads (bumps) trough the metal power mesh to the devices. Compare verification: XOR verification is performed between the design GDSII database used during LVS and the foundry GDSII database used during DRC. The two databases may be different because different CAD layers are used during design process for device identification, which are not supported by the foundry. Different map files are used to stream out the LVS GDSII and the DRC GDSII database. However only the DRC GDSII database is send to the foundry. Mask layers integrity check, verifies that only the expected mask layers are in the database which is send to the foundry. ECE 260B CSE 241A Tapeout 30

31 Yield signoff Performed mainly by the fabless, fablite design houses. Not a standard verification flow in the industry. Perform the following analysis: CAA analysis at the chip level. (critical area analysis) Litho simulation and verification across process window CMP analysis. (Chemical Mechanical Planarization) Parametric yield analysis (SSTA) Build knowledge database. Perform silicon to design correlation post tapeout when the silicon is coming back from the foundry. ECE 260B CSE 241A Tapeout 31

32 EMI signoff Parallel process with the tapeout verification. Perform EMI analysis at the system level considering the power model of the silicon die, the package RLC model and the board RLC model. Required for wireless and high speed applications. Time consuming process which requires good understanding of the overall system behavior. Drives changes in the: Clock frequency planning Clock tree implementation PG mesh implementation Package design Board design ECE 260B CSE 241A Tapeout 32

33 Analog: Functional signoff For analog and mixed signal design the functionality of the design relative to a design specification document is validated trough full spice simulation: Full chip spice and mix signal spice analysis using the post LPE spice (cdl) netlist is performed: - Transient analysis - Sensitivity analysis - Monte Carlo analysis - AC analysis - PVT corner based analysis - Mismatch analysis - Spice analysis with RLC substrate information - Spice analysis with PG mesh RLC extracted netlist, RLC substrate information and RLC package information. ECE 260B CSE 241A Tapeout 33

34 Noise/Jitter signoff Noise analysis must be performed for RF/Mixed signal designs as a mandatory verification step. Yield loss estimation is performed based on this analysis The analysis requires high level of engineering skills and feedback from the product and test teams. The noise/jitter signoff verification methodology is build based on experimental results and simulation data. The methodology is process dependent and is not scalable from one process node to the next one. ECE 260B CSE 241A Tapeout 34

35 Database management Mandatory requirement for production designs: Required for maintaining database integrity Enables automated design flow development Required for design handoff during design implementation stage Required for revision control Next revision of a tapeout will use as a starting point the current revision. The database can be queried to extract valuable design information's. Used to support product and test deployment and failure analysis. ECE 260B CSE 241A Tapeout 35

36 Post-tapeout database management All the verification views must be archived in a relevant format and efficient manner. An archive design methodology must be employed for design audits and ISO 9000 (2006) compliance purpose. The archived database has a legal binding value which can be used in courts for Intellectual Property protection. From the archived tapeout design database, quality design metrics are extracted: Number of devices. Type of devices. Area of the die. Standard cell utilization. Memory utilization. I/O utilization. Routing resource utilization per routing layer. Estimated active power per functional modes. Estimated leakage power per functional modes. ECE 260B CSE 241A Tapeout 36

37 Quality metrics and design statistics Quality metrics and design statistics: Tapeout cycle time Implementation cycle time (per design step/task) Hardware utilization: number of CPU s/task Software (license) utilization Total amount of hard disk allocated to the project Number of engineers/week/task Number of mask layers Total cost/revision Number of revisions Number of design hardware bugs/revision Design quality metrics: - CMP uniformity. Metal density uniformity. Poly pitch distribution. - DFM score. CAA score. LPC score. Etc - Timing slack distribution. Etc. ECE 260B CSE 241A Tapeout 37

38 Tapeout completion ECE 260B CSE 241A Tapeout 38