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1 Florida State University Libraries Electronic Theses, Treatises and Dissertations The Graduate School 2010 FPGA Implementation of Digital Filters Using MCM Abhijit Patil Follow this and additional works at the FSU Digital Library. For more information, please contact

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65 5 7/// library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity matlabfilter is Port ( clk : in STD_LOGIC; e : in STD_LOGIC_VECTOR (17 downto 0); x : in STD_LOGIC_VECTOR (15 downto 0); y : out STD_LOGIC_VECTOR (17 downto 0)); end matlabfilter; architecture Behavioral of matlabfilter is -- Add Signal Declarations signal t1_sig : std_logic_vector(15 downto 0); signal t2_sig : std_logic_vector(17 downto 0); signal t3_sig : std_logic_vector(13 downto 0); signal t4_sig : std_logic_vector(15 downto 0); signal t5_sig : std_logic_vector(13 downto 0); signal t6_sig : std_logic_vector(13 downto 0); signal t7_sig : std_logic_vector(13 downto 0); signal t8_sig : std_logic_vector(15 downto 0); signal t9_sig : std_logic_vector(11 downto 0); signal t10_sig : std_logic_vector(11 downto 0); signal t11_sig : std_logic_vector(15 downto 0); signal t12_sig : std_logic_vector(16 downto 0); signal t13_sig : std_logic_vector(15 downto 0); signal t14_sig : std_logic_vector(15 downto 0); signal t15_sig : std_logic_vector(11 downto 0); signal t16_sig : std_logic_vector(12 downto 0); signal t17_sig : std_logic_vector(13 downto 0); signal t18_sig : std_logic_vector(14 downto 0); signal t19_sig : std_logic_vector(15 downto 0); signal t20_sig : std_logic_vector(16 downto 0); signal t21_sig : std_logic_vector(17 downto 0); BB

66 signal t22_sig : std_logic_vector(17 downto 0); signal t23_sig : std_logic_vector(17 downto 0); signal t24_sig : std_logic_vector(17 downto 0); signal t25_sig : std_logic_vector(17 downto 0); signal t26_sig : std_logic_vector(17 downto 0); -- Shift Register Type Declarations type shiftreg_t3_2 is array (0 to 1) of std_logic_vector(12 downto 0); type shiftreg_t4_3 is array (0 to 2) of std_logic_vector(14 downto 0); type shiftreg_t9_18 is array (0 to 17) of std_logic_vector(10 downto 0); type shiftreg_t10_2 is array (0 to 1) of std_logic_vector(10 downto 0); type shiftreg_t11_2 is array (0 to 1) of std_logic_vector(15 downto 0); type shiftreg_t15_30 is array (0 to 29) of std_logic_vector(11 downto 0); type shiftreg_t16_43 is array (0 to 42) of std_logic_vector(12 downto 0); type shiftreg_t17_37 is array (0 to 36) of std_logic_vector(13 downto 0); type shiftreg_t18_33 is array (0 to 32) of std_logic_vector(14 downto 0); type shiftreg_t19_26 is array (0 to 25) of std_logic_vector(15 downto 0); type shiftreg_t21_6 is array (0 to 5) of std_logic_vector(17 downto 0); -- Register Signal Declarations signal t1 : std_logic_vector(15 downto 0) := " "; signal t2 : std_logic_vector(17 downto 0) := " "; signal t3 : shiftreg_t3_2 := ( " ", " "); signal t4 : shiftreg_t4_3 := ( " ", " ", " "); signal t5 : std_logic_vector(12 downto 0) := " "; signal t6 : std_logic_vector(12 downto 0) := " "; signal t7 : std_logic_vector(12 downto 0) := " "; signal t8 : std_logic_vector(15 downto 0) := " "; signal t9 : shiftreg_t9_18 := ( " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", BH

67 signal t10 : shiftreg_t10_2 := ( " ", " ", " ", " ", " ", " "); " ", " "); signal t11 : shiftreg_t11_2 := ( " ", " "); signal t12 : std_logic_vector(15 downto 0) := " "; signal t13 : std_logic_vector(15 downto 0) := " "; signal t14 : std_logic_vector(15 downto 0) := " "; signal t15 : shiftreg_t15_30 := ( " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " "); BA

68 signal t16 : shiftreg_t16_43 := ( signal t17 : shiftreg_t17_37 := ( " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " "); " ", B@

69 signal t18 : shiftreg_t18_33 := ( " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " "); " ", " ", " ", " ", " ", " ", " ", " ", " ", B<

70 signal t19 : shiftreg_t19_26 := ( " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " "); " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", H-

71 " ", " ", " ", " ", " "); signal t20 : std_logic_vector(16 downto 0) := " "; signal t21 : shiftreg_t21_6 := ( " ", " ", " ", " ", " ", " "); signal t22 : std_logic_vector(17 downto 0) := " "; signal t23 : std_logic_vector(17 downto 0) := " "; signal t24 : std_logic_vector(17 downto 0) := " "; begin -- Process to register adder outputs and implement shift registers reg_logic : process(clk) begin if (rising_edge(clk)) then t1 <= x; t3 <= t3_sig(t3_sig'length-1 downto 1) & t3(0 to 1-1); t4 <= t4_sig(t4_sig'length-1 downto 1) & t4(0 to 2-1); t5 <= t5_sig(t5_sig'length-1 downto 1); t6 <= t6_sig(t6_sig'length-1 downto 1); t7 <= t7_sig(t7_sig'length-1 downto 1); t8 <= t8_sig; t9 <= t9_sig(t9_sig'length-1 downto 1) & t9(0 to 17-1); t10 <= t10_sig(t10_sig'length-1 downto 1) & t10(0 to 1-1); t11 <= t11_sig & t11(0 to 1-1); t12 <= t12_sig(t12_sig'length-1 downto 1); t13 <= t13_sig; t14 <= t14_sig; t15 <= t15_sig & t15(0 to 29-1); t16 <= t16_sig & t16(0 to 42-1); t17 <= t17_sig & t17(0 to 36-1); t18 <= t18_sig & t18(0 to 32-1); t19 <= t19_sig & t19(0 to 25-1); t20 <= t20_sig; t21 <= t21_sig & t21(0 to 5-1); t22 <= t22_sig; t23 <= t23_sig; t24 <= t24_sig; H

72 end if; end process; y <= t25_sig; begin -- Process to register adder outputs and implement shift registers reg_logic : process(clk) begin if (rising_edge(clk)) then t1 <= x; t3 <= t3_sig(t3_sig'length-1 downto 1) & t3(0 to 1-1); t4 <= t4_sig(t4_sig'length-1 downto 1) & t4(0 to 2-1); t5 <= t5_sig(t5_sig'length-1 downto 1); t6 <= t6_sig(t6_sig'length-1 downto 1); t7 <= t7_sig(t7_sig'length-1 downto 1); t8 <= t8_sig; t9 <= t9_sig(t9_sig'length-1 downto 1) & t9(0 to 17-1); t10 <= t10_sig(t10_sig'length-1 downto 1) & t10(0 to 1-1); t11 <= t11_sig & t11(0 to 1-1); t12 <= t12_sig(t12_sig'length-1 downto 1); t13 <= t13_sig; t14 <= t14_sig; t15 <= t15_sig & t15(0 to 29-1); t16 <= t16_sig & t16(0 to 42-1); t17 <= t17_sig & t17(0 to 36-1); t18 <= t18_sig & t18(0 to 32-1); t19 <= t19_sig & t19(0 to 25-1); t20 <= t20_sig; t21 <= t21_sig & t21(0 to 5-1); t22 <= t22_sig; t23 <= t23_sig; t24 <= t24_sig; y <= t25_sig; end if; end process; -- Adder Tree Description Logic --e <= e1; t2 <= e; t3_sig <= sxt(t2(17 downto 4), 14) - sxt(t2(17 downto 9), 14); t4_sig <= sxt(t2(17 downto 3), 16) + sxt(t2(17 downto 11), 16); t5_sig <= sxt(t3(0)(12 downto 0), 14) + sxt(t3(0)(12 downto 1), 14); t6_sig <= sxt(t5(12 downto 1), 14) + sxt(t3(1)(12 downto 0), 14); t7_sig <= sxt(t6(12 downto 0), 14) + sxt(t4(2)(14 downto 1), 14); t8_sig <= sxt(t2(17 downto 2), 16); H1

73 t9_sig <= sxt(t3(0)(12 downto 2), 12) + sxt(t8(15 downto 8), 12); t10_sig <= sxt(t3(0)(12 downto 4), 12) + sxt(t8(15 downto 5), 12); t11_sig <= sxt(t4(0)(14 downto 0), 16) + sxt(t8(15 downto 1), 16); t12_sig <= sxt(t3(0)(12 downto 4), 17) + sxt(t8(15 downto 0), 17); t13_sig <= sxt(t5(12 downto 0), 16) + sxt(t11(0)(15 downto 0), 16); t14_sig <= sxt(t13(15 downto 0), 16) + sxt(t10(1)(10 downto 0), 16); t15_sig <= sxt(t9(17)(10 downto 0), 12) - sxt(t6(12 downto 1), 12); t16_sig <= sxt(t3(0)(12 downto 1), 13) + sxt(t15(29)(11 downto 0), 13); t17_sig <= sxt(t16(42)(12 downto 0), 14) - sxt(t7(12 downto 0), 14); t18_sig <= sxt(t17(36)(13 downto 0), 15) - sxt(t13(15 downto 2), 15); t19_sig <= sxt(t18(32)(14 downto 0), 16) - sxt(t12(15 downto 0), 16); t20_sig <= sxt(t14(15 downto 0), 17) + sxt(t19(25)(15 downto 0), 17); t21_sig <= sxt(t20(16 downto 0), 18) - sxt(t11(1)(15 downto 0), 18); t22_sig <= sxt(t2(17 downto 0), 18) + sxt(t2(17 downto 2), 18); t23_sig <= sxt(t1(15 downto 0), 18) + sxt(t21(5)(17 downto 0), 18); t24_sig <= sxt(t23(17 downto 0), 18) - sxt(t2(17 downto 4), 18); t25_sig <= sxt(t24(17 downto 0), 18) - sxt(t22(17 downto 0), 18); end Behavioral; H:

74 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; 51 7/ / entity HPFilter is port( xt: in std_logic_vector(15 downto 0); yt : out std_logic_vector(31 downto 0); clk, reset: in std_logic); end HPFilter; architecture Behavioral of HPFilter is constant L:integer:=198; constant o16:std_logic_vector(15 downto 0):=" "; constant o32:std_logic_vector(31 downto 0):=" "; type vec is array (0 to L) of std_logic_vector(15 downto 0); type vec1 is array (0 to L) of std_logic_vector(31 downto 0); type vect1 is array (0 to L-1) of std_logic_vector(31 downto 0); function lut2(data_in: std_logic_vector(15 downto 0)) return vec1 is VARIABLE Y: vec1; VARIABLE w1,w16,w17,w128,w111,w32,w31,w124,w141,w4512,w4653,w144384,w ,w2048,w2079,w16632,w16633,w7104, w151519,w28416,w123103,w37224,w160327,w32768,w118751,w66532, w52219,w14208,w288830: std_logic_vector(31 downto 0); begin w1 := SXT(data_in,32); w16 := (SHL(w1,"100")); H;

75 w17 := w1 + w16; w128 := (SHL(w1,"111")); w111 := w128 - w17; w32 := (SHL(w1,"101")); w31 := w32 - w1; w124 :=(SHL(w31,"010")); w141 := w17 + w124; w4512 := (SHL(w141,"101")); w4653 := w141 + w4512; w := (SHL(w1,"1010")); w := w31 + w144384; w2048 := (SHL(w1,"1011")); w2079 := w31 + w2048; w16632 := (SHL(w2079,"0011")); w16633 := w1 + w16632; w7104 := (SHL(w111,"0110")); w := w w7104; w28416 := (SHL(w111,"1000")); w := w w28416; w37224 := (SHL(w4653,"0011")); w := w w37224; w32768 := (SHL(w1,"1111")); w := w w32768; w66532 := (SHL(w16633,"0010")); w52219 := w w66532; w37224 := o32 - w37224; w14208 := (SHL(w111,"0111")); w14208 := o32 - w14208; w := o32 - w160327; w := (SHL(w144415,"0001")); Y :=(0=> w37224, 1 => w52219, 2 => w66532, 3 => w14208, 4 =>160327, 5 => w288830, 6 => w160327, 7 => w14208, 8 => w66532, 9 => w52219, 10 => w37224, others=>o32); return Y; END lut2; BEGIN process(clk) variable x : std_logic_vector(15 downto 0); variable ym:vec1; variable v:vect1; begin if reset='1' then x:=o16; ym:=(others=>o32); HB

76 v:=(others=>o22); yt<=o32; elsif clk'event and clk='1' then x:=xt; ym:=lut2(x); yt<=v(0)+ym(0); for k in 0 to L-2 loop v(k):=v(k+1)+ym(k+1); end loop; v(l-1):=ym(l); end if; end process; end Behavioral; HH

77 7/+/ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity HP_filter_24 is port( xt: in std_logic_vector(15 downto 0); yt : out std_logic_vector(31 downto 0); clk, reset: in std_logic); end HP_filter_24; architecture Behavioral of HP_filter_24 is constant L:integer:=24; constant o16:std_logic_vector(15 downto 0):=" "; constant o32:std_logic_vector(31 downto0):=" "; type vec is array (0 to L) of std_logic_vector(15 downto 0); type vec1 is array (0 to L) of std_logic_vector(31 downto 0); type vect1 is array (0 to L-1) of std_logic_vector(31 downto 0); function lut2(data_in: std_logic_vector(15 downto 0)) return vec1 is VARIABLE Y: vec1; variable w1,w8,w7,w16,w23,w64,w41,w56,w79,w184,w177,w316,w275,w2048,w2089,w44 8,w449,w393,w46,w495,w1796,w1301,w47104,w47183,w45882,w22941,w7184, w9273,w9548,w2387,w164,w632,w1618,w1619,w708,w990,w4774,w8356: std_logic_vector(31 downto 0); begin -----Adder Logic w1:=sxt(data_in,32); w8:=(shl(w1,"011")); w7:= w8 - w1; w16:=(shl(w1,"100")); w23:= w7 + w16; HA

78 w64:=(shl(w1,"110")); w41:=w64 - w23; w56:=(shl(w7,"011")); w79:= w23+w56; w184:=(shl(w23,"011")); w177:=w184-w7; w316:=(shl(w79,"010")); w275:=w316-w41; w2048:=(shl(w1,"1011")); w2089:=w41+w2048; w448:=(shl(w7,"110")); w449:=w1+w448; w56:=(shl(w7,"011")); w393:=w449-w56; w46:=(shl(w23,"001")); w495:=w449+w46; w1796:=(shl(w449,"010")); w1301:=w1796-w495; w47104:=(shl(w23,"1011")); w47183:=w79+w47104; w45882:=w47183-w1301; w22941:=(shr(w45882,"001")); w7184:=(shl(w449,"100")); w9273:=w2089+w7184; w9548:=w275+w9273; w2387:=(shr(w9548,"010")); w164:=(shl(w41,"010")); w184:=(shl(w23,"011")); w7:=o32-w7; w393:=o32-w393; w632:=(shl(w79,"011")); w632:=o32-w632; w275:=o32-w275; w708:=(shl(w177,"010")); w990:=(shl(w495,"001")); w990:=o32-w990; w4774:=(shl(w2387,"001")); w4774:=o32-w4774; w8356:=(shl(w2089,"010")); w8356:=o32-w8356; Y:=(0=>w164, 1=>w184, 2=>w7, 3=>w393, 4=>w632, 5=>w275, 6=>w708, 7=>w1619, 8=>w1301, 9=>w990, 10=>w4774, 11=>w8356, 12=>w22941, 13=>w8356, 14=>w4774, 15=>w990, 16=>w1301, 17=>w1618, 18=>w708, H@

79 19=>w275, 20=>w632, 21=>w393, 22=>w7, 23=>w184, 24=>w164, others=>o32); return Y; END lut2; BEGIN process(clk) variable x : std_logic_vector(15 downto 0); variable ym:vec1; variable v:vect1; begin if reset='1' then x:=o16; ym:=(others=>o32); v:=(others=>o32); yt<=o32; elsif clk'event and clk='1' then x:=xt; ym:=lut2(x); yt<=v(0)+ym(0); for k in 0 to L-2 loop v(k):=v(k+1)+ym(k+1); end loop; v(l-1):=ym(l); end if; end process; end Behavioral; H<

80 7/+ / library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity HP_50_mcm is port( xt: in std_logic_vector(15 downto 0); yt : out std_logic_vector(31 downto 0); clk, reset: in std_logic); end HP_50_mcm; architecture Behavioral of HP_50_mcm is constant L:integer:=50; constant o15:std_logic_vector(15 downto 0):=" "; constant o32:std_logic_vector(31 downto 0):=" "; type vec is array (0 to L) of std_logic_vector(15 downto 0); type vec1 is array (0 to L) of std_logic_vector(31 downto 0); type vect1 is array (0 to L-1) of std_logic_vector(31 downto 0); function lut2(data_in: std_logic_vector(15 downto 0)) return vec1 is VARIABLE Y: vec1; variable w1,w4,w3,w5,w8,w9,w24,w23,w48,w43,w45,w80,w85,w144,w141,w384,w387,w1 72,w217,w344,w353,w360,w357,w368,w413,w564,w587,w868,w1009,w1815,w61 44,w5731,w4512,w4159,w1736,w2423,w40,w4199,w_3,w16,w72,w36,w79,w180, w10,w826,w1412,w4846,w8398,w22924:std_logic_vector(31 downto 0); begin ----adder graph logic w1:= SXT(data_in,32); w4 :=(SHL(w1,"010")); w3:=w4-w1; w4:=(shl(w1,"010")); w5:=w1+w4; w8:=(shl(w1,"011")); w9:=w1+w8; w24:=(shl(w3,"011")); w23:=w24-w1; A-

81 w48:=(shl(w3,"100")); w43:=w48-w5; w48:=(shl(w3,"100")); w45:=w48-w3; w80:=(shl(w5,"100")); w79:=w80-w1; w80:=(shl(w5,"100")); w85:=w80+w5; w144:=(shl(w9,"100")); w141:=w144-w3; w384:=(shl(w3,"111")); w387:=w3+w384; w172:=(shl(w43,"010")); w217:=w45+w172; w344:=(shl(w43,"011")); w353:=w9+344; w360:=(shl(w45,"011")); w357:=w360-w3; w368:=(shl(w23,"100")); w413:=w45+w368; w564:=(shl(w141,"010")); w587:=w23+w564; w868:=(shl(w217,"010")); w1009:=w141+w868; w1736:=(shl(w217,"011")); w1815:=w79+w1736; w6144:=(shl(w3,"1011")); w5731:=w6144-w413; w4512:=(shl(w141,"101")); w4159:=w4512-w353; w1736:=(shl(w217,"011")); w2423:=w4159-w1736; w40:=(shl(w5,"011")); w4199:=w4159+w40; w_3:=o32-w3; w16:=(shl(w1,"100")); w16:=o32-w16; w23:=o32-w23; w72:=(shl(w9,"011")); w36:=(shl(w9,"010")); w79:=o32-w79; w180:=(shl(w45,"010")); w180:=o32-w180; w141:=o32-w141; w10:=(shl(w5,"1010")); w587:=o32-w587; A

82 w868:=(shl(w217,"010")); w868:=o32-w868; w360:=(shl(w45,"011")); w360:=o32-w360; w826:=(shl(w413,"001")); w1412:=(shl(w353,"010")); w1009:=o32-w1009; w4846:=(shl(w2423,"001")); w4846:=o32-w4846; w8398:=(shl(w4199,"001")); w8398:=o32-w8398; w22924:=(shl(w5731,"010")); Y:=(0=>w3, 1=>w3, 2=>w_3, 3=>w16, 4=>w23, 5=>w_3, 6=>w43, 7=>w72, 8=>w36, 9=>w79, 10=>w180, 11=>w141, 12=>w85, 13=>w357, 14=>w387, 15=>w10, 16=>w587, 17=>w868, 18=>w360, 19=>w826, 20=>w1815, 21=>w1412, 22=>w1009, 23=>w4846, 24=>w8398, 25=>w22924, 26=>w8398, 27=>w4846, 28=>w1009, 29=>w1412, 30=>w1815, 31=>w826, 32=>w360, 33=>w868, 34=>w587, 35=>w10, 36=>w387, 37=>w357, 38=>w85, 39=>w141, 40=>w180, 41=>w79, 42=>w36, 43=>w72, 44=>w43, 45=>w_3, 46=>w23, 47=>w16, 48=>w_3, 49=>w3, 50=>w3); return Y; END lut2; begin process(clk) variable x : std_logic_vector(15 downto 0); variable ym:vec1; variable v:vect1; begin if reset='1' then x:=o16; ym:=(others=>o32); v:=(others=>o32); yt<=o32; elsif clk'event and clk='1' then x:=xt; ym:=lut2(x); yt<=v(0)+ym(0); for k in 0 to L-2 loop v(k):=v(k+1)+ym(k+1); end loop; v(l-1):=ym(l); end if; end process; end Behavioral; A1

83 & 7/ ; / library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity HP_FIL_MCM_100 is port( xt: in std_logic_vector(15 downto 0); yt : out std_logic_vector(31 downto 0); clk, reset: in std_logic); end HP_FIL_MCM_100; architecture Behavioral of HP_FIL_MCM_100 is constant L:integer:=100; constant o16:std_logic_vector(15 downto 0):=" "; constant o32:std_logic_vector(31 downto 0):=" "; type vec is array (0 to L) of std_logic_vector(15 downto 0); type vec1 is array (0 to L) of std_logic_vector(31 downto 0); type vect1 is array (0 to L-1) of std_logic_vector(31 downto 0); function lut2(data_in: std_logic_vector(15 downto 0)) return vec1 is VARIABLE Y: vec1; variable w1,w3,w4,w5,w8,w7,w16,w17,w512,w513,w13,w24,w23,w32,w29,w48,w43,w64, w59,w80,w75,w96,w93,w103,w112,w105,w160,w157,w256,w239,w272,w267,w2 8,w485,w128,w151,w357,w416,w393,w928,w927,w1536,w1051, w1068,w1055,w1472,w1455,w4800,w4905,w47616,w45894,w22947,w_3,w10,w2 0,w_29,w_10,w206,w184,w544,w534,w744,w1026,w1940,w8408, w46161: std_logic_vector(31 downto 0); begin w1:=sxt(data_in,32); w4:=(shl(w1,"010")); w3 :=w4-w1; w4 := (SHL(w1,"010")); w5 := w1+w4; w8 := (SHL(w1,"011")); w7 := w8-w1; A:

84 w16 := (SHL(w1,"100")); w17 := w1+w16; w512 :=(SHL(w1,"1001")); w513 := w1+w512; w16 := (SHL(w1,"100")); w13 := w16-w3; w24 := (SHL(w3,"011")); w23 := w24-w1; w32 := (SHL(w1,"101")); w29 := w32-w3; w48 := (SHL(w3,"100")); w43 := w48-w5; w64 := (SHL(w1,"110")); w59 := w64-w5; w80 := (SHL(w5,"100")); w75 := w80-w5; w96 := (SHL(w3,"101")); w93 := w96-w3; w96 := (SHL(w3,"101")); w103 := w7+w96; w112 := (SHL(w7,"100")); w105 := w112-w7; w160 := (SHL(w5,"101")); w157 := w160-w3; w256 := (SHL(w1,"1000")); w239 := w256-w17; w272 := (SHL(w17,"100")); w267 := w272-w5; w28 := (SHL(w7,"010")); w485 := w513-w28; w128 := (SHL(w1,"0111")); w151 := w23+w128; w128 := (SHL(w1,"0111")); w357 := w485-w128; w416 := (SHL(w13,"101")); w393 := w416-w23; w928 := (SHL(w29,"101")); w927 := w928-w1; w1536 := (SHL(w3,"1001")); w1051 := w1536-w485; w1068 := (SHL(w267,"010")); w1055 := w1068-w13; w1472 := (SHL(w23,"110")); w1455 := w1472-w17; w4800 := (SHL(w75,"110")); w4905 := w105+w4800; A;

85 w47616 := (SHL(w93,"1001")); w46161 := w47616-w1455; w45894 := w46161-w267; w22947 := (SHR(w45894,"001")); w_3 :=o32-w3; w7 := o32-w7; w_3 := w_3; w3 := w3; w10 := (SHL(w5,"001")); w20 := (SHL(w5,"010")); w20 := o32-w20; w_29 := o32-w29; w_10 := o32-w10; w_29 := w_29; w105 := o32-w105; w105 := w105; w3 := w3; w206 :=(SHL(w103,"001")); w184 :=(SHL(w23,"011")); w184 := o32-w184; w357 := o32-w357; w239 :=o32-w239; w544 :=(SHL(w17,"101")); w534 := (SHL(w267,"001")); w7 := w7; w744 := (SHL(w93,"011")); w744 := o32-w744; w1026 :=(SHL(w513,"001")); w1026 := o32-w1026; w393 := o32-w393; w1940 := (SHL(w485,"010")); w1055 :=o32-w1055; w4905 := o32-w4905; w8408 := (SHL(w1051,"011")); w8408 := o32-w8408; Y:=(13=>w3,15=>w_3,16=>w7,17=>w_3,18=>w3,19=>w10,20=>w13,22=>w20,23= >w_29,24=>w_10,25=>w29, 26=>w59,27=>w43,28=>w_29,29=>w105,30=>w105,31=>w3,32=>w151,33=>w20 6,34=>w75,35=>w184,36=>w357, 37=>w239,38=>w157,39=>w544,40=>w534,41=>w7,42=>w744,43=>w1026,44=> w393,45=>w927,46=>w1940, 47=>w1455,48=>w1055,49=>w4905,50=>w8408,51=>w22947,52=>w8408,53=>w 4905,54=>w1055,55=>w1455, AB

86 56=>w1940,57=>w927,58=>w393,59=>w1026,60=>w744,61=>w7,62=>w534,63= >w544,64=>w157,65=>w239, 66=>w357,67=>w184,68=>w75,69=>w206,70=>w151,71=>w3,72=>w105,73=>w1 05,74=>w_29,75=>w43,76=>w59, 77=>w29,78=>w_10,79=>w_29,80=>w20,82=>w13,83=>w10,84=>w3,85=>w_3,86 =>w7,87=>w_3,89=>w3, others=>o32); return Y; END lut2; BEGIN process(clk) variable x : std_logic_vector(15 downto 0); variable ym:vec1; variable v:vect1; begin if reset='1' then x:=o16; ym:=(others=>o32); v:=(others=>o32); yt<=o32; elsif clk'event and clk='1' then x:=xt; ym:=lut2(x); yt<=v(0)+ym(0); for k in 0 to L-2 loop v(k):=v(k+1)+ym(k+1); end loop; v(l-1):=ym(l); end if; end process; end Behavioral; AH

87 0 02 &$O=!)R$ S %% && %'((')1--1)A< A & $ R( * % &!$'(('):B1:BB+ 0:2= ' R( S % % & & %'((,) -<A-- 0;2 = ' )(' )G C)R S%% && %'((-) ;A:;AH 0B2 = ' )O=!)(' ) RG4 4 S%% && %'((' 0H2.)> >)R& S"C)<A<)<HB# :<;)1:1:-@ 0A2(' )S! S666! $ ;)B)=<<; 0@2 (' ) S? S)%.& %%.'/001) 2 L;1),<)$<<B 0<2 UL &X, R S.!'((,)L:),1 0-2U>)( >!? G6) R= 4 S %%.3 '((4)L6<(),1 02G( 6 =' ) R( 4 S & "%'((4)$;+ AA

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