Mark Redekopp, All rights reserved. EE 357 Unit 21. Final Review

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1 EE 357 Unit 21 Final Review

2 EE 357 in review A LOOK BACK

3 Where EE 357 Fits CS 101,102,105,201 Programming with highlevel languages (HLL s) like C / C++/ Java EE 101,201 SW Digital hardware (registers, adders, muxes) C / C++ / Java Applications Functional Units (Registers, Adders, Muxes) HW Logic Gates Transistors Voltage / Currents

4 Where EE 357 Fits CS 101,102,105,201 Programming with highlevel languages (HLL s) like C / C++/ Java EE 101,201 Digital hardware (registers, adders, muxes) EE 357 Computer organization and architecture HW/SW System Perspective Topics HW/SW interface System Software Assembly Language Computer Architecture SW HW C / C++ / Java Assembly / Machine Code Logic Gates Transistors Applications OS Processor / Memory / I/O Voltage / Currents Libraries Functional Units (Registers, Adders, Muxes)

5 Where Computer Architecture Fits Embedded Devices + Applications Operating Systems + Compilers IC/VLSI/Digital Design Software Development (Parallel Programming, Memory Hierarchy effects) Computer Architecture New Technology

6 EE 357 in Context Software Development ( CS 303, EE 451?) Embedded Devices + Applications (EE 459L, EE 454L, EE 579, EE 483, EE 434L, BME 302, BME 405L) EE 357 EE 457 EE 557 EE 653 Operating Systems + Compilers (CS 402 / CS 410) New Technology (EE 337L) IC/Digital Design (EE 477L, EE 438L)

7 Architecture Multicore Mark Redekopp, All rights reserved Power, multithreaded/multicore, parallel programming Reliability Smaller transistors leads to reliability issues (bits can be flipped accidentally, transistors can break, etc.) How do we add reliability into the architecture Mobile and network-centric Low power, software/hardware decomposition Architectural Concepts Make the common case fast (Amdahl s law) Concept of caching (save your work and reuse it next time you need it) applies to almost anything (SW programs can cache their results, too), not just cache memory Often easier to tackle throughput rather than latency

8 Digital Design & VLSI Build the structures and implement the algorithms that architects, signal processing, and communications engineers develop given power, area, and performance constraints Focus on SoC (System-on-chip) Combine processor core + IP cores => Embedded System Learn Verilog and/or VHDL Understand advantages of FPGA vs. custom chips Learn to program (likely in C/C++ or maybe Python) Take EE 477L (VLSI design) as a technical elective

9 Programming Understand the hardware architecture you are working on and how to take advantage of it Effects of Cache Sequential access is best Static allocation (fewer pointer based data structures) is often better Cluster accesses to same data don t use it, do a lot of other stuff, then reuse it if you don t have to Thread Level Parallelism (Create parallel tasks) OpenMP, MPI, Native Threads Data Level Parallelism (SIMD) Compiler options, intrinsics Understand the cost of parallelization Amdahl s law Cost of communications/synchronization

10 Embedded Systems Complex systems which integrate and interface to many I/O devices can be cheaply and efficiently made with programmable microcontrollers Identify your I/O and computational needs and select an appropriate microcontroller/microprocessor

11 Microcontrollers Freescale ( Atmel AVR ( PIC ( ARM (

12 Embedded Systems Devices Parallel I/O Character LCD s LED s, Switches, Pushbuttons Serial I/O LCD s (IIC) GPS (RS-232) USB Bluetooth (direct or RS-232) Wireless (direct or RS-232) Real Time Clocks (IIC) Servo Motors Analog Inputs Pressure, temperature, biometric sources Touch screens/sensors Web sites Digikey.com Jameco.com Sparkfun.com

13 REVIEW FOR FINAL Mark Redekopp, All rights reserved

14 Final Jeopardy Binary Brainteasers Performance Puzzles Memory Madness Processor Predicaments Programming Pickles

15 Binary Brainteaser 100 Given the binary string , what would its decimal equivalent be assuming a 2 s complement representation? ANSWER: = -115

16 Binary Brainteaser 200 Assuming the 12-bit IEEE shortened FP format, what is the decimal equivalent of the following number? ANSWER: *2 3 = =

17 Binary Brainteaser 300 Under what conditions does overflow occur in signed arithmetic (addition/subtraction)? ANSWER: when p+p=n or n+n=p

18 Binary Brainteaser 400 Under what conditions does overflow occur in unsigned arithmetic (addition/subtraction)? ANSWER: If adding, when Cout=1, if subtracting, when Cout=0

19 Binary Brainteaser 500 Given the following normalized FP number, what would the result be after using the round-to-nearest method? * 2 5 ANSWER: Round to 0 in the LSB, so round up to *2 5

20 Performance Puzzle 100 What is the best metric for performance measurement (i.e. not subject to manipulation or misleading results)? ANSWER: Time (not rates like MIPS, CPI, etc.)

21 Performance Puzzle 200 What are the three basic components of the performance equation learned in class? ANSWER: Instruction Count, Average CPI, Clock cycle time/period

22 Performance Puzzle 300 Which of the three components of the performance equation would be affected by the choice of compiler? ANSWER: Instruction Count and probably CPI since the instruction mix it selects will affect the CPI

23 Performance Puzzle 400 State Amdahl s law for speedup? ANSWER: Speedup = 1 / [frac. unenhanced + frac. enhanced /improvement factor]

24 Performance Puzzle 500 Using Amdahl s law, if 50% of the instructions of a program can be sped up by a factor of 2, will the speedup of the program be 1 / 0.75 = 4/3?? ANSWER: No, because the 50% represents instruction count and not time those instruction require. Those 50% instructions may take 2 CPI while the other 50% instruction average 10 CPI. Thus improving them by two times will not yield the 4/3 speedup.

25 Memory Madness 100 SDRAM will allow consecutive (columns/rows/banks) to be read/written in bursts? ANSWER: Columns

26 Memory Madness 200 In a 4-way set associative cache with 512 total blocks, how many bits will be used to index the set (i.e. the set field of the address breakdown)? ANSWER: 512/4 = 128 sets => 7-bits

27 Memory Madness 300 DRAM (may / will not) lose its content even though power is continuously provided and in general is (faster / slower) to access than SRAM

28 Memory Madness 400 In general, caches closer to the processor core are (smaller / larger) so that they can be faster. In addition, they usually have a (lower / higher) degree of associativity?

29 Memory Madness 500 In a 4-way set-associative cache with 128 sets, the worst cache performance will occur when all accesses map to different blocks in (the same / different) set(s) and the earliest an eviction can occur is on the (1 st / 4 th / 5 th / 128 th / 129 th ) block access.

30 Processor Predicaments 100 What is the ideal throughput (IPC) of a pipelined CPU? ANSWER: 1 (1 instruction completing every cycle)

31 Processor Predicaments 200 Name the three kinds of hazards that prevent the pipeline from being kept full? ANSWER: Structural Hazards, Data Hazards, Control Hazards

32 Processor Predicaments 300 What method(s) can be used to solve the following Read-After-Write data hazards/dependencies or at least reduce the associated stall penalty? Forwarding (bypassing) in HW Rearranging instructions (by the compiler)

33 Processor Predicaments 400 Temporary registers are needed in the (single- / multi-) cycle CPU. An example of a temporary register is the (PC / IR).

34 Processor Predicaments 500 The (single- / multi-) cycle CPU architecture implies variable CPI s for different instruction classes and the clock cycle time is set by the longest (state / instruction) delay.

35 Programming Pickles 100 When checking the status of an I/O device one can rely on interrupts or? ANSWER: Polling/Busy looping

36 Programming Pickles 200 Calling a subroutine requires using the (bsr / bra) instruction and will result in the return address being stored (on the stack / in A7)?

37 Programming Pickles 300 The stack frame of a subroutine includes space for three sections of data, what are they? ANSWER: Local variables Saved registers Arguments for subroutines

38 Programming Pickles 400 System calls/traps, interrupts, and error conditions cause breaks in normal program execution. What is the name we give to these events? ANSWER: Exceptions

39 Programming Pickles 500 What is the name we use for software routines associated with an interrupt or other error event? ANSWER: handler routines

40 Cache Operation Example Address Trace R: 0x3c0 W: 0x048 R: 0x3d4 W: 0xb50 Operations Hit Fetch block XX Evict block XX (w/ or w/o WB) Final WB of block XX) Perform address breakdown and apply address trace 2-Way Set-Assoc, N=8, B=8 words Address Tag Set Word Unused 0x3c x x3d xb Processor Access Cache Operation R: 0x3c0 Fetch Block 3c0-3df W: 0x048 Fetch Block f R: 0x3d4 Hit W: 0xb50 Evict f w/ WB, Fetch b40-b5f Mark Redekopp, All rights reserved Done! Final WB of b40-b5f

41 DBNZ on Multicycle CPU Many looping operations require decrementing a counter and branching it the new value is zero Many instructions sets include an instruction that we will term DBNZ (Decrement and Branch if Not Zero) Format: DBNZ $rs, disp Operation: $rs = $rs 1 if $rs /= 0, branch to PC+4+disp Opcode Rs Rt Displacement Mark Redekopp, All rights reserved 6-bits 5-bits 5-bits (copy of Rs) 16-bits

42 PCWrite PC IorD Mark Redekopp, All rights reserved MemRead MemWrite IRWrite Reg Write ALUSelA Modified Datapath for DBNZ PCSource TargetWrite PC[31:28] Target Reg RegDst Sh. Left Addr. Write Data Read Data Memory Instruc[31:26] Instruc[25:0] Instruc. Reg. MemtoReg [25:21] [20:16] [15:11] Read Reg. 1 # Read Reg. 2 # Write Reg. # Write Data Read data 1 Read data 2 Register File 1 [15:0] Sign 16 Extend Sh. Left [5:0] ALU ALUSelB Zero Res. ALU control

43 Multi-cycle CPU FSM w/ DBNZ Reset 0 MemRead ALUSelA=0 IorD=0 IRWrite ALUSelB=01 ALUOp=00 PCSource=00 PCWrite Instruc. Fetch Instruc. Decode + 1 Reg. Fetch ALUSelA=0 ALUSelB=11 ALUOp=00 TargetWrite (Op= JMP ) (Op= BEQ ) ALUSelA=1 ALUSelB=100 ALUOp=01 PCWriteCond PCSource=01 RegDst=0 MemtoReg=0 RegWrite 8 9 ALUSelA=1 ALUSelB=00 PCWrite ALUOp=01 PCSource=10 PCWriteCond PCSource=01 Branch Completion Jump Completion

44 Addressing Modes Review data PTR:.long 0x c.long 0x DAT:.long -1,1 RES:.space 4 RES = MAIN.text MOVEA.L #DAT,A1 A1= MOVEA.L -4(A1),A0 A0= a MOVE.L (A0),D5 D5= c MOVE.L -(A0),D6 D6= A0= e ADD.L OR.L D5,D6 D5,D6 D6= N,Z,V,C= D6= LSL.L #1,D6 D6= MOVE.L D6,RES

45 Addressing Modes Review data PTR:.long 0x c.long 0x DAT:.long -1,1 RES:.space 4 RES = 0x MAIN:.text MOVEA.L #DAT,A1 A1= 0x c MOVEA.L -4(A1),A0 A0= 0x a MOVE.L (A0),D5 D5= 0x c MOVE.L -(A0),D6 D6= 0xffffffff A0= 0x c e ADD.L OR.L D5,D6 D5,D6 D6= 0x N,Z,V,C= 0,1,0,1 D6= 0x LSL.L #1,D6 D6= 0x MOVE.L D6,RES