CSE 2021: Computer Organization Fall 2010 Solution to Assignment # 3: Multicycle Implementation

Transcription

1 CSE 2021: Computer Organization Fall 2010 Solution to Assignment # 3: Multicycle Implementation Note that these questions are taken from the previous final exmas of CSE2021 and should serve as practice questions for multicycle implementation section of the final exam. Question 1 A. We have to modify the existing datapath so that PC + 4 can be written to register 31 (corresponding to $ra) while PC is written with the new jump address. To accomplish this, we expand 1. The multiplexor for RegDst to include 31 as an additional input. With three inputs to the multiplexor, control RegDst should be expanded to 2 bits. To select 31 as the input, we assume that RegDst = The multiplexor for MemtoReg to include PC + 4 as an additional input. With three inputs to the multiplexor, control MemtoReg is expanded to 2 bits. To select PC + 4, we set MemtoReg = 10. The execution steps for the jal instruction are: Step 1: Instruction Fetch: remains unchanged Step 2 Instruction Decode and Register Fetch: remains unchanged Step 3 Execution, Memory Address Computation, Branch, Jump or Jump and Link Completion: jal: Reg[31] = PC + 4; PC = PC[31-28] ( IR[25-0] << 2 ); The datapath for the jal instruction is shown using the bold lines in figure A2.1. B. A new state 10 is added from state 1, such that state 1 state 10 state 0 The control values for this new state are PCWrite, PCSource = 10, RegDst = 10, MemtoReg = 10, and RegWrite. Since RegDst and MemtoReg are now 2 bits, their corresponding values in the other states have to change as well to reflect this enhancement. We show the changes in fig. A3.2 using shaded blocks. C. Based on our result in part (b), the jal instruction will take 3 cycles (state 0 state 1 state 10 state 0). 1

2 Figure A3.1: Datpath for the jal instruction. Note that the RegDst Multiplexer and MemtoReg multiplexer have been modified to include three inputs. The control lines RegDst and MemtoReg are therefore 2-bit buses. 2

3 Fig. A3.2: Finite State Machine diagram that includes the jal instruction. States 4 and 7 are modified as RegDst and MemtoReg are 2-bit controls. State 10 is added as an additional state for the jal instruction. 3

4 Question 2: A. In Fig. 5.38, the states involved in executing beq are states 0, 1, and 8. If we look at states 0, 1 and 8 on the fig. 5.38, we can write out the control signals as seen in each state. Any control signal not mentioned will be deasserted. In state 0, the states asked for have the following values: ALUSrcA = 0, IRWrite is asserted, ALUOp = 00, IorD = 0, and PCSource = 00. The other states set are: ALUSrcB=01, MemRead asserted, PCWrite asserted In state 1, the states asked for have the following values: ALUSrcA = 0, ALUOp = 00, IRWrite is deasserted as are the other signals not shown in the state circle IorD = 0, and PCSource = 00. In state 8, the states asked for have the following values: ALUSrcA = 1, IRWrite is de-asserted, ALUOp = 01, IorD = 0, and PCSource = 01. The other controls mentioned are PCWriteCond= 01, ALUScrB = 00. B. A fault in the control unit forces PCSource to be 0 at all times: This fault will not affect states 0 (instruction fetch) and 1 (instruction decode/register fetch). However during state 8 (branch completion), if a branch is to take place, PCSource stuck at 0 will prevent the branch target address from the ALUOut buffer to be written to PC. The content of PC will be the output of the ALU unit at this time A-B. C. A fault in the control unit forces ALUOp to be 0 at all times: Again, this fault will not affect states 0 (instruction fetch) and 1 (instruction decode/register fetch). However during state 8 (branch completion), in order to determine if a branch is to take place, the ALU will have to perform an equality test by evaluating A B. ALUOp stuck at 0 will cause the ALU to evaluate A + B, instead of A B. The branch will take place incorrectly when A+B = 0. D. A fault in the control unit forces ALUSrcB to be 1 at all times: This fault will not affect state 0 (instruction fetch). During state 1 (instruction decode/register fetch), when the datapath has to compute the branch target address, ALUSrcB stuck at 1 will caused the datapath to pick up the value 4, instead of the branch offset. The resulting branch target address will not be correct. Furthermore, during state 8 (branch completion), in order to determine if a branch is to take place, the ALU will have to perform an equality test by evaluating A B. ALUSrcB stuck at 1 will cause the ALU to evaluate A - 4, instead of A B. This will result in branch taking place only if A is also equal to 4, which is not what was intended. Question 3: A. add $a0, $s0, $t0 there are no errors or anomalies. Register $a0 becomes = 10. B. add $a0, $s0, $t0 There are no errors. It is an anomaly that MemtoReg is set to 0 at all times' but it has no effect on the execution of this instruction. Register $a0 becomes = 10. C. It is an anomaly that MemtoReg is set to 1 in cycles 1 through 3 but this has no effect on the execution of this instruction in these cycles. There is an error in cycle #4 because the instruction is trying to add (add $s0, $t0, $a0) but MemToReg 4

5 is always asserted and this leads to the machine language code for the instruction being stored in $a0. Register $a0 becomes: D. sw $t0, 2($s0) or sw $t0, 2($s0) or sb $t0, 2($s0). Any answer is OK. There are no errors. Since $s0=4, the instruction stores the content of $t0 (i.e. 6) at memory address 2+4 = 6. If this is a sb, byte 6 in DRAM becomes 6. If this is a sh, byte 6 in DRAM becomes 0 and byte 7 becomes 6. If this is a sw, then there is an anomaly because the address (6) is not a multiple of 4. Nevertheless, any of the following answers will be accepted: A mis-aligned exception is thrown. Locations 6,7,8,9 will become: 0,0,0,6 (respectively). Locations 4,5,6,7 will become: 0,0,0,6 (respectively). 5