Computer Science 141 Computing Hardware
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1 Computer Science 4 Computing Hardware Fall 6 Harvard University Instructor: Prof. David Brooks dbrooks@eecs.harvard.edu
2 Upcoming topics Mon, Nov th MIPS Basic Architecture (Part ) Wed, Nov th Basic Computer Performance (/ lecture) Mon, Nov 7 th MIPS Basic architecture (Part, continued) Wed, Nov 9 th MIPS Multi-cycle architecture Mon, Dec 4 th MIPS Pipelining and Hazards (Part ) Wed, Dec 6 th MIPS Pipelining and Hazards (Part ) Mon, Dec th Memory and Caches (Part ) Wed, Dec 3 th Memory and Caches (Part ) Mon, Dec 8 th Advanced Topics (Preview CS46) [MIPS Pipeline Slides adapted from Dave Patterson s UCB CS5 slides and Mary Jane Irwin s CSE33 slides] David Brooks CS4
3 Flash Memory Overview Charge stored on floating gate of special nmos transistor, changes threshold voltage Can erase/store electrically, better than the old EEPROM s (UV-light exposure) David Brooks CS4
4 History of FLASH David Brooks CS4
5 Code vs. File Storage David Brooks CS4
6 Review: Single Cycle Data and Control Path 4 Add Instr[5-] 6 Op Instr[3-6] Control 8 3 PC+4[3-8] Jump Branch Src Add PCSrc Mem MemtoReg MemWrite PC Address Instruction Memory Instr[3-] RegDst Instr[5-] Instr[-6] Instr[5 -] RegWrite Addr Register Addr Data File Write Addr Data ovf zero Address Data Memory Data Instr[5-] Sign 6 Extend 3 control Instr[5-] David Brooks CS4
7 Disadvantages of the Single Cycle Datapath Uses the clock cycle inefficiently the clock cycle must be timed to accommodate the slowest instruction especially problematic for more complex instructions like floating point multiply Is wasteful of area since some functional units must be duplicated since they can not be shared during an instruction execution e.g., need separate adders to do PC update and branch target address calculations, as well as an to do R-type arithmetic/logic operations and data memory address calculations David Brooks CS4
8 Multicycle Implementation Overview Each step in the execution takes clock cycle An instruction takes more than clock cycle to complete Not every instruction takes the same number of clock cycles to complete Multicycle implementations allow functional units to be used more than once per instruction as long as they are used on different clock cycles, as a result only need one memory need only one /adder faster clock rates different instructions to take a different number of clock cycles David Brooks CS4
9 The Multicycle Datapath A High Level View Registers have to be added after every major functional unit to hold the output value until it is used in a subsequent clock cycle PC Address Memory Data (Instr. or Data) IR MDR Addr Register Addr Data File Write Addr Data A B out David Brooks CS4
10 Clocking the Multicycle Datapath System Clock clock cycle MemWrite RegWrite PC Address Memory Data (Instr. or Data) IR MDR Addr Register Addr Data File Write Addr Data A B out David Brooks CS4
11 Break up the instructions into steps where each step takes a cycle while trying to balance the amount of work to be done in each step restrict each cycle to use only one major functional unit At the end of a cycle Multicycle Approach Store values needed in a later cycle by the current instruction in a state element (internal register) not visible to the programmer IR Instruction Register MDR Memory Data Register A and B register file read data registers out output register All (except IR) hold data only between a pair of adjacent clock cycles (so don t need a write control signal) Data used by subsequent instructions are stored in programmer visible state elements (i.e., register file, PC, or memory) David Brooks CS4
12 The Complete Multicycle Data with Control Cond IorD Mem MemWrite MemtoReg IRWrite PCSource Op Control SrcB SrcA RegWrite RegDst PC Address Memory Data (Instr. or Data) IR MDR Instr[3-6] Instr[5-] Instr[5-] Addr Register Addr Data File Write Addr Data Sign Extend 3 Instr[5-] A B 4 3 PC[3-8] zero control 8 out David Brooks CS4
13 Review: Control Controlling the makes use of multiple levels of decoding main control unit generates the Op bits control unit generates control inputs Instr op lw sw beq add subt and or slt funct xxxxxx xxxxxx xxxxxx Op desired action add add subtract add subtract and or slt control input David Brooks CS4
14 ing/writing to Multicycle Approach, con t any of the internal registers or the PC occurs (quickly) at the end of a clock cycle reading/writing to the register file takes ~5% of a clock cycle since it has additional control and access overhead (reading can be done in parallel with decode) Have to add multiplexors in front of several of the functional unit inputs because the functional units are shared by different instruction cycles All operations occurring in one step occur in parallel within the same clock cycle This limits us to one operation, one memory access, and one register file access per step (per clock cycle) David Brooks CS4
15 Instruction Fetch Five Instruction Steps Instruction Decode and Register Fetch R-type Instruction Execution, Memory /Write Address Computation, Branch Completion, or Jump Completion Memory Access, Memory Write Completion or R-type Instruction Completion Memory Completion (Write Back) INSTRUCTIONS TAKE FROM 3-5 CYCLES! David Brooks CS4
16 Step : Instruction Fetch Use PC to get instruction from the memory and put it in the Instruction Register Increment the PC by 4 and put the result back in the PC Can be described succinctly using RTL "Register-Transfer Language IR = Memory[PC]; PC = PC + 4; Can we figure out the values of the control signals? What is the advantage of updating the PC now? David Brooks CS4
17 Datapath Activity During Instruction Fetch Cond IorD Mem MemWrite MemtoReg IRWrite PCSource Op Control SrcB SrcA RegWrite RegDst PC Address Memory Data (Instr. or Data) IR MDR Instr[3-6] Instr[5-] Instr[5-] Addr Register Addr Data File Write Addr Data Sign Extend 3 Instr[5-] A B 4 3 PC[3-8] zero control 8 out David Brooks CS4
18 Datapath Activity During Instruction Fetch Cond IorD Mem MemWrite MemtoReg IRWrite PCSource Op Control SrcB SrcA RegWrite RegDst PC Address Memory Data (Instr. or Data) IR MDR Instr[3-6] Instr[5-] Instr[5-] Addr Register Addr Data File Write Addr Data Sign Extend 3 Instr[5-] A B 4 3 PC[3-8] zero control 8 out David Brooks CS4
19 Fetch Control Signals Settings Start Instr Fetch David Brooks CS4
20 Fetch Control Signals Settings Unless otherwise assigned Start,IRWrite, MemWrite,RegWrite= others= IorD= Mem;IRWrite SrcA= srcb= PCSource,Op= Instr Fetch David Brooks CS4
21 Step : Instruction Decode and Register Fetch Don t know what the instruction is yet, so can only registers rs and rt in case we need them Compute the branch address in case the instruction is a branch RTL: A = Reg[IR[5-]]; B = Reg[IR[-6]]; Out = PC +(sign-extend(ir[5-])<< ); Note we aren't setting any control lines based on the instruction (since we are busy "decoding" it in our control logic) David Brooks CS4
22 Datapath Activity During Instruction Decode Cond IorD Mem MemWrite MemtoReg IRWrite PCSource Op Control SrcB SrcA RegWrite RegDst PC Address Memory Data (Instr. or Data) IR MDR Instr[3-6] Instr[5-] Instr[5-] Addr Register Addr Data File Write Addr Data Sign Extend 3 Instr[5-] A B 4 3 PC[3-8] zero control 8 out David Brooks CS4
23 Datapath Activity During Instruction Decode Cond IorD Mem MemWrite MemtoReg IRWrite PCSource Op Control SrcB SrcA RegWrite RegDst PC Address Memory Data (Instr. or Data) IR MDR Instr[3-6] Instr[5-] Instr[5-] Addr Register Addr Data File Write Addr Data Sign Extend 3 Instr[5-] A B 4 3 PC[3-8] zero control 8 out David Brooks CS4
24 Unless otherwise assigned Start,IRWrite, MemWrite,RegWrite= others= Decode Control Signals Settings IorD= Mem;IRWrite SrcA= srcb= PCSource,Op= Instr Fetch Decode David Brooks CS4
25 Unless otherwise assigned Start,IRWrite, MemWrite,RegWrite= others= Decode Control Signals Settings IorD= Mem;IRWrite SrcA= srcb= PCSource,Op= Instr Fetch Decode SrcA= SrcB= Op= Cond= David Brooks CS4
26 Step 3 (instruction dependent) is performing one of four functions, based on instruction type Memory reference (lw and sw): Out = A + sign-extend(ir[5-]); R-type: Out = A op B; Branch: if (A==B) PC = Out; Jump: PC = PC[3-8] (IR[5-] << ); David Brooks CS4
27 Datapath Activity During Instruction Execute Cond IorD Mem MemWrite MemtoReg IRWrite PCSource Op Control SrcB SrcA RegWrite RegDst PC Address Memory Data (Instr. or Data) IR MDR Instr[3-6] Instr[5-] Instr[5-] Addr Register Addr Data File Write Addr Data Sign Extend 3 Instr[5-] A B 4 3 PC[3-8] zero control 8 out David Brooks CS4
28 Datapath Activity During lw & sw Execute Cond IorD Mem MemWrite MemtoReg IRWrite PCSource Op Control SrcB SrcA RegWrite RegDst PC Address Memory Data (Instr. or Data) IR MDR Instr[3-6] Instr[5-] Instr[5-] Addr Register Addr Data File Write Addr Data Sign Extend 3 Instr[5-] A B 4 3 PC[3-8] zero control 8 out David Brooks CS4
29 Datapath Activity During R-type Execute Cond IorD Mem MemWrite MemtoReg IRWrite PCSource Op Control SrcB SrcA RegWrite RegDst PC Address Memory Data (Instr. or Data) IR MDR Instr[3-6] Instr[5-] Instr[5-] Addr Register Addr Data File Write Addr Data Sign Extend 3 Instr[5-] A B 4 3 PC[3-8] zero control 8 out David Brooks CS4
30 Datapath Activity During beq Execute Cond IorD Mem MemWrite MemtoReg IRWrite PCSource Op Control SrcB SrcA RegWrite RegDst PC Address Memory Data (Instr. or Data) IR MDR Instr[3-6] Instr[5-] Instr[5-] Addr Register Addr Data File Write Addr Data Sign Extend 3 Instr[5-] A B 4 3 PC[3-8] zero control 8 out David Brooks CS4
31 Datapath Activity During j Execute Cond IorD Mem MemWrite MemtoReg IRWrite PCSource Op Control SrcB SrcA RegWrite RegDst PC Address Memory Data (Instr. or Data) IR MDR Instr[3-6] Instr[5-] Instr[5-] Addr Register Addr Data File Write Addr Data Sign Extend 3 Instr[5-] A B 4 3 PC[3-8] zero control 8 out David Brooks CS4
32 Unless otherwise assigned Start,IRWrite, MemWrite,RegWrite= others= Execute Control Signals Settings (Op = lw or sw) IorD= Mem;IRWrite SrcA= srcb= PCSource,Op= Instr Fetch (Op = R-type) (Op = beq) (Op = j) Decode SrcA= SrcB= Op= Cond= Execute David Brooks CS4
33 Unless otherwise assigned Start,IRWrite, MemWrite,RegWrite= others= SrcA= SrcB= Op= Cond= Execute Control Signals Settings (Op = lw or sw) Execute IorD= Mem;IRWrite SrcA= srcb= PCSource,Op= SrcA= SrcB= Op= Cond= Instr Fetch (Op = R-type) SrcA= SrcB= Op= PCSource= Cond (Op = beq) (Op = j) Decode SrcA= SrcB= Op= Cond= PCSource= David Brooks CS4
34 Step 4 (instruction dependent) Memory reference: MDR = Memory[Out]; -- lw or Memory[Out] = B; -- sw R-type instruction completion Reg[IR[5-]] = Out; Remember, the register write actually takes place at the end of the cycle on the clock edge David Brooks CS4
35 Datapath Activity During Memory Access Cond IorD Mem MemWrite MemtoReg IRWrite PCSource Op Control SrcB SrcA RegWrite RegDst PC Address Memory Data (Instr. or Data) IR MDR Instr[3-6] Instr[5-] Instr[5-] Addr Register Addr Data File Write Addr Data Sign Extend 3 Instr[5-] A B 4 3 PC[3-8] zero control 8 out David Brooks CS4
36 Datapath Activity During lw Memory Access Cond IorD Mem MemWrite MemtoReg IRWrite PCSource Op Control SrcB SrcA RegWrite RegDst PC Address Memory Data (Instr. or Data) IR MDR Instr[3-6] Instr[5-] Instr[5-] Addr Register Addr Data File Write Addr Data Sign Extend 3 Instr[5-] A B 4 3 PC[3-8] zero control 8 out David Brooks CS4
37 Datapath Activity During sw Memory Access Cond IorD Mem MemWrite MemtoReg IRWrite PCSource Op Control SrcB SrcA RegWrite RegDst PC Address Memory Data (Instr. or Data) IR MDR Instr[3-6] Instr[5-] Instr[5-] Addr Register Addr Data File Write Addr Data Sign Extend 3 Instr[5-] A B 4 3 PC[3-8] zero control 8 out David Brooks CS4
38 Datapath Activity During R-type Memory Access Cond IorD Mem MemWrite MemtoReg IRWrite PCSource Op Control SrcB SrcA RegWrite RegDst PC Address Memory Data (Instr. or Data) IR MDR Instr[3-6] Instr[5-] Instr[5-] Addr Register Addr Data File Write Addr Data Sign Extend 3 Instr[5-] A B 4 3 PC[3-8] zero control 8 out David Brooks CS4
39 Memory Access Control Signals Settings Unless otherwise assigned Start,IRWrite, MemWrite,RegWrite= others= SrcA= SrcB= Op= Cond= (Op = lw) (Op = sw) Memory Access (Op = lw or sw) Execute IorD= Mem;IRWrite SrcA= srcb= PCSource,Op= SrcA= SrcB= Op= Cond= Instr Fetch (Op = R-type) SrcA= SrcB= Op= PCSource= Cond (Op = beq) (Op = j) Decode SrcA= SrcB= Op= Cond= PCSource= David Brooks CS4
40 Memory Access Control Signals Settings Unless otherwise assigned Start,IRWrite, MemWrite,RegWrite= others= SrcA= SrcB= Op= Cond= (Op = lw) Mem IorD= Cond= (Op = sw) Memory Access (Op = lw or sw) Execute MemWrite IorD= Cond= IorD= Mem;IRWrite SrcA= srcb= PCSource,Op= SrcA= SrcB= Op= Cond= RegDst= RegWrite MemtoReg= Cond= Instr Fetch (Op = R-type) SrcA= SrcB= Op= PCSource= Cond (Op = beq) (Op = j) Decode SrcA= SrcB= Op= Cond= PCSource= David Brooks CS4
41 Step 5: Memory Completion (Write Back) All we have left is the write back into the register file the data just read from memory for lw instruction Reg[IR[-6]]= MDR; What about all the other instructions? David Brooks CS4
42 Datapath Activity During Write Back Cond IorD Mem MemWrite MemtoReg IRWrite PCSource Op Control SrcB SrcA RegWrite RegDst PC Address Memory Data (Instr. or Data) IR MDR Instr[3-6] Instr[5-] Instr[5-] Addr Register Addr Data File Write Addr Data Sign Extend 3 Instr[5-] A B 4 3 PC[3-8] zero control 8 out David Brooks CS4
43 Datapath Activity During lw Write Back Cond IorD Mem MemWrite MemtoReg IRWrite PCSource Op Control SrcB SrcA RegWrite RegDst PC Address Memory Data (Instr. or Data) IR MDR Instr[3-6] Instr[5-] Instr[5-] Addr Register Addr Data File Write Addr Data Sign Extend 3 Instr[5-] A B 4 3 PC[3-8] zero control 8 out David Brooks CS4
44 Write Back Control Signals Settings Unless otherwise assigned Start,IRWrite, MemWrite,RegWrite= others= SrcA= SrcB= Op= Cond= (Op = lw) Mem IorD= Cond= (Op = sw) Memory Access (Op = lw or sw) Execute MemWrite IorD= Cond= IorD= Mem;IRWrite SrcA= srcb= PCSource,Op= SrcA= SrcB= Op= Cond= RegDst= RegWrite MemtoReg= Cond= Instr Fetch (Op = R-type) SrcA= SrcB= Op= PCSource= Cond (Op = beq) (Op = j) Decode SrcA= SrcB= Op= Cond= PCSource= Write Back David Brooks CS4
45 Write Back Control Signals Settings Unless otherwise assigned Start,IRWrite, MemWrite,RegWrite= others= SrcA= SrcB= Op= Cond= (Op = lw) Mem IorD= Cond= (Op = sw) Memory Access (Op = lw or sw) Execute MemWrite IorD= Cond= IorD= Mem;IRWrite SrcA= srcb= PCSource,Op= SrcA= SrcB= Op= Cond= RegDst= RegWrite MemtoReg= Cond= Instr Fetch (Op = R-type) SrcA= SrcB= Op= PCSource= Cond (Op = beq) (Op = j) Decode SrcA= SrcB= Op= Cond= PCSource= RegDst= RegWrite MemtoReg= Cond= Write Back David Brooks CS4
46 RTL Summary Step Instr fetch Decode Execute Memory access R-type Out = PC +(sign-extend(ir[5-])<< ); Out = if (A==B) A + sign-extend PC = (IR[5-]); Out; Out = A op B; Writeback Reg[IR[5- ]] = Out; Mem Ref Branch IR = Memory[PC]; PC = PC + 4; A = Reg[IR[5-]]; B = Reg[IR[-6]]; MDR = Memory[Out]; or Memory[Out] = B; Reg[IR[-6]] = MDR; Jump PC = PC[3-8] (IR[5-] << ); David Brooks CS4
47 Simple Questions How many cycles will it take to execute this code? lw $t, ($t3) lw $t3, 4($t3) beq $t, $t3, Label #assume not add $t5, $t, $t3 sw $t5, 8($t3) Label:... What is going on during the 8 th cycle of execution? In what cycle does the actual addition of $t and $t3 takes place? In what cycle is the branch target address calculated? David Brooks CS4
48 Simple Questions How many cycles will it take to execute this code? lw $t, ($t3) 5 lw $t3, 4($t3) 5 beq $t, $t3, Label 3 #assume not add $t5, $t, $t3 4 sw $t5, 8($t3) 4 Label:... = cycles What is going on during the 8 th cycle of execution? address for second lw being calculated In what cycle does the actual addition of $t and $t3 takes place? 6 th cycle In what cycle is the branch target address calculated? th cycle David Brooks CS4
49 Multicycle Control Multicycle datapath control signals are not determined solely by the bits in the instruction e.g., op code bits tell what operation the should be doing, but not what instruction cycle is to be done next We ll use a finite state machine for control a set of states (current state stored in State Register) next state function (determined by current state and the input) output function (determined by Combinational current state and the input) control logic... Datapath control points Inst Opcode We ll use a Moore machine (so control signals based only on current state) David Brooks CS State Reg Next State
50 Multicycle Datapath Finite State Machine Unless otherwise assigned Start,IRWrite, MemWrite,RegWrite= others= SrcA= SrcB= Op= Cond= 3 (Op = lw) Mem IorD= Cond= (Op = sw) Memory Access (Op = lw or sw) Execute IorD= Instr Fetch 5 MemWrite IorD= Cond= Mem;IRWrite SrcA= srcb= PCSource,Op= 6 SrcA= SrcB= Op= Cond= 7 RegDst= RegWrite MemtoReg= Cond= (Op = R-type) 8 9 SrcA= SrcB= Op= PCSource= Cond (Op = beq) (Op = j) Decode SrcA= SrcB= Op= Cond= PCSource= 4 RegDst= RegWrite MemtoReg= Cond= Write Back David Brooks CS4
51 Finite State Machine Implementation Combinational control logic Inputs Outputs Cond IorD Mem MemWrite IRWrite MemtoReg PCSource Op SourceB SourceA RegWrite RegDst Op5 Op4 Op3 Op Op Op Inst[3-6] System Clock State Reg Next State David Brooks CS4
52 David Brooks CS4 Datapath Control Outputs Truth Table RegDst RegWrite SrcA SrcB Op PCSource MemtoReg IRWrite MemWrite Mem IorD Cond Input Values (Current State[3-]) Outputs
53 David Brooks CS4 Next State Truth Table illegal illegal illegal illegal illegal illegal illegal illegal illegal Any other (sw) (lw) (beq) (jmp) (R-type) Inst[3-6] (Op[5-]) Current State [3- ]
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