ECE 313 Computer Organization FINAL EXAM December 11, Multicycle Processor Design 30 Points

Transcription

1 This exam is open book and open notes. Credit for problems requiring calculation will be given only if you show your work. 1. Multicycle Processor Design 0 Points In our discussion of exceptions in the multicycle processor implementation, we showed how the Exception Program Counter (EPC) is written, but not how it is read. This is typically done using an instruction which moves the EPC to one of the 2 general-purpose registers. An exception handler can then use the EPC value to identify the instruction where the exception occurred, and (if the exception can be handled), where the program should resume after exception handling is completed. To transfer the EPC to a register, we propose a new MIPS instruction called mfepc (move from EPC), which stores the EPC into the register given by the rt field. The assembly language format, register transfer, and binary instruction format of the mfepc instruction are shown below: mfepc rt Reg[rt] <- EPC 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits 16 0 rt (a) Modify the attached multicycle datapath schematic and controller state diagram to implement the mfepc instruction as described above. (b) If an exception handler can successfully deal with an exception (e.g., by emulating an unimplemented instruction), it can continue execution of the interrupted program starting with the instruction after the instruction that caused the exception. Assuming that the mfepc is used to move the EPC to register $t0, write a sequence of MIPS assembly language instructions that will do this. Page 1 of 6

2 Start 0 Instruction Fetch MemRead ALSrcA = 0 IorD = 0 IRWrite ALSrcB = 01 ALOp = 00 PCSource = 00 Instruction decode / register fetch 1 ALSrcA = 0 ALSrcB = 11 ALOp = 00 Memory address computation 2 ALSrcA = 1 ALSrcB = 10 ALOp = 00 Branch Execution Completion ALSrcA = 1 ALSrcB = 00 ALOp = 10 ALSrcA = 1 ALSrcB = 00 ALOp = 01 Cond PCSource = 01 (OP = JMP ) Jump Completion PCSource = 10 (OP = other) 4 (OP = LW ) MemRead IorD = 1 Memory access RegWrite MemToReg=1 RegDst = 0 (OP = ( SW ) Writeback step Memory access 5 7 MemWrite IorD = 1 RegDst = 1 RegWrite MemtoReg = 0 No Overflow Overflow 11 IntCause = 1 CauseWrite ALSrcA = 0 ALSrcB = 01 ALOp = 01 E PCSouce = IntCause = 0 CauseWrite ALSrcA = 0 ALSrcB = 01 ALOp = 01 E PCSource = 11 0xC PCWr* PC IorD 0 M 1 X MemWrite ADDR Memory RD WD MemRead I R M D R Instruction I 2 1 M 0 X MemtoReg immediate rs rt 5 5 RN1 RN2 WN Registers RD1 WD RegWrite 16 E X T N D 2 5 rd 0 1 MX 5 RD2 <<2 jmpaddr I[25:0] RegDst A B <<2 CONCAT ALSrcA Operation 0 M 1 X 0 1 M 2 X ALSrcB AL 0 1 Zero Overflow 0 M 1 X AL OT C A S E IntCause. CauseWrite 2 M 1 X 0 PCSource E P C E Page 2 of 6

3 2. Pipelined Processor Design 25 Points The pipelined processor implementation that was described in Chapter 6 does implement the j (jump) instruction. (a) (b) Modify the pipelined processor datapath and control to implement the j (jump) instruction. Show any changes to the datapath on the diagram on the next page, and show all control signals (including any that you add) in the table below. You may find it helpful to review the control table in Fig on p. 469 of the text. HINT: most of the instruction can be implemented in the ID stage. Will the jump instruction in your design be susceptible to any hazards? Why or whey not? Instr. jmp Reg Dst EX Stage Control Lines AL Op0 AL Op1 AL Src Branch MEM Stage Control Lines Mem Mem Read Write WB Stage Control Lines Reg Memto Write Reg Page of 6

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5 . Pipelined Design Forwarding, Data Hazards, and Stalls 25 Points Consider the following sequence of MIPS instructions and assume that we are using the pipelined design with forwarding shown in Fig of the book (p. 484). add $1, $2, $ sw $, 100($1) lw $4, 200($) sub $5, $5, $4 (a) Circle any data dependencies which exist in these instructions for the given pipeline in the code listed above. (b) Fill in the multi-cycle pipeline diagram below to show how the given instructions flow through the pipeline. You should label each instruction, shade stages to show which parts of each stage are active during each cycle, show any forwarding connections that are needed, and clearly mark stalled instructions. (c) Assuming that the pipeline is initially empty, how many clock cycles does it take for this sequence of instructions to execute? CC 1 CC 2 CC CC 4 CC 5 CC 6 CC 7 CC 8 CC 9 CC 10 CC 11 Page 5 of 6

6 4. Short Answers 20 Points Please answer the following questions concisely and briefly. (a) What are the advantages of a fixed-length instruction format compared to a variablelength instruction format? (b) What is the purpose of denormalized numbers in the IEEE floating-point representation? (c) Why is microcode still used in the Pentium 4 and other x86 processor designs? (d) What is the key advantage of performing out-of-order execution in a processor implementation? (e) What happens on a cache miss? Page 6 of 6