14:332:331. Computer Architecture and Assembly Language Spring Week 6

Transcription

1 14:332:331 Computer Architecture and Assembly Language Spring 2005 Week 6 [Adapted from Dave Patterson s UCB CS152 slides and Mary Jane Irwin s PSU CSE331 slides] Week 6.1 Spring 2005

2 Review: Entity-Architecture Features Design Entity-Architecture == Hardware Component Entity == External Characteristics Architecture (Body ) == Internal Behavior or Structure Entity defines externally visible characteristics Ports: channels of communication Architecture defines the internal behavior or structure Declaration of internal signals Description of behavior - concurrent behavioral description: collection of CSA s - process behavioral description: CSAs and variable assignment statements within a process description - structural description: system described in terms of the interconnections of its components Week 6.2 Spring 2005

3 Review: Model of Execution CSA s are executed concurrently - textural order of the statements is irrelevant to the correct operation VHDL programmer specifies events - with CSA s delays - with CSA s with delay annotation concurrency - by having a distinct CSA for each signal Week 6.3 Spring 2005

4 Review: Signal Resolution Resolving values of pairs of std_logic type signals When a signal has multiple drivers (e.g., a bus), the value of the resulting signal is determined by a resolution function U unknown X forcing unknown 0 1 Z high imped W weak unknown L weak 0 H weak 1 - don t care U U U U U U U U U U X U X X X X X X X X 0 U X 0 X X 1 U X X X Z U X 0 1 Z W L H X W U X 0 1 W W W W X L U X 0 1 L W L W X H U X 0 1 H W W H X - U X X X X X X X X Week 6.4 Spring 2005

5 Motivation for Process Construct How would you build the logic (and the VHDL code) for a 32 by 2 multiplexor given inverters and 2 input nands? SEL A B 0 1 DOUT Week 6.5 Spring 2005

6 Motivation for Process Construct How would you build the logic for a 32 by 2 multiplexor given inverters and 2 input nands? SEL SEL A B 0 1 DOUT A[0] SELbar TA(0) Given the logic schematic, can you write the VHDL code? A[1] B[0] B[1] Week 6.6 Spring TA(1) TB(0) TB(1)... DOUT[0] DOUT[1]...

7 MUX CSA Description A B 0 1 SEL entity MUX32X2 is port(a,b: in std_logic_vector(31 downto 0); DOUT: out std_logic_vector(31 downto 0); SEL: in std_logic); end MUX32X2; DOUT How can we describe the circuit in VHDL if we don t know what primitive gates we will be designing with? Week 6.7 Spring 2005

8 MUX CSA Description A B 0 1 SEL expands to 32 gates each entity MUX32X2 is port(a,b: in std_logic_vector(31 downto 0); DOUT: out std_logic_vector(31 downto 0); SEL: in std_logic); end MUX32X2; DOUT architecture conc_behavior of MUX32X2 is signal TA,TB: std_logic_vector (31 downto 0), SELbar: std_logic; begin SELbar <= not SEL after 1 ns; TA <= A nand SELbar after 2 ns; TB <= B nand SEL after 2 ns; DOUT <= TA nand TB after 2 ns; end conc_behavior; How can we describe the circuit in VHDL if we don t know what primitive gates we will be designing with? Week 6.8 Spring 2005

9 Mux Process Description entity MUX32X2 is port(a,b: in std_logic_vector(31 downto 0); DOUT: out std_logic_vector(31 downto 0); SEL: in std_logic); end MUX32X2; architecture process_behavior of MUX32X2 is begin mux32x2_process: process(a, B, SEL) begin if (SEL = 0 ) then DOUT <= A after 5 ns; else DOUT <= B after 4 ns; end if; end process mux32x2_process; end process_behavior; A B 0 1 SEL DOUT Process fires whenever a signal in the sensitivity list changes Week 6.9 Spring 2005

10 VHDL Process Features Process body is executed sequentially to completion in zero (simulation) time Delays are associated only with assignment of values to signals marked by CSAs <= operator Variable assignments take effect immediately marked by := operator Upon initialization all processes are executed once After initialization processes are data-driven activated by events on signals in sensitivity list waiting for the occurrence of specific events using wait statements Week 6.10 Spring 2005

11 Process Programming Constructs if-then-else case Boolean valued expressions are evaluated sequentially until first true is encountered loop index cannot be assigned a value or altered in loop body while loop if (expression1 = value1 ) then... elsif (expression2 = value2 ) then... end if; branches must cover all possible case (expression) is values for the case expression when value0 =>... for loop end case; loop index declared (locally) by virtue of use in loop stmt for index in value1 to value2 loop condition may involve variables modified within the loop while (condition) loop Week 6.11 Spring 2005

12 Behavioral Description of a Register File write_cntrl Register File src1_addr src2_addr dst_addr write_data 32 words src1_data src2_data library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; 32 bits entity regfile is port(write_data: in std_logic_vector(31 downto 0); dst_addr,src1_addr,src2_addr: in UNSIGNED(4 downto 0); write_cntrl: in std_logic; src1_data,src2_data: out std_logic_vector(31 downto 0)); end regfile; Week 6.12 Spring 2005

13 Behavioral Description of a Register File, con t architecture process_behavior of regfile is type reg_array is array(0 to 31) of std_logic_vector (31 downto 0); begin regfile_process: process(src1_addr,src2_addr,write_cntrl) variable data_array: reg_array := ( (X ), (X ),... (X )); variable addrofsrc1, addrofsrc2, addrofdst: integer; begin addrofsrc1 := conv_integer(src1_addr); addrofsrc2 := conv_integer(src2_addr); addrofdst := conv_integer(dst_addr); if write_cntrl = 1 then data_array(addrofdst) := write_data; end if; src1_data <= data_array(addrofsrc1) after 10 ns; src2_data <= data_array(addrofsrc2) after 10 ns; end process regfile_process; end process_behavior; Week 6.13 Spring 2005

14 Process Construct with Wait Statement library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; entity dff is port(d,clk: in std_logic; Q,Qbar: out std_logic); end dff; D clk Q dff Qbar positive edge-triggered architecture dff_behavior of dff is begin output: process begin wait until (clk event and clk = 1 ); Q <= D after 5 ns; Qbar <= not D after 5 ns; end process output; end dff_behavior; Week 6.14 Spring 2005

15 Wait Statement Types Wait statements specify conditions under which a process may resume execution after suspension wait for time expression wait for (20 ns); - suspends process for a period of time defined by the time expression wait on signal wait on clk, reset, status; - suspends process until an event occurs on one (or more) of the signals wait until condition wait until (clk event and clk = 1 ); wait - suspends process until condition evaluates to specified Boolean Process resumes execution at the first statement following the wait statement Week 6.15 Spring 2005

16 Signal Attributes Attributes are used to return various types of information about a signal Function attribute signal_name event signal_name active signal_name last_event signal_name last_active signal_name last_value Function Boolean value signifying a change in value on this signal Boolean value singifying an assignment made to this signal (may not be a new value!) Time since the last event on this signal Time since the signal was last active Previous value of this signal Week 6.16 Spring 2005

17 Things to Remember About Processes A process must have either a sensitivity list or at least one wait statement A process cannot have both a sensitivity list and a wait statement Remember, all processes are executed once when the simulation is started Don t confuse signals and variables. Signals are declared either in the port definitions in the entity description or as internal signals in the architecture description. They are used in CSAs. Signals will be updated only after the next simulation cycle. Variable exist only inside architecture process descriptions. They are used in variable assignment statements. Variables are updated immediately. Week 6.17 Spring 2005

18 Finite State Machine Structure a b comb z Exec Fetch PC = PC+4 Decode Q(0) dff D(0) Q(1) dff D(1) clk Week 6.18 Spring 2005

19 Structural VHDL Model System is described by its component interconnections assumes we have previously designed entity-architecture descriptions for both comb and dff with behavioral models in1 in2 a b c_state(1) c_state(0) comb z nxt_state(1) nxt_state(0) out1 Q(0) Qbar(0) dff D(0) Q(1) Qbar(1) dff D(1) clk clk Week 6.19 Spring 2005

20 Structural VHDL Model System is described by its component interconnections assumes we have previously designed entity-architecture descriptions for both comb and dff with behavioral models in1 in2 a b c_state(1) c_state(0) comb z nxt_state(1) nxt_state(0) out1 s1(0) Q(0) Qbar(0) s1(1) Q(1) Qbar(1) dff dff s2(0) D(0) s2(1) D(1) clk clk Week 6.20 Spring 2005

21 Finite State Machine Structural VHDL entity seq_circuit is port(in1,in2,clk: in std_logic; out1: out std_logic); end seq_circuit; architecture structural of seq_circuit is component comb port(a,b: in std_logic; z: out std_logic; c_state: in std_logic_vector (1 downto 0); nxt_state: out std_logic_vector (1 downto 0)); end component; component dff port(d,clk: in std_logic; Q,Qbar: out std_logic); end component; for all: comb use entity work.comb(comb_behavior); for all: dff use entity work.dff(dff_behavior); signal s1,s2: std_logic_vector (1 downto 0); begin C0:comb port map(a=>in1,b=>in2,c_state=>s1,z=>out1, nxt_state=>s2); D0:dff port map(d=>s2(0),clk=>clk,q=>s1(0),qbar=>open); D1:dff port map(d=>s2(1),clk=>clk,q=>s1(1),qbar=>open); end structural; Week 6.21 Spring 2005

22 Summary Introduction to VHDL A language to describe hardware - entity = symbol, architecture ~ schematic, signals = wires Inherently concurrent (parallel) Has time as concept Behavioral descriptions of a component - can be specified using CSAs - can be specified using one or more processes and sequential statements Structural descriptions of a system are specified in terms of its interconnections - behavioral models of each component must be provided Week 6.22 Spring 2005