APPENDIX 1 SINUSOIDAL PULSE WIDTH MODULATION

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1 120 APPENDIX 1 SINUSOIDAL PULSE WIDTH MODULATION % A Program For Analysis of SINUSOIDAL PULSE WIDTH MODULATION of Inverter Fed AC Drive % Signal. % By: R.Rajran % Date 08/06/2011 % clear all disp('sinusoidal Pulse Width Modulation of AC Signal') disp(' ') % % PART II % In this part the already known variables are entered, the user is % asked to enter the other variables. % Vrin is the rms value of the input supply voltage in per unit. Vrin=1; % f is the frequency of the input supply voltage. f=input('the frequency of the input supply voltage, f = '); % Z is the load impedance in per unit. Z=1; % ma is the modulation index ma=input('the modulation index,ma, (0<ma<1), ma = '); % phi is load-phase-angle phi=input('the phase angle of the load in degrees = '); % Q is the number of pulses per half-period of the supply voltage.

2 121 Q=input('The number of pulses per half period = '); % % PART III % Calculating load parameters. % phi=phi*pi/180; % R and L are the load resistance and inductance respectively. R=Z*cos(phi); L=(Z*sin(phi))/(2*pi*f); % % PART IV % Calculating the number of pulses per period,n N=2*Q; % %PART V for k=1:2*n for j=1:50 % finding the generalized time counter i=j+(k-1)*50; % finding the time step wt(i)=i*pi/(n*50); % calculating the input supply voltage. Vin(i)=sqrt(2)*Vrin*sin(wt(i)); ma1(i)=ma*abs(sin(wt(i))); % calculating the sawtooth waveform if rem(k,2)==0 Vt(i)=0.02*j; if abs(vt(i)-ma*abs(sin(wt(i))))<=0.011 m=j; beta(fix(k/2)+1)=3.6*((k-1)*50+m)/n; else

3 122 j=j; else Vt(i)=1-0.02*j; if abs(vt(i)-ma*abs(sin(wt(i))))<0.011 l=j; alpha(fix(k/2)+1)=3.6*((k-1)*50+l)/n; else j=j; if Vt(i)>ma*abs(sin(wt(i))) Vout(i)=0; else Vout(i)=Vin(i); beta(1)=[]; subplot(3,1,2) plot(wt,vt,wt,ma1,wt,a) axis([0,2*pi,-2,2]) ylabel('vt, m(pu)'); subplot(3,1,3) plot(wt,vout,wt,a) axis([0,2*pi,-2,2]) ylabel('vo(pu)'); xlabel('radian');

4 123 % PART VIII % Analyzing the output voltage waveform % Finding the rms value of the output voltage Vo =sqrt(1/(length(vout))*sum(vout.^2)); disp('the rms Value of the Output Voltage ') Vo % finding the harmonic contents of the output voltage waveform y=fft(vout); y(1)=[]; x=abs(y); x=(sqrt(2)/(length(vout)))*x; disp('the rms Value of the output voltage fundamental component = ') x(1) % Findint the THD of the output voltage THDVo = sqrt(vo^2 -x(1)^2)/x(1); % PART IX % calculating the output current waveform m=r/(2*pi*f*l); DT=pi/(N*50); C(1)=-10; i=100*n+1:2000*n; Vout(i)=Vout(i-100*N*fix(i/(100*N))+1); for i=2:2000*n; C(i)=C(i-1)*exp(-m*DT)+Vout(i-1)/R*(1-exp(-m*DT));

5 124 %PART XIV figure(2) subplot(3,2,1) plot(wt,vout(1:100*n),wt,a); title(''); axis([0,2*pi,-1.5,1.5]); ylabel('vo(pu)'); % subplot(3,2,2) plot(x(1:100)) title(''); axis([0,100,0,0.8]); ylabel('von(pu)'); subplot(3,2,3) plot(wt,c(1900*n+1:2000*n),wt,a); title(''); axis([0,2*pi,-1.5,1.5]); ylabel('io(pu)'); subplot(3,2,4) plot(cox(1:100)) title(''); axis([0,100,0,0.8]); ylabel('ion(pu)');

6 125 APPENDIX 2 SPACE VECTOR MODULATION % A program for SVPWM of Inverter Fed Induction motor Drive warning off; clc; clear all; phir=0.96; wref=input('refernce speed='); V=220; I=14.8; P=5*746; F=60; Lls=1.9e-3;

7 126 Llr=1.9e-3; Lm=41.2e-3; N=1750; Rs=0.6; Rr=0.41; p=4; Ls=Lls+Lm; Lr=Llr+Lm; %parameters eta=rr/lr; sigma=(1-lm^2/(ls*lr)); k3=1/(sigma*ls); k2=rs/(sigma*ls); k1=k3*lm/lr; %control parameters u0=1; u=0.002;

8 127 APPENDIX 2 FIELD ORIENTED CONTROL OF INDUCTION MOTOR DRIVE S Function Code for Induction Motor static void mdinitializesampletimes(simstruct *S) sssetsampletime(s,0, CONTINUOUS_SAMPLE_TIME); sssetoffsettimes(s,0,0,0); static void mdlinitializeconditions(real_t*x0,simstauct *s int i; for(i=0;i<4;i++) *x0++=0.0; static void mdloutputs(real_t*y, const real_t *x, const real_t *u)

9 128 double lm; int po; lm=mxgetpr(lm) [0]; po=mxgetpr(p0) [0]; y[0]=x[0]; y[1]=x[1]; y[2]=x[2]; y[3]=x[3]; y[4]=x[4]; y[4]=0.75*po*lm*(x[2]*x[1]-x[3]*x[0]); static void mdlupdate(const real_t *dx, const real_t *x, const real_t *u, SimStrauct *S) static void mdlderivative(const real_t *dx, const real_t *x, const real_t *u, SimStrauct *S) double lr,ls,rr,rs,lm,a: lm=mxgetpr(lm)[0]; lr=mxgetpr(lr) [0]; ls=mxgetpr(ls)[0]; rr=mxgetpr(rr) [0]; rs=mxgetpr(rs)[0]; static void mdlterminate(simstruct *s)

10 129 APPENDIX 4 CONVENTIONAL DIRECT TORQUE CONTROL OF INDUCTION MOTOR DRIVE S-Function code for voltage vector selection table static void mdinitializesampletimes(simstruct *S) sssetsampletime(s,0, CONTINUOUS_SAMPLE_TIME); sssetoffsettimes(s,0,0,0); static void mdlinitializeconditions(real_t*x0,simstauct *s int i;

11 130 for(i=0;i<4;i++) *x0++=0.0; static void mdloutputs(real_t*y, const real_t *x, const real_t *u) double lm; int po; lm=mxgetpr(lm) [0]; po=mxgetpr(p0) [0]; y[0]=x[0]; y[1]=x[1]; y[2]=x[2]; y[3]=x[3]; y[4]=x[4]; y[4]=0.75*po*lm*(x[2]*x[1]-x[3]*x[0]); static void mdlupdate(const real_t *dx, const real_t *x, const real_t *u, SimStrauct *S) static void mdlderivative(const real_t *dx, const real_t *x, const real_t *u, SimStrauct *S) double lr,ls,rr,rs,lm,a: lm=mxgetpr(lm)[0]; lr=mxgetpr(lr) [0]; ls=mxgetpr(ls)[0]; rr=mxgetpr(rr) [0]; rs=mxgetpr(rs)[0]; static void mdlterminate(simstruct *s)

12 131 APPENDIX 5 PROPOSED SVM-DTC OF INDUCTION MOTOR DRIVE function [sys,x0,str,ts]=volvector(t,x,u,flag) switch flag %%%%%%%%%%%%%%%%%%%%%% Initialization %%%%%%%%% case 0 [sys,x0,str,ts]=mdlinitializesizes; %%%%%%%%%%%%%%%%%%%%%%%%%% Derivatives,Update and Terminate %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% case 1,2,9 sys=[]; case 3 sys=mdloutputs(t,x,u);

13 132 otherwise error(['unhandled flag=',num2str(flag)]); %================================================= %mdlinitializesizes %Return the sizes, initial conditions, and sample time for the s-function %================================================== function[sys,x0,str,ts]=mdlinitializesizes sizes=simsizes; sizes.numcontstates=0; sizes.numdiscstates=0; sizes.numoutputs=3; sizes.dirfeedthrough=1; sizes.numsampletimes=1; sys=simsize(sizes); str=[]; x0=[]; ts=[0 0]; function sys=mdloutputs(t,x,u) if(u(1)==1 & u(2)==0 & u(3)==1) sys(1)=1; elseif(u(1)==0&u(2)==0 & u(3)==1) sys(1)=1; elseif(u(1)==1&u(2)==0 & u(3)==1) sys(1)=1; sys(3)=1; elseif(u(1)==1&u(2)==1 & u(3)==1) sys(1)=1;

14 133 elseif(u(1)==0&u(2)==1 & u(3)==1) sys(1)=1; elseif(u(1)==1&u(2)==1 & u(3)==1) sys(1)=-1; elseif(u(1)==0&u(2)==0 & u(3)==1) sys(1)=-1; elseif(u(1)==0&u(2)==0 & u(3)==1) sys(1)=-1; elseif(u(1)==0&u(2)==0 & u(3)==1) sys(1)=1; elseif(u(1)==0&u(2)==0 & u(3)==1) sys(1)=-1; elseif(u(1)==0&u(2)==0 & u(3)==1) sys(1)=-1; elseif(u(1)==0&u(2)==0 & u(3)==1) sys(1)=-1; sys(2)=-1; elseif(u(1)==1&u(2)==0 & u(3)==2) sys(1)=1;

15 134 elseif(u(1)==2&u(2)==1 & u(3)==1) sys(1)=1; elseif(u(1)==1&u(2)==1 & u(3)==1) sys(1)=1;

16 135 APPENDIX 6 XILINX SYSTEM GENERATOR ISE PROJECT NAVIGATOR

17 136 APPENDIX 7 SYNTHESIS REPORT Release xst M.70d (nt) Copyright (c) Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to xst/projnav.tmp Total REAL time to Xst completion: 1.00 secs Total CPU time to Xst completion: 0.25 secs --> Parameter xsthdpdir set to xst Total REAL time to Xst completion: 1.00 secs Total CPU time to Xst completion: 0.25 secs --> Reading design: jc2_top.prj TABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Compilation 3) Design Hierarchy Analysis 4) HDL Analysis 5) HDL Synthesis 5.1) HDL Synthesis Report 6) Advanced HDL Synthesis 6.1) Advanced HDL Synthesis Report 7) Low Level Synthesis 8) Partition Report 9) Final Report * Synthesis Options Summary * ---- Source Parameters Input File Name : "SVM-DTC" Input Format : mixed Ignore Synthesis Constraint File : NO ---- Target Parameters Output File Name : "jc2_top" Output Format : NGC Target Device : XC9500XL CPLDs ---- Source Options

18 137 Top Module Name Automatic FSM Extraction FSM Encoding Algorithm Safe Implementation Mux Extraction Resource Sharing ---- Target Options Add IO Buffers MACRO Preserve XOR Preserve Equivalent register Removal : jc2_top : YES : Auto : No : Yes : YES : YES : YES : YES : YES ---- General Options Optimization Goal : Speed Optimization Effort : 1 Keep Hierarchy : Yes Netlist Hierarchy : As_Optimized RTL Output : Yes Hierarchy Separator : / Bus Delimiter : <> Case Specifier : Maintain Verilog 2001 : YES ---- Other Options Clock Enable : YES wysiwyg : NO * HDL Compilation * Compiling vhdl file "C:/Documents and Settings/user/jc2_vhd/jc2_top.vhd" in Library work. Entity <jc2_top> compiled. Entity <jc2_top> (Architecture <jc2_top_arch>) compiled. * Design Hierarchy Analysis * Analyzing hierarchy for entity <jc2_top> in library <work> (architecture <jc2_top_arch>). * HDL Analysis *

19 138 Analyzing Entity <jc2_top> in library <work> (Architecture <jc2_top_arch>). Entity <jc2_top> analyzed. Unit <jc2_top> generated. * HDL Synthesis * Performing bidirectional port resolution... Synthesizing Unit <jc2_top>. Related source file is "C:/Documents and Settings/user/jc2_vhd/jc2_top.vhd". Found 1-bit register for signal <DIR>. Found 4-bit register for signal <Q_int>. Found 1-bit register for signal <RUN>. Summary: inferred 4 D-type flip-flop(s). Unit <jc2_top> synthesized. HDL Synthesis Report Macro Statistics # Registers : 6 1-bit register : 6 * Advanced HDL Synthesis * Advanced HDL Synthesis Report Macro Statistics # Registers : 4 Flip-Flops : 4 * Low Level Synthesis * Optimizing unit <jc2_top>... implementation constraint: INIT=r : Q_int_0 implementation constraint: INIT=r : Q_int_1 implementation constraint: INIT=r : Q_int_2 implementation constraint: INIT=r : Q_int_3 implementation constraint: INIT=r : RUN implementation constraint: INIT=r : DIR

20 139 ======================================================* Partition Report * Partition Implementation Status No Partitions were found in this design. * Final Report * Final Results RTL Top Level Output File Name : jc2_top.ngr Top Level Output File Name : jc2_top Output Format : NGC Optimization Goal : Speed Keep Hierarchy : Yes Target Technology : XC9500XL CPLDs Macro Preserve : YES XOR Preserve : YES Clock Enable : YES wysiwyg : NO Design Statistics # IOs : 8 Cell Usage : # BELS : 24 # AND2 : 8 # GND : 1 # INV : 9 # OR2 : 6 # FlipFlops/Latches : 6 # FDCE : 6 # IO Buffers : 8 # IBUF : 4 # OBUF : 4 Total REAL time to Xst completion: 3.00 secs Total CPU time to Xst completion: 2.98 secs --> Total memory usage is kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered)

21 140 APPENDIX 8 VHDL CODE library IEEE; use IEEE.std_logic_1164.all; -- defines std_logic types entity jc2_top is port ( LEFT : in STD_LOGIC; -- Active-low switch #3 (left) RIGHT : in STD_LOGIC; -- Active-low switch #0 (right) STOP : in STD_LOGIC; -- Active-low switch #2 CLK : in STD_LOGIC; Q : out STD_LOGIC_VECTOR (3 downto 0) -- Active-low LEDs ); --To pass pin location constraints from this HDL source file rather than --through a User Constraints Format (UCF) file, uncomment the six attribute --declarations below and remove jc2_top.ucf from the project. -- attribute pin_assign : string; -- attribute pin_assign of clk : signal is "A7"; -- attribute pin_assign of left : signal is "G7"; -- attribute pin_assign of right : signal is "B2"; -- attribute pin_assign of stop : signal is "F2"; -- attribute pin_assign of q : signal is "G5 F6 C6 B4"; jc2_top; architecture SVMDTC_arch of jc2_top is signal DIR : STD_LOGIC := '0'; -- Left=1, Right=0 signal RUN : STD_LOGIC := '0'; signal Q_int : STD_LOGIC_VECTOR (3 downto 0) := "0000"; -- Internal signal driving Q output; Active-low LEDs begin process (CLK, RIGHT, LEFT, STOP, RUN, DIR, Q_int) begin if (CLK'event and CLK='1') then -- CLK rising edge -- DIR register: if (RIGHT='0') then DIR <= '0';

22 141 elsif (LEFT='0') then DIR <= '1'; if; -- RUN register: if (STOP='0') then RUN <= '0'; elsif (LEFT='0' or RIGHT='0') then RUN <= '1'; if; architecture LPF of jc2_top is signal DIR : STD_LOGIC := '0'; -- Left=1, Right=0 signal RUN : STD_LOGIC := '0'; signal Q_int : STD_LOGIC_VECTOR (3 downto 0) := "0000"; -- Internal signal driving Q output; Active-low LEDs begin process (CLK, RIGHT, LEFT, STOP, RUN, DIR, Q_int) begin if (CLK'event and CLK='1') then -- CLK rising edge -- DIR register: if (RIGHT='0') then DIR <= '0'; elsif (LEFT='0') then DIR <= '1'; if; -- RUN register: if (STOP='0') then RUN <= '0'; elsif (LEFT='0' or RIGHT='0') then RUN <= '1'; if; architecture PI_arch of jc2_top is signal DIR : STD_LOGIC := '0'; -- Left=1, Right=0 signal RUN : STD_LOGIC := '0'; signal Q_int : STD_LOGIC_VECTOR (3 downto 0) := "0000"; -- Internal signal driving Q output; Active-low LEDs begin

23 142 process (CLK, RIGHT, LEFT, STOP, RUN, DIR, Q_int) begin if (CLK'event and CLK='1') then -- CLK rising edge -- DIR register: if (RIGHT='0') then DIR <= '0'; elsif (LEFT='0') then DIR <= '1'; if; -- RUN register: if (STOP='0') then RUN <= '0'; elsif (LEFT='0' or RIGHT='0') then RUN <= '1'; if; architecture EST_arch of jc2_top is signal DIR : STD_LOGIC := '0'; -- Left=1, Right=0 signal RUN : STD_LOGIC := '0'; signal Q_int : STD_LOGIC_VECTOR (3 downto 0) := "0000"; -- Internal signal driving Q output; Active-low LEDs begin process (CLK, RIGHT, LEFT, STOP, RUN, DIR, Q_int) begin if (CLK'event and CLK='1') then -- CLK rising edge -- DIR register: if (RIGHT='0') then DIR <= '0'; elsif (LEFT='0') then DIR <= '1'; if; -- RUN register: if (STOP='0') then RUN <= '0'; elsif (LEFT='0' or RIGHT='0') then RUN <= '1'; if;

24 Counter section: if (RUN='1') then if (DIR='1') then Q_int(3 downto 1) <= Q_int(2 downto 0); -- Shift lower bits (Left Shift) Q_int(0) <= not Q_int(3); -- Circulate inverted MSB to LSB else Q_int(2 downto 0) <= Q_int(3 downto 1); -- Shift upper bits (Right Shift) Q_int(3) <= not Q_int(0); if; if; if; Q <= Q_int; process; -- Circulate inverted LSB to MSB jc2_top_arch;

25 144 APPENDIX 9 DETAILS OF HARWARE SET UP INDUCTION MOTOR Parameters of Induction Motor Power Rating 1 kw Number of Poles 4 Stator Resistance 10.9 Rotor Resistance 9.5 Stator Self Inductance 0.879H Rotor Self Inductance 0.879H Mutual Inductance 0.878H Moment of Inertia kg-m 2 Hall-Effect Current Sensor Spartan 3E FPGA Board Analog to Digital Converter (ADC) Gate Drivers and Voltage Source Inverter NI DAQ Card LabVIEW Software

Logic Implementation on a Xilinx FPGA using VHDL WWU Linux platform assumed. rev 10/25/16

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