Intel Corporation. Software Development Environment for Reconfigurable Communications Architecture Intel Corporation.

Transcription

1 Software Development Environment for Reconfigurable Communications Architecture Vladimir Ivanov Radio Communications Lab/Corporate Technology Group Contributor: Vicki Tsai Radio Communications Lab/Corporate Technology Group Reconfigurable Computing Tutorial International Symposium on System-on-Chip Conference Tampere, Finland Intel Corporation 18 November 2003 Outline RCA Review What are the specific architectural features which impact software development tools? Programming flow How do specific architectural features impact software development process? Software Development Environment Goals and Challenges Process specifics System-level issues Development Environment Concept Algorithm and compiler point of view 2 1

2 RCA Review What are the specific architectural features which impact software development tools? RCA Review Scalable mesh interconnect of heterogeneous processing elements (s) Interconnect with Nearest Neighbour Mesh Clock frequency dependent on load and process 4 2

3 RCA Review Ubiquitous wireless communication across multiple protocols UMAC UMAC 2 1 UMAC 3 D D 1 2 A I.E. B IO (EC) C IO (EC) D IO (EC) E 1 2 Ultra-wideband WPAN WCDMA WWAN IO (AFE 1) IO (AFE 2) IO (AFE 3) 4 A B C D E CMOS AFE 1 CMOS AFE 2 CMOS AFE a WLAN Figure source Intel research and development A scalable mesh interconnect of heterogeneous processing elements (s): Configurable basebands for multiple (concurrent) PHY/MAC operation Power and Size conserving when compared to multiple dedicate d cores or traditional SDR (S/W defined radio) approaches Tools for simple programming and portability to different arrays of elements 5 Programming Flow How do specific architectural features impact the software development process? 3

4 1. Divide the protocol into modes Preamble Detect: Diversity Selection: Steady-State Data: Each mode refers to a different, non-overlapping period in time 7 2. Partitioning Specify functions for each mode Preamble Detect: AFE1 (ant. 1) AGC Dec. Filter Preamble Det. Diversity Selection: AFE1 (ant. 1) AGC Dec. Filter SNR Calc. Diversity Sel. AFE1 (ant. 2) AGC Dec. Filter SNR Calc. Steady-State Data: AFE1 (ant. 1) Dec. Filter AFC Fixed IQ Imb. Corr. Guard Int. Removal Host IO Descram. Viterbi Deinter. QAM Demap Adapt. IQ Imb Corr FEQ 64-Pt FFT Note: This description is function based and not hardware based. 8 4

5 3. Communication Establish communication structure among functions Preamble Detect: AFE1 (ant. 1) AGC Dec. Filter Preamble Det. Diversity Selection: AFE1 (ant. 1) AGC Dec. Filter SNR Calc. Diversity Sel. AFE1 (ant. 2) AGC Dec. Filter SNR Calc. Steady-State Data: AFE1 (ant. 1) Dec. Filter AFC Fixed IQ Imb. Corr. Guard Int. Removal Host IO Descram. Viterbi Deinter. QAM Demap Adapt. IQ Imb Corr FEQ 64-Pt FFT 9 4. Aggregation Determine onto which types the functions could be mapped Preamble Detect: AFE1 (ant. 1) AGC Dec. Filter Preamble Det. typea typeb typec typed typee Diversity Selection: AFE1 (ant. 1) AGC Dec. Filter SNR Calc. Diversity Sel. AFE1 (ant. 2) AGC Dec. Filter SNR Calc. Steady-State Data: AFE1 (ant. 1) Dec. Filter AFC Fixed IQ Imb. Corr. Guard Int. Removal Host IO Descram. Viterbi Deinter. QAM Demap Adapt. IQ Imb Corr FEQ 64-Pt FFT 10 5

6 5. Check if resources available for the current hardware layout Preamble Detect: AFE1 (ant. 1) AGC Dec. Filter Preamble Det. typea typeb typec typed typee Diversity Selection: AFE1 (ant. 1) AGC Dec. Filter SNR Calc. Diversity Sel. AFE1 (ant. 2) AGC Dec. Filter SNR Calc. Steady-State Data: AFE1 (ant. 1) Dec. Filter AFC Fixed IQ Imb. Corr. Guard Int. Removal Host IO Descram. Viterbi HW topology Deinter. QAM Demap Adapt. IQ Imb Corr FEQ 64-Pt FFT B A Resource Usage (%): typeb typea typee typed typec 11 C C E D C D 6. Mapping Place functions onto specific s Preamble Detect: AFE1 (ant. 1) AGC Dec. Filter Preamble Det. Diversity Selection: AFE1 (ant. 1) AGC Dec. Filter SNR Calc. Diversity Sel AFE1 (ant. 2) AGC Dec. Filter SNR Calc. Steady-State Data: AFE1 (ant. 1) Dec. Filter AFC Fixed IQ Imb. Corr. Guard Int. Removal Host IO Descram. Viterbi Deinter. QAM Demap Adapt. IQ Imb Corr FEQ 64-Pt FFT 12 6

7 7. Generate code for this mapping Preamble Detect: AFE1 (ant. 1) AGC Dec. Filter Preamble Det. Diversity Selection: AFE1 (ant. 1) AGC Dec. Filter SNR Calc. Diversity Sel AFE1 (ant. 2) AGC Dec. Filter SNR Calc. Steady-State Data: AFE1 (ant. 1) Dec. Filter AFC Fixed IQ Imb. Corr. Guard Int. Removal Host IO Descram. Viterbi Deinter. QAM Demap Adapt. IQ Imb Corr FEQ 64-Pt FFT Check if desired performance has been reached HW topology Stimulus Data System Profiler Performance results If desired performance has been met, output the binary images. Otherwise, use the results to adjust the mapping and go to Step 2 or 4 or

8 Programming Flow Summary 1. Divide the protocol into modes 2. Specify functions for each mode Programmer 3. Establish communication structure among functions 4. Determine onto what types the functions could be Tools mapped 5. Check if we have the resources in the hardware 6. Place functions onto specific s 7. Generate code for this mapping If code cannot be generated because the cannot fit the assigned functions, try a different mapping 8. Check if desired performance has been reached If not, try a different mapping Otherwise, output the generated code from Step 6 15 Software Development Environment Goals and Challenges Process specifics System-level issues 8

9 Tools Goals Primary goal is to assure development of effective code for RCA Developed code should effectively use all RCA capabilities Implemented protocols should meet users requirements Abstract code development from hardware If the number of total s change or the number of s of a certain type change, the algorithm does not need to be altered Give reasonable programming abstraction level for the programmer Provide effective environment for development, debugging and testing of software 17 Tools Challenges Reasonable balance for abstracting software development from hardware Classical challenges for parallel architecture Decomposition of program into parallel processes Effective mapping of processes to s Effective communication among processes Synchronization among processes Protocol concurrency implies dynamic RCA resource distribution among protocols Heterogeneity of s mesh Variety of Processing Elements (s) s may not be processor-based Methods to program s differ greatly Guaranteed protocol performance Effective data visualization from multiple s High performance simulation of RCA 18 9

10 Software Development Process Algorithm START redevelopment Redevelopment Algorithm development Source code development Tools for algorithm development Tools for source code development No Program code translation Translation tools, Linkage tools Debugging Debugger, Simulator Performance measurement Profiler Meets user s reqs? Yes Testing AWARD 19 Software Development Environment Hardware Software description description Algorithm and source code development tools Descriptions editor Process diagram editor Source code of processes IDE Source Code Editor Source Source etc etc. Descriptions Translator Specific tools Map Directives Parsed Descriptions (XML) Makefile Translation Translation tool tool Librarian Relocatable Relocatable Execution statistics Mapper Relocatable images of processes User Constraints Processes Layout (XML) Library Library Translation and linkage tools Packager creates Makefile in accordance with layout scheme and runs make for the loadable image building Packager Loadable Makefile Linkage tool Linkage tool Simulation/ Execution Loader 20 10

11 Input Example myfn in data In0 Out0 (Auto) realfir In0 Out0 (Auto) L In0 myfn3 Out0 In1 (Auto) out data myfn.c myfn(int16 in0[], int16 out0[]) { int16 i,x; for (i=0; i<in1len; i++) { x=in1[i] * in1[i]; send_output(0,x); } } myfn2 In0 Out0 ( typea) myfn2.ccs _myfn2:... X0:X7=*P0++8 Y0:Y7=*P1++8 M0=X0*Y0 M1=X1*Y1 M2=X2*Y2 M3=X3*Y3 M4=X4*Y4 M5=X5*Y5 M6=X6*Y6 M7=X7*Y7 A00=M0+M1 A20=M2+M3 A4=M4+M5 A6=M6+M7;....DONE 21 System Simulator Cycle accurate simulation High performance Allow to evaluate latency and computational overhead Possibility to connect two instances of the System Simulator to each other Provide debugging facilities 22 11

12 System Simulator SysSim contains Simulator Core (SC) and Individual Simulators (IS) Two abstraction layers for IS representation High level object Scheduled Object Object design principle: If being in state S1 and got an input signal In than after delay D change the state to S2 and produce an output signal Out Hardware Configuration File Debug queries Debugger User Application JTAG Host Data Driver Control control Debug events / RCA Device Driver responses JTAG Host Data Control RCA System Simulator Simulator Core AFE Data (to data files or to another AFE Data Host Data instance of the Simulator) Individual simulator Scheduled Objects Layer: efficient cycle-accurate scheduling 23 Simulation Performance Source D flip-flop D flip-flop Destination N instances Comparing SystemC core and SysSim core SC_METHOD process was used for SystemC Simulated object is N instances of D flip-flop flop objects Simulation on Intel 2.4 GHz Pentium 4 4*4 Mesh (~1000 objects), 400 MHz 1 sec simulation takes ~100 hours for SystemC Core and ~13 hours for SySim Core Simulation time (sec N of scheduled objects CTL core SystemC core 24 12

13 Development Environment Concept Algorithm and Compiler point of view Tools Development Concepts Naive Phase : Manual program partitioning Manual code optimization Independent compiler tools Static hardware and software Mature Phase: Automatic program partitioning Automatic code optimization Common compiler tools Static hardware and software Advanced Phase: Macro architecture description tools Automatic generation of micro architecture description Automatic software tools generation Protocol partitioning for joint hardware -software optimization 26 13

14 Tools Development Naive Phase Enhanced Traditional Model Networking (communication architecture) Mapping (distributable compilation) Traditional tool-suite for RCA Complete development tool-suite Integration of tools for sequential programming Solution constraints Aided mapping (user-defined mapping of process to ) 27 Enhanced Traditional Model source C source source code for for ii code for C C Compiler Object Object 1 module Linker Executable module Assembly code for for jj code for FMCA C Compiler Assembler Object Object Object module 22 module Linker Executable module Specialized code for VMCA Configurator Reconfiguration vector Linker Executable module Make directives Link directives Description Translator Tiny Mapper RCA Linker Loadable image RCA Simulator 28 Debugger 14

15 Tools Development Mature Phase True distributable compilation Automated mapping Global optimization Intermodule optimization Optimization on heterogeneous environment Enhanced development tools C C Compiler with high-level IR generation High-level IR Linker Retargetable Code Generator 29 Distributable Compilation Architecture source C source source code code Assembly code code Specialized code code C Front-End Assembler Configurator IR IR 1 IR 1 IR IR 2 IR 2 IR IR IR 3 IR Libs IR Linker General IR Mapper IR for 1 IR for 2 IR for 3 CG for 1 CG for 2 CG for 3 Object module 1 Object module 2 Object module 3 Obj Libs Communications Technology 30 Lab 15

16 Tools Development Advanced Phase Distributable compilation Retargetable development tools Retargetable C Compiler (tunable CG and optimization) Retargetable Assembler (target architecture templates) Retargetable Simulator (for RCA configurations) Comprehensive Target Descriptive Language Target Tools Generator HDL code generation Joint hardware and software optimization 31 Co-Design Architecture Software Design Source Code for RCA Tools Generator RCA Hardware Design Comprehensive Target Description HDL Output High Level IR Target Representation Target Tools C Compiler CGi Assemblers RCA Simulator HDL (VHDL) Debugger 32 16

17 Summary RCA programming process characteristics Parallel running processes with message exchange Procedure level parallelism Partitioning-communication-aggregation-mapping based optimization cycle RCA software development env contains standard set of tools for Algorithm and source code development Source code translation and linking RCA software development environment contains specific set of tools for the optimization cycle 3 phases of software tools development Main goal of the naive and mature phases is to assure (manually or automatically) program code effectiveness Main goal of advanced phase is to assure joint hardware- software effectiveness of PHY/MAC algorithms implementation 33 Acknowledgements Ernest Tsui, Vladimir Pudovkin, Vladimir Pavlov, Sergey Mironov, Veronica Mikheeva, Tony Chun, Michael K. Chen 34 17