DSPACE: LISA Methodology
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1 DSPACE: LISA Methodology Maximilian Odendahl ESA DSP Day, Noordwjik, Institute for Communication Technologies and Embedded Systems
2 Outline 2 Introduction DSPACE Requirements LISA Methodology LISA 2.0 Language Overview Resources Operations DSPACE Results Demo
3 DSPACE Core 3 Issues and Requirements: Final architecture not known at the beginning Should be easily adaptable and extendable to cope with future standards and algorithms Needs a mature and stable software development environment Relatively short project time frame Raise the abstraction level of the processor model Use of a Processor Development Environment
4 Synopsys Processor Designer 4 History: LISA project at ICE LISATek Inc. CoWare Inc. Integrated, embedded processor development environment Unified processor model in LISA 2.0 language Automatic generation of: SW tools HW models
5 Modification / Refinement S O F T W A R E Traditional Processor Architecture Exploration 5 Requirements HLL language code (C/C++) Compiler Translating HLL programs into assembly code Target Architecture Design Processor Architecture Verification & Evaluation Assembly code Object code Executable binary Simulator Assembler Linker Translating assembly files into binary object code, which still contains unresolved symbols Resolving symbols in object files, linking them into a single executable program Debugger Profiler
6 Requirements Processor Design Flow with LISA 6 Assembler Disassembler Linker Simulator Verification & Evaluation Target Architecture LISA Description LISA Compiler HDL Model (VHDL, Verilog) Verification & Evaluation Main advantages of LISA: Modeling and modification of processors at a high level of abstraction. Automatic generation of software development tools Shortening the development time Consistency Generation of HDL Description Exploration Implementation
7 Exploration/debugger GUI 7 Application simulation Debugging Profiling Resource utilization analysis Pipeline analysis Processor model debugging Memory hierarchy exploration Code coverage analysis...
8 Outline 8 Introduction DSPACE Requirements LISA Methodology LISA 2.0 Language Overview Resources Operations DSPACE Results Demo
9 LISA Language Overview 9 Processor Description Language Formalized Description of Processor Resources Instruction Set Abstracted Hardware Behavior Timing Organized in Operations Modularity Reusability C/C++ based easy to learn integrate existing IP Multiple abstraction levels LISA 2.0
![RESOURCE { PROGRAM_COUNTER long PC; REGISTER bit[12] R[0.](/docs-images/94/122013059/images/10-4.jpg ".31]; CONTROL_REGISTER short ST; PIN IN bit[5] IRQ, NMI; RAM char pmem {.")
10 LISA Resources 10 RESOURCE section provides a unique, centralized definition of all processor resources e.g. registers, memories, etc. RESOURCE { PROGRAM_COUNTER long PC; REGISTER bit[12] R[0..31]; CONTROL_REGISTER short ST; PIN IN bit[5] IRQ, NMI; RAM char pmem {... ; RAM char dmem1 {... ; RAM int dmem2 {... ; PROGRAM_COUNTER REGISTERS MEMORIES
11 LISA Operation Sections 11 LISA operation DECLARE CODING SYNTAX References to other operations Binary coding Assembly syntax Resource access, e.g. registers EXPRESSION Initiate downstream operations in pipe ACTIVATION Computation and processor state update BEHAVIOR
12 OPERATION (1) 12 OPERATION add { BEHAVIOR { R[dest] = R[src1] + R[src2]; C Code OPERATIONs are used to describe the behavior of functional units in the processor.
13 OPERATION (2) 13 OPERATION add { DECLARE { GROUP src1 = { reg ; GROUP src2 = { reg ; GROUP dest = { reg ; BEHAVIOR { R[dest] = R[src1] + R[src2]; OPERATIONs are used to describe the behavior of functional units in the processor.
14 OPERATION (3) 14 OPERATION add { DECLARE { GROUP src1 = { reg ; GROUP src2 = { reg ; GROUP dest = { reg ; CODING {0b10001 dest src1 src2 SYNTAX { add src1, src2, dest BEHAVIOR { R[dest] = R[src1] + R[src2]; Additionally, OPERATIONs contain information about coding and syntax.
15 OPERATION (4) 15 add r3,r4,r5 OPERATION add { DECLARE { GROUP src1 = { reg_idx ; GROUP src2 = { reg_idx ; GROUP dest = { reg_idx ; SYNTAX { add src1, src2, dest CODING {0b10001 dest src1 src2 BEHAVIOR { dest = src1 + src2; Assembler+Linker Loader+Decoder r5 = r3 + r4;
16 Outline 16 Introduction DSPACE Requirements LISA Methodology LISA 2.0 Language Overview Resources Operations Results Demo
17 Implementation Results 17 DSPACE core running at 125 MHz 1.0 GOPS 750 MFLOPS Increase of 17 and 13 times, respectively, compared to Atmel s TSC21020F area of 370 kgates (180nm standard-cell library, typical) lines of LISA source code lines of generated VHDL
18 LISA Introduction Thank you for your attention! Questions?
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