Laboratory Exercise 1

Transcription

1 Laboratory Eercie Switche, Light, and Multipleer The purpoe of thi eercie i to learn how to connect iple input and output device to an FPGA chip and ipleent a circuit that ue thee device. We will ue the witche SW 5 on the BASYS board a input to the circuit. We will ue light eitting diode (LED) and 7-egent diplay a output device. Part I The BASYS board provide 6 toggle witche, called SW 5, that can be ued a input to a circuit, and 8 red light, called LEDR 7, that can be ued to diplay output value. Figure how a iple Verilog odule that ue thee witche and how their tate on the LED. Since there are 6 witche and light it i convenient to repreent the a vector in the Verilog code, a hown. We have ued a ingle aignent tateent for all 6 LEDR output, which i equivalent to the individual aignent aign LEDR[5] = SW[5]; aign LEDR[4]= SW[4]; aign LEDR[] = SW[]; The BASYS board ha hardwired connection between it FPGA chip and the witche and light. To ue SW 7 and LEDR 7 it i neceary to include in your Vivado project the correct pin aignent, which are given in the BASYS Uer Manual. For eaple, the anual pecifie that SW i connected to the FPGA pin N25 and LEDR i connected to pin AE2. A good way to ake the required pin aignent i to iport into the oftware the file called BASYS pin aignent.cv, which i provided on the BASYS Syte CD and in the Univerity Progra ection of Altera web ite. The procedure for aking pin aignent i decribed in the tutorial Vivado Introduction uing Verilog Deign, which i alo available fro Xilin. The file ue the nae SW[]... SW[7] and LEDR[]... LEDR[7] for the witche and light, which i the reaon we ued thee nae in Figure. // Siple odule that connect the SW witche to the LEDR light odule part (SW, LEDR); input [7:] SW; output [7:] LEDR; // toggle witche // red LED aign LEDR = SW; endodule Figure. Verilog code that ue the BASYS board witche and light. Perfor the following tep to ipleent a circuit correponding to the code in Figure on the BASYS board.. Create a new Vivado project for your circuit. Select a the target chip, which i the FPGA chip on the Xilin board. 2. Create a Verilog odule for the code in Figure and include it in your project.

2 . Include in your project the required pin aignent for the BASYS board, a dicued above. Copile the project. 4. Download the copiled circuit into the FPGA chip. Tet the functionality of the circuit by toggling the witche and oberving the LED. Part II Figure 2a how a u-of-product circuit that ipleent a 2-to- ultipleer with a elect input. If =the ultipleer output i equal to the input, and if =the output i equal to y. Part b of the figure give a truth table for thi ultipleer, and part c how it circuit ybol. y a) Circuit y y b) Truth table c) Sybol Figure 2. A 2-to- ultipleer. The ultipleer can be decribed by the following Verilog tateent: aign =( &) ( & y); You are to write a Verilog odule that include eight aignent tateent like the one hown above to decribe the circuit given in Figure a. Thi circuit ha two eight-bit input, X and Y, and produce the eight-bit output M. If = then M = X, while if = then M = Y. We refer to thi circuit a an eight-bit wide 2-to- ultipleer. It ha the circuit ybol hown in Figure b, in which X, Y, and M are depicted a eight-bit wire. Perfor the tep hown below. 2

3 7 y y 6 6 X Y M y a) Circuit b) Sybol. Create a new Vivado project for your circuit. Figure. An eight-bit wide 2-to- ultipleer. 2. Include your Verilog file for the eight-bit wide 2-to- ultipleer in your project. Ue witch SW 7 on the BASYS board a the input, witche SW 7 a the X input and SW 5 8 a the Y input. Connect the SW witche to the red light LEDR and connect the output M to the green light LEDG 7.. Include in your project the required pin aignent for the BASYS board. A dicued in Part I, thee aignent enure that the input port of your Verilog code will ue the pin on the Cyclone II FPGA that are connected to the SW witche, and the output port of your Verilog code will ue the FPGA pin connected to the LEDR and LEDG light. 4. Copile the project. 5. Download the copiled circuit into the FPGA chip. Tet the functionality of the eight-bit wide 2-to- ultipleer by toggling the witche and oberving the LED. Part III In Figure 2 we howed a 2-to- ultipleer that elect between the two input and y. For thi part conider a circuit in which the output ha to be elected fro our input u, v, w, Part a o f Figure 4 how how we can build the required 4-to- ultipleer by uing three 2-to- ultipleer. The circuit ue a -bit elect input 2 a nd ipleent the truth table hown in Figure 4b. A circuit ybol for thi ultipleer i given in part c of the figure. Recall fro Figure that an eight-bit wide 2-to- ultipleer can be built by uing eight intance of a 2- to- ultipleer. Figure 5 applie thi concept to define a two-bit wide 4-to- ultipleer. It contain three intance of the circuit in Figure 4a.

4 u v w a) Circuit u v w u v w b) Truth table c) Sybol DR and the output to the green LEDG and 4. 4.

5 Part IV Figure 6 how a 7-egent decoder odule that ha the three-bit input c 2 c c. Thi decoder produce even output that are ued to diplay a character on a 7-egent diplay. Table lit the character that hould be diplayed for each valuation of c 2 c c. To keep the deign iple, only four character are included in the table. The even egent in the diplay are identified by the indice to 6 hown in the figure. Each egent i illuinated by driving it to the logic value. You are to write a Verilog odule that ipleent logic function that repreent circuit needed to activate each of the even egent. Ue only iple Verilog aign tateent in your code to pecify each logic function uing a Boolean epreion. c 2 c c 7-egent decoder Figure 6. A 7-egent decoder. Perfor the following tep: c 2 c c Character F P G A Table. Character code. Create a Vivado project for your circuit and ipleent it in the Xilin FPGA board to dipaly one fo the four character uing a Verilog code SW 6 SW 5 SW 4 2 SW 9 SW 8 6 SW 5 SW 2 7-egent decoder Figure 7. A circuit that can elect and diplay one of four character. 5

6 odule part5 (SW, HEX); input [4:] SW; // toggle witche output [:6] HEX; // 7-eg diplay wire [2:] M; u 2bit 4to M (SW[6:5], SW[4:2], SW[:9], SW[8:6], SW[5:], SW[2:], M); char 7eg H (M, HEX); endodule // ipleent a 2-bit wide 4-to- ultipleer odule u 2bit 4to (S, U, V, W, X); input [:] S, U, V, W, X; output [2:] M;... code not hown endodule // ipleent a 7-egent decoder for F, P, G, A odule char 7eg (C, Diplay); input [:] C; // input code output [:6] Diplay; // output 7-eg code...code not hown endodule Figure 8. outline of the Verilog code for the circuit in Figure 7. Perfor the following tep.. Create a new Vivado project for your circuit. 2. Include your Verilog odule in the Vivado project. Connect the witche SW 6-5 to the elect input of each of the five intance of the three-bit wide 5-to- ultipleer. Alo connect SW 4 to each intance of the ultipleer a required to produce the pattern of character.connect the output of the ultipleer to the 7-egent diplay HEX, HEX2, HEX, and HEX.. Include the required pin aignent a per the contraint.xdc file for the BASYS board for all witche, LED, and 7-egent diplay. Copile the project. 4. Download the copiled circuit into the FPGA chip. Tet the functionality of the circuit by etting the proper character code on the witche SW 4 and then toggling SW 6 5 to oberve the rotation of the character. 7

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