The PULP Cores: A Set of Open-Source Ultra-Low- Power RISC-V Cores for Internet-of-Things Applications

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2017 Pasquale Davide Schiavone, Florian Zaruba Davide

Gasler, Stefan Mach, Giovanni Rovere, Germain Haugou,

Daniele Palossi, Andrea Marongiu, Fabio Montagna, Victor

1 The PULP Cores: A Set of Open-Source Ultra-Low- Power RISC-V Cores for Internet-of-Things Applications Pasquale Davide Schiavone, Florian Zaruba Davide Rossi, Igor Loi, Antonio Pullini, Francesco Conti, Florian Gasler, Stefan Mach, Giovanni Rovere, Germain Haugou, Manuele Rusci, Alessandro Capotondi, Giuseppe Tagliavini, Daniele Palossi, Andrea Marongiu, Fabio Montagna, Victor Javier Kartsch Morinigo, Simone Benatti, Lei Li, Eric Flamand, Frank K. Gürkaynak, Luca Benini 1 Department of Electrical, Electronic and Information Engineering 2 Integrated Systems Laboratory

2 Energy Efficient HW Sense MEMS IMU Analyze and Classify µcontroller Transmit Short range, medium BW MEMS Microphone ULP Imager EMG/ECG/EIT IOs 1 10 mw Low rate (periodic) data SW update, commands Long range, low BW 100 µw 2 mw Battery + Harvesting powered à a few mw power envelope Idle: ~1µW Active: ~ 50mW Davide Schiavone

3 RISC-V cores under development Low Cost Core Zero-riscy RV32IMC Micro-riscy RV32EC 32 bit 64 bit Core with DSP enhancements RV32IMCX SIMD HW loops Bit manipulation Fixed point Floating-point capable Core + FPU RV32IMFCX Linux capable Core Ariane RV64IMC Davide Schiavone

RISCY Core for Energy Efficient -Computation 4-stage pipeline RV32IM[F]C 40.7 69.3 kge 30 logic levels of critical path Coremark/MHz 3.

4 RISCY Core for Energy Efficient -Computation 4-stage pipeline RV32IM[F]C kge 30 logic levels of critical path Coremark/MHz 3.19 Includes various extensions psimd Fixed point Bit manipulations HW loops Working Chips in: UMC65 GF28 Versions taped out in: TSMC40LP Tape out soon: GF22 FDX Different Options: FPU: IEEE 754 single precision Iterative DIV/SQRT (7 cycles) Pipeline MAC, MUL, ADD, SUB, Cast Single cycle load, store, min, max, cmpetc Privilege support: Support subset of privilege mode M and U Davide Schiavone

RISCY ISA Extensions improve performance for (i

Auto-incr load/store HW Loop Packed-SIMD mv x5,

0(x11) addi x10,x10, 1 addi x11,x11, 1 add x2,

x12,x12, 1 bne x4, x5, Lstart 11 cycles/output

) bne x4, x5, Lstart 8 cycles/output lp.

setupi 25, Lend lw x2, 0(x10!) lw x3, 0(x11!

5 RISCY ISA Extensions improve performance for (i = 0; i < 100; i++) d[i] = a[i] + b[i]; Baseline Auto-incr load/store HW Loop Packed-SIMD mv x5, 0 mv x4, 100 Lstart: lb x2, 0(x10) lb x3, 0(x11) addi x10,x10, 1 addi x11,x11, 1 add x2, x3, x2 sb x2, 0(x12) addi x4, x4, -1 addi x12,x12, 1 bne x4, x5, Lstart 11 cycles/output mv x5, 0 mv x4, 100 Lstart: lb x2, 0(x10!) lb x3, 0(x11!) addi x4, x4, -1 add x2, x3, x2 sb x2, 0(x12!) bne x4, x5, Lstart 8 cycles/output lp.setupi 100, Lend lb x2, 0(x10!) lb x3, 0(x11!) add x2, x3, x2 Lend: sb x2, 0(x12!) 5 cycles/output lp.setupi 25, Lend lw x2, 0(x10!) lw x3, 0(x11!) pv.add.b x2, x3, x2 Lend: sw x2, 0(x12!) 1,25 cycles/output Small Power and Area overhead à Energy reduction in NT >3x Davide Schiavone

Zero-riscy Core for Energy Efficient Control-Tasks 2-stage pipeline RV32{I,E}[M]C 11.6 18.9 kge 30 logic levels of critical path Coremark/MHz RV32IMC 2.44 RV32EC 0.

6 Zero-riscy Core for Energy Efficient Control-Tasks 2-stage pipeline RV32{I,E}[M]C kge 30 logic levels of critical path Coremark/MHz RV32IMC 2.44 RV32EC 0.91 Optimized for area High resource sharing 3/4 cycles mul 1bit iterative divider Versions taped out in: UMC65 TSMC40LP Different Options: Zero-riscy: 32 GP registers, HW multiplier and division Micro-riscy: 16 GP registers, no HW resources for multiplications and divisions Davide Schiavone

Ariane Core for Linux 6-stage pipeline RV64IMC 185 kge

modes TLB Tightly integrated D$ and I$ Hardware PTW

01 Optimized for speed Synthesized for 1.5 GHz@0.

7 Ariane Core for Linux 6-stage pipeline RV64IMC 185 kge OoO execution In-order Commit M, S and U privilege modes TLB Tightly integrated D$ and I$ Hardware PTW Branch Prediction Scoreboarding Coremark/MHz 2.01 Optimized for speed Synthesized for 1.5 GHz@0.72V, SSG corner in GF22 FDX SOON OPEN-SOURCE Davide Schiavone

Rich SW tools Virtual platform implementation: C++ + Python Any ISS can be integrated (or1ksim, gdb simulator, riscv on-going) Timing model: Fully-event based Includes timing models for

8 Rich SW tools Virtual platform implementation: C++ + Python Any ISS can be integrated (or1ksim, gdb simulator, riscv on-going) Timing model: Fully-event based Includes timing models for interconnects, DMACs, memories Simulation performance: Around 1MIPS simulation speed Functionally aligned with HW Timing accuracy is within 10-20% of target HW Debug with GDB: Supports RTL and virtual platform Uses a bridge to inject JTAG requests Profiling with KCachegrind: Supports PC traces from RTL and VP Several events can be catched (PC, cycles, I$ miss, stalls ) Davide Schiavone

perturbated environment (random interrupts,

maximize the code coverage IIS and the RTL

have to produce the same output Constraints.

9 Recent effort in Core Verification Constrained Pseudo-Random Test in a perturbated environment (random interrupts, stalls) The ugp program generator tires to maximize the code coverage IIS and the RTL model receive the same random program and have to produce the same output Constraints.XML Golden Model ETH-IIS Genetic PG.S program.s DUT RTL Simulation Code Coverage Interrupt Req Instruction Stalls Stalls == PASS/FAIL Davide Schiavone

10 PULP/PULPino Users + Several Universities Davide Schiavone

PULP Platform: new controller PULPissimo CLUSTER TIGHTLY COUPLED DATA MEMORY L2 Bank L2 Bank ROM RELEASE Q1 2018 à New

TIMER Zeroriscy POWER DEBUG Cluster Bus DMA Event Timer MMU Peripheral Int.

11 PULP Platform: new controller PULPissimo CLUSTER TIGHTLY COUPLED DATA MEMORY L2 Bank L2 Bank ROM RELEASE Q à New Int-Controller DEBUG PWM GPIO SPI M CAMIF I2C UART APB Bus µdma Logarithmic Interconnect CLK Event Peripheral Int. TIMER Zeroriscy POWER DEBUG Cluster Bus DMA Event Timer MMU Peripheral Int. à udma for efficient peripheral data transfer Logarithmic Interconnect à RISCY or Zero-Riscy Shared FPU à New SDK à Tape out soon: GF22 Shared FPU Shared Instruction Cache HYPER Davide Schiavone

Research Collection. KISS PULPino - Updates on PULPino updates on PULPino. Other Conference Item. ETH Library

Research Collection. KISS PULPino - Updates on PULPino updates on PULPino. Other Conference Item. ETH Library Research Collection Other Conference Item KISS PULPino - Updates on PULPino updates on PULPino Author(s): Pullini, Antonio; Gautschi, Michael; Gürkaynak, Frank Kagan; Glaser, Florian; Mach, Stefan; Rovere,