AccuCell Technical Training. AccuCell Commands & Concepts

Transcription

1 AccuCell Technical Training AccuCell Commands & Concepts

2 Agenda Introduction to AccuCell and AccuCore Cell Characterization Introduction to AccuCell Getting Started with Accucell Methods of Characterization Sequential Cells Power Characterization - 2 -

3 Silvaco Characterization Flow AccuTools Cell Block Core Cell Block/Core Functional Extraction Vector Generation Dynamic Simulation Model Generation Timing Power Function Timing Block/Core Partitioning Characterization Static Timing Model Generation Timing Power Function Model Generation - 3 -

4 Scalable Characterization Solution Silvacos characterization technology scales-up from standard cells to hard IP cores Full-Chip Environment Timing Models.lib (all paths).lib (compressed).lib (black box) Functional Models Verilog (gate level) Power Models.lib (standard cell) - 4 -

5 Agenda Introduction to AccuCell and AccuCore Cell Characterization Introduction to AccuCell Getting Started with AccuCell Methods of Characterization Sequential Cells Power Characterization - 5 -

6 Cell Characterization Challenges Extensive set-up Function determination, Vector generation Optimum load and slope tables Custom Cells I/O Pads, Dynamic, DCVS, Adders, Comparators Long Run Time Setup/Hold Long Vector Set Accuracy Vector dependent, Measurement techniques Results Validation Tool Maintenance New formats and standards, design templates Scripts re-vamping Conventional Tools Script Based Flow Manual Function Identification Manual description of transitions Convert transition to Vectors Run Simulation Extract Results Build model - 6 -

7 Agenda Introduction to AccuCell and AccuCore Cell Characterization Introduction to AccuCell Getting Started with Accucell Methods of Characterization Sequential Cells Power Characterization - 7 -

8 The AccuCell Advantage Conventional Approach Manual Function Identification Manual description of transitions Silvaco s approach AccuCell Convert transition to Vectors Run Simulation Extract Results Build model Library Validation - 8 -

9 Vectors Should Drive Characterization Automatic function extraction Automatic Smart vector generation It is important to only generate the necessary vectors, complete with no redundancies, for the specific cell characterization needs: Delays Output Slews Input Capacitance Max Capacitance Setup and Hold Power Automatic table selection Supports complex cell Domino and Dynamic Logic Differential Logic Cells with many inputs - 9 -

10 Where to Use AccuCell New library characterization Re-characterize commercial libraries Create custom PVT for design Migrate to a new process or foundry Characterize custom cell libraries Characterize complex cells Domino/Dynamic Cells Cells with a large number of inputs and/or outputs QA of existing libraries AccuCell is well-suited for High Performance, Low Power, and Timing Critical Cell Based design flows!

11 AccuCell Flow Config File Liberty.lib SPICE Netlist AccuCell Function Extraction Vector Generation SPICE Simulations Model Generations Verilog Datasheet SPICE Engines SmartSpice HSPICE Spectre Eldo Automatic function extraction: Advanced CMOS circuit handling: Domino, DVCS, Large & complex cells Automatic vector generation: Employs Smart vector algorithm for complete vector set with no redundancies Simultaneous switching State/path dependent delays Input Capacitance Max_capacitance for output Tri-state conditions Setup/hold, recovery/removal, and MPW Power Automatic Table Selection (ATS): Auto Selected/Optimized input slope and output capacitance table indices to reduce error Automatic model generation No intermediate steps and template needed Outputs Liberty.lib (timing, power, leakage, noise) Statistical verilog Datasheets

12 AccuCell SPICE Simulation Engines Internal SmartSpice with high-speed API runs up to 20x faster while maintaining high-accuracy External HSPICE Spectre Eldo

13 Agenda Introduction to AccuCell and AccuCore Cell Characterization Introduction to AccuCell Getting Started with AccuCell Methods of Characterization Sequential Cells Power Characterization

14 LAB 1 Objectives Purpose: To become familiar with setting up cfg files and running AccuCell. Setup a AccuCell run Run AccuCell to characterize a single cell Run AccuCell to characterize a cell library Familiarize yourself with the output formats of AccuCell

15 AccuCell Setup Configuration Files Library.cfg../library Global Library Cell Characterization Settings (unless cell.cfg overrides) nand.cfg nor.cfg dff.cfg aoi.cfg../library/nand../library/nor../library/dff../library/aoi Individual Cell Characterization Settings (can override library.cfg global settings)

16 AccuCell Setup Library Config File LIBRARY_NAME MODEL_TYPE Lib.cfg lib1 synthesis # SPICE COMMANDS SPICE_TYPE SMARTSPICE_OPTIONS MOSFET_TYPE MOSFET_TYPE smartspice {scale=1.0e-6} p pmos n nmos # Specify Process File (mosfet model)information INC_CMD /home/models/param_file LIB_CMD /home/models/bsim3v3.1 typ TEMP 25 SUPPLY_V_HIGH 1.8 TRAN_ANALYSIS_STEP

17 ACCUCELL Setup Individual Cell Config Files nand3.cfg #nand3.cfg IN_FILE_NAME CELL_NAME TOP_SPICE_SUBCKT INPUTS OUTPUTS POWERS GROUNDS nand3.spi nand3 nand3 a b c y vdd gnd

18 AccuCell Setup TCL Command File gen_lib lib.list library.cfg library.tcl INV NAND2 NOR2 AOI222 DFF LAT1.. lib.list

19 Running AccuCell gen_lib lib.list library.cfg unix% accucell library.tcl & tee log

20 AccuCell Auto Config File Setup (lib2cfg) Silvaco also provides the lib2cfg routine which automatically creates the configuration files from an existing Liberty.lib file Library_sps.lib lib2cfg Library.cfg nand.cfg nor.cfg dff.cfg. aoi.cfg

21 Agenda Introduction to Silvaco Cell Characterization Introduction to AccuCell Getting Started with Accucell Methods of Characterization Sequential Cells Power Characterization

22 LAB 2 - Objectives Purpose: To become familiar with AccuCell s flexible methods of cell characterization. Run AccuCell with slope and capacitance tables Run AccuCell with ATS Calculate input pin capacitance for library cells

23 Input Slopes and Output Caps: User Defined Tables lib.cfg #------COMMANDS FOR INPUT SLOPES and #------OUTPUT LOADS SLOPE_LOWER_THR 0.3 SLOPE_UPPER_THR 0.7 SLOPE_TABLE { } CAP_TABLE { }

24 Input Slopes and Output Caps: Automatic Table Selection Automated means of determining the minimum number of points needed for accurate characterization Eliminates the need for costly Over-Sampling Significantly reduces runtime

25 Input Slopes and Output Caps: Automatic Table Selection (ATS) ATS is an automated means of determining the minimum number of points needed for accurate characterization Eliminates the need for Over-Sampling Significantly reduces runtime

26 Input Slopes and Output Caps: Automatic Table Selection lib.cfg #---- COMMANDS for ATS (Automatic Table Select) AUTO_TABLE_SELECT {<cap_min> <cap_max>} {<slew_min> <slew_max> ATS_MAX_DELAY_ERROR 0.05 ATS_MAX_SLEW_ERROR

27 Input Pin Cap Integrate Method Technique includes finding the Cin got both the rising and failing output conditions then AVERAGING the two for the final input capacitance (CIN) for the input pin. CALC_C_EFF 1 C_EFF_RISE_SLOPE 0.05 C_EFF_FALL_SLOPE 0.05 CUR_MEAS_PERIOD

28 Max Capacitance Techniques include the following steps: CHAR_MAXCAP 1 MAXCAP_DEGRADATION 0 MAXCAP_SLEW 0.4 MAXCAP_START User determines the maximum allowable delay or output slope for the Cell (described in terms of degradation). 2. AccuCell then determines what C=? will produce the described output slope or delay degradation. 3. A bi-section algorithm is employed during the converging process to obtain the ultimate max cap value

29 Data Sheets Data Sheets generated by AccuCell enhances usability and readability of the characterization data

30 Agenda Introduction to Silvaco Cell Characterization Introduction to AccuCell Getting Started with Accucell Methods of Characterization Sequential Cells Power Characterization

31 LAB 3 Objectives To become familiar characterizing Sequential cells using AccuCell Setup an equation file (*.eqn) Setup AccuCell for Setup/Hold Characterization. Run AccuCell on a sequential cell

32 Setup/Hold Characterization Employs very fast BiSection Algorithm User selectable criteria methods: Pass/fail or Pass/fail with degradation Pass/Fail: User selectable Upper/Lower thresholds Degradation: User selectable Percent (%) Degradation

33 Setup/Hold Characterization: Degradation Method Employs very fast BiSection Algorithm Degradation: User selectable percent (%) Degradation

34 AccuCell Commands for SETUP/HOLD lib.cfg # COMMANDS for SETUP & HOLD SETHLD_2D 1 SH_DATA_SLOPE_TABLE { } SH_CLK_SLOPE_TABLE { } # for Delay Degradation (15% degradation) SETHOLD_DELAY

35 What does Single_Simulation do? SINGLE_SIMULATION 1 Reduce run time significantly if a table is needed for setup/hold AccuCell puts.data statement in the spice deck to do single simulation for setup/hold instead of multiple simulations For external simulators only

36 User Defined Equations and Explicit Tables dff.cfg dff.eqn IN_FILE_NAME CELL_NAME TOP_SPICE_SUBCKT #EQN_FILE_NAME #TBL_FILE_NAME dff.spi dff dff dff.eqn dff.tbl q.0:= q.1:= nq.0:=, nq.0:= ~d & nr & ns & main- ~nr & ns; d & nr & ns & main- nr & ns; d & nr & ns & main- nr & ns; ~d & nr & ns & main- ~nr & ns; CLOCKS INPUTS OUTPUTS main ck d nr ns nq q dff.tbl POWERS GROUNDS vdd gnd Please refer to the explict table in the tutorial or Users Guide for more details. Note: Equations and/or table files are rarely necessary and typically only used for complex cells. It is NOT necessarily required for flip-flop or latches. Use either.eqn or.tbl method but NOT both at the same time in the.cfg file

37 Recovery and Removal AccuCell Config Command: CHAR_RECREM <0 or 1> Where 1 requires AccuCell to run recovery and removal calculations. The default is 0 AccuCell Operation AccuCell generates a table for recovery and removal values. The table indices are the same as those for synchronous pin setup and hold value. That is, they are also defined by the following two configuration commands: SH_DATA_SLOPE_TABLE {..} SH_CLK_SLOPE_TABLE {..} Just like for setup and hold measurements, AccuCell also employs bi-section method to perform the recovery and removal measurements

38 Clock Minimum Pulse Width Employs very fast Bisection Algorithm Supports <Vdd (runt) pulses to find fail point User-selectable minimum level for runt pulse (Vdd/2 to Vdd) User selectable criteria methods: Pass/fail or Pass/fail with Degradation Pass/Fail: User selectable Upper/Lower thresholds Degradation: User selectable Percent (%) Degradation Uses SETHOLD_ parameters to control characterization

39 Gated Clock Checks Characterize setup/hold for clken->clk Currently supported in SVC only CLOCKS main clk OUTPUTS gclk CLOCK_ENABLE clken : CLK_ENABLE_ACTIVE_EDGE {clk r}

40 Load Dependency Between Output Pins Within a Cell, the delay of a given buffered output of a cell is dependent upon its own loading as well as the loading on any combinationally connected un-buffered output. UNBUF_OUT_LIST {{NQ Q negative_unate} { } { } } For the example above, the CLK->Q delay is dependent on the load presented on NQ. In AccuCell, the user can specify that Characterization be done from CLK->NQ and then NQ->Q using the command UNBUF_OUT_LIST Excerpt from Synopsys.lib pin (Q) { : timing { related_pin: NQ timing_sense: negative_unate : }

41 Characterizing with Active Drivers By default a voltage source with piecewise linear waveform is added directly to the input pins of the cell being characterized Optional method a user defined buffer is inserted, and the voltage source is applied to the input of the applied buffer #----COMMANDS for Active Drivers # user-defined buffer sub-circuit BUF_SUBCKT buf_ckt/home/cust/buffer.sp buffer_ckt {out in} # user-defined load sub-circuit LOAD_SUBCKT load_ckt/home/cust/load.sp load_ckt #multiplier for slope table SLEW_LOAD_TABLE { }

42 Tri-states Characterization Characterizes tri-state cells Function extracted automatically Measure Input to Output arcs Enable to Output arcs

43 Tri-state Measurement Cell is characterized as it is used in the design Driving another tri-state cell Do not have to measure transistors being on or off No resistors needed for setup of the Z state initial condition

44 Tri-state Measurement Connect two cells together with specified load Apply vectors Force one cell to go from a logic 1 on the output to a Z Force the other cell to go from a Z to a logic 0 Repeat for 0 to 1 transition

45 Agenda Introduction to AccuCell and AccuCore Cell Characterization Introduction to AccuCell Getting Started with Accucell Methods of Characterization Sequential Cells Power Characterization

46 LAB 4 - Objectives To become familiar with using AccuCell for Power Characterization

47 Need for Power Characterization Low power applications Stand by time is critical for all battery powered devices High Performance applications Higher operating frequencies Power bus sizing Cooling issues

48 Static Power Characterization Static (Leakage) Power: Measured by DC means with optional state dependence Constant power dissipated by the cell in steady state after the vector is applied and all transitions are stabilized Sub-threshold leakage from source to drain; Current flow through reverse biased diode (diffusion layer & substrate) Majority of power dissipation when circuit is inactive Less than 30% of total dissipation when circuit is active

49 Dynamic Power Characterization Dynamic Power: Power dissipated when an input transition is being made charging/discharging internal and external capacitive loads on the output; short circuit current from VDD to GND due to all transistors on or partially on during switching event Concurrently with timing characterization as avg Vdd current Switching Power Charge and discharge the loads Up to 80%-95% of total power dissipated Measurement Apply input vectors Measure the power dissipation through the capacitor Hidden Power Measure when inputs switch but outputs do not 0 1 Charge/Discharge

50 Power Characterization Model AccuCell uses the following circuit configuration for power characterization:

51 AccuCell Power Measurement Advantage Current based! Curve s nature: Peak, Monotonic, local MINs or MAXs, etc. Signal-processing-lie technique to filter unwanted numerical noises

52 AccuCell Commands for POWER Characterization lib.cfg # POWER CHARACTERIZATION COMMANDS CHAR_POWER 1 CHAR_POWER_METHOD average LEAKAGE_POWER_UNIT µw

53 State-based Function Extraction Primitive ff_12in_udp (12in.d.clk.svc.notifier): Output 12in: reg 12in: Input d.clk.svc.notifier table rl?:?:0; lr?:?:0; Fl?:?:1 0r?:?:1; *0?:?:-;?f?:?:-;??*:?:x; endtable endprimitive This algorithm finds logic loops and their state keeping nodes. It then infers clocks and generates an edge-sensitive UDP for each state element primitive ff_q_udp (q.clk. 12in.svc.notifier ): output q : reg q: Input clk.12in.svc.notifier: table rl?:?:0; lr?:?:0; Fl?:?:1 0r?:?:1; *0?:?:-;?f?:?:-;??*:?:x; endtable endprimitive

54 Verilog TestBench Module test: reg[10:0] dr; reg [10:0] clkr; Wire q; Integer index,count: ff ff(q,d,clk); Initial Begin dr=11 b : clkr=11 b ; for (count=11;count>0;count=count-1 begin index=count-1; d=dr[index]; clk = clkr [index]; end $finish; end Initial $monitor($time, %b%b%b,d,clk,q); endmodule Module ff (q, d, clk); Output q; Input d, clk ; reg svc_notifiers; specify (posedge clk=> (q:clk)) = (0:0:0:0:0:0): delays are tris.tfall $width (posedge clk, 0:0:0. 0:0:0, svc_notifier): $setup (d, posedge clk, 0:0:0, svc_notifier): $hold (posedge clk, d, 0:0:0, svc_notifier): endspecify Wire 12in; ff_q_udp ff_q_udp_inst (q, clk. 12in.svc_notifier ); Ff_12in_udp ff_12in_udp_inst (12in, d, clk.svc_notifier); endmodule A verilog testbench module is automatically generated to exercise the cell s verilog functionality

55 Verilog Timing Timing metrics are represented in a specify block An SDF annotation flow is supported, so all values in the specify block (min:ty:max) are set to zero. Unit delays for functional simulation are not instantiated Timing Checks $setup $hold $width $recover $removal (not supported by all simulators) VLOG_REMOVAL_TC_SUPPORTED controls suppression of this statement State dependent paths, polarity, and tristate enables are supported

56 Sample Verilog module nor (out, in1, in2); output out; input in1, in2; reg svc_notifier; specify if ((!in2)) (in1-=> out) = (0:0:0, 0:0:0); // delays are tris,tfall if none (in1-=>out) = (0:0::0, 0:0:0); // delays are tris,tfall if ((!in1)) (in2 -=> out) = (0:0:0, 0:0:0); // delays are tris,tfall ifnone (in2-=>out) = (0:0:0, 0:0:0); // delays are tris,tfall endspecify wire net_out_1; not ( net_out_1, in2 ) ; not ( out_sel_,in1 ) ; and ( out, net_out_1, out_sel_) ; endmodule module or (out, in1, in2); output out; input in1, in2; reg svc_notifier; specify if ((!in2)) (in1+=> out) = (0:0:0, 0:0:0); // delays are tris,tfall if none (in1+=>out) = (0:0::0, 0:0:0); // delays are tris,tfall if ((!in1)) (in2 +=> out) = (0:0:0, 0:0:0); // delays are tris,tfall ifnone (in2+=>out) = (0:0:0, 0:0:0); // delays are tris,tfall endspecify or ( out, 1n2, in1 ); endmodule module nand (out, in1, in2); output out; input in1, in2; reg svc_notifier; specify if ((in2)) (in1-=> out) = (0:0:0, 0:0:0); // delays are tris,tfall if none (in1-=>out) = (0:0::0, 0:0:0); // delays are tris,tfall if ((in1)) (in2 -=> out) = (0:0:0, 0:0:0); // delays are tris,tfall ifnone (in2-=>out) = (0:0:0, 0:0:0); // delays are tris,tfall endspecify wire net_out_1; not ( net_out_1, in2 ) ; not ( out_sel_,in1 ) ; or ( out, net_out_1, out_sel_) ; endmodule module and(out, in1, in2); output out; input in1, in2; reg svc_notifier; specify if ((in2)) (in1+=> out) = (0:0:0, 0:0:0); // delays are tris,tfall if none (in1+=>out) = (0:0::0, 0:0:0); // delays are tris,tfall if ((in1)) (in2+-=> out) = (0:0:0, 0:0:0); // delays are tris,tfall ifnone (in2+=>out) = (0:0:0, 0:0:0); // delays are tris,tfall endspecify or ( out, 1n2, in1 ); endmodule

57 I/O Cell Characterization Multi-Voltage I/O Cells Bi-Directional I/O Cells Open drain, Pull-up keeper Schmitt trigger Characterization: Delays/Slews Tri-state Measurements Capacitance Calculations

58 Multiple Job Submission Allows multiple cells to be characterized simultaneously Uses industry standard SUN Grid User selects which machines are available for use

59 Summary AccuCell for automated cell library characterization Automatic function extraction Automatic smart vector generation Automatic Table Selection (ATS) - accuracy Supports complex cells Domino and dynamic logic Differential logic Cells with many inputs Supports power characterization