Chapter 15: Design Examples. CPU Design Example. Prof. Soo-Ik Chae 15-1

Transcription

1 CPU Design Example Prof. Soo-Ik Chae 5-

2 Partitioned Sequential Machine Datapaths Datapath Unit External Control Inputs Control Unit Finite State Machine Control signals Datapath Logic Clock Datapath Registers Status signals Clock 5-2

3 Application-Driven Architecture Application Architecture Instruction Set Control Sequence Control Unit FSM 5-3

4 RISC ALU Chapter 5: Design Examples Digital circuits are designed to perform arithmetic and/or logic operations, or in general a mixture of them Arithmetic operations : ADD, SUB, MUL, DIV etc. Logic operations : NOT, AND, OR etc. A mathematical problem usually can be decomposed into a number of arithmetic and/or logic operations which may be executed serially or in parallel. However, to save the cost of hardware circuits, usually only one copy of circuit is built for each specific arithmetic or logic function. As a result, the mathematical problem is rearranged into a sequential order of the combinations of these operations. E.g. : partition D = A + B + C into D A + B followed by D D + C These arithmetic or logic circuits are collected together to form an arithmetic and logic unit (ALU), and a set of systematic methods are created for this ALU to invoke the functions built in the ALU These methods are collectively referred to as the instruction set, which may also involve memory access and/or data movement 5-4

5 RISC vs CISC Chapter 5: Design Examples To support the functions of ALU, a number of data elements such as registers and counters are also necessary to help bring data from memory/register to the inputs of ALU and store the output of ALU to memory or registers The entire set of supporting elements plus the ALU as well as its accompanying instruction set is referred to as the central processing unit (CPU) Central processing unit (CPU) As it is suggested by its name, all arithmetic operations are executed by this unit one instruction a time. There are two types of design methodologies for the instruction sets of CPU Reduced instruction-set computers (RISC), which features o A small number of instructions that execute in short cycles o A small number of cycles per instruction Complex instruction-set computers (CISC) 5-5

6 RISC Stored Program Machine (SPM) A RISC store-program machine (SPM) consists of three functional units : a processor, a controller and memory Program instructions and data are stored in memory Instructions are fetched from memory synchronously, decoded and executed to Operate on data with ALU Change the contents of storage registers Change the content of the program counter (PC), instruction register (IR) and the address register (ADD_R) Change the content of memory Retrieve data and instructions from memory Control the movement of data on the system busses 5-6

7 RISC Stored Program Machine (SPM) Chapter 5: Design Examples 5-7

8 Control Functions Functions of the control unit: Determine when to load registers Select the path of data through the multiplexers Determine when data should be written to memory Control the three-state busses in the architecture. 5-8

9 Control Signals Control Signal Action Load_Add_Reg Loads the address register RISC_SPM Load _PC Load_IR Loads Bus_2 to the program counter Loads Bus_2 to the instruction register Controller Load_R Load_R Processor R R PC IR Inc_PC Increments the program counter Load_R2 R2 Sel_Bus Mux Selects among the Program_Counter, Load_R3 Load_PC R3 Sel_Bus_2_Mux R, R, R2, and R3 to drive Bus_ Selects among Alu_out, Bus_, and Inc_PC instruction Sel_Bus Mux Load_IR Mux_ Bus_ memory to drive Bus_2 Load_Add_Reg Load_Reg_Y Reg_Y Load_R Loads general purpose register R Load_R Loads general purpose register R opcode ALU Memory Load_R2 Load_R3 Load_Reg_Y Load Reg_Z Loads general purpose register R2 Loads general purpose register R3 Loads Bus_2 to the register Reg_Y Stores output of ALU in register Reg_Z Load_Reg_Z zero Sel_Bus_2_Mux write alu_zero_flag Zflag Reg_Z Bus_2 2 Mux_2 mem_word Add_R ad dr es s write Loads Bus_ into the SRAM memory 5-9

10 RISC SPM: Instruction Set [] The design of the controller depends on the processor's instruction set. RISC SPM has two types of instructions. Short Instruction 8 bits (basic arithmetic) opcode source destination Long Instruction 6 bits (accessing memory) opcode source destination address don't care don't care 5-

11 RISC SPM: Instruction Set [2] Instruction Set Single-Byte instruction NOP ADD : Dest Source + Des AND : Dest Source & Des. NOT : Dest Source SUB : Dest Source - Des Two-Byte instruction RD : Dest Memory WR : Memory Source BR : PC Address BRZ : PC Address if zero flag == Opcode Source Dest. Opcode Source Dest. X X Address 5-

12 RISC SPM: Instruction Set [3] Instr Instruction Word Action opcode src dest NOP???? none ADD src dest dest <= src + dest SUB src dest dest <= dest - src AND src dest dest <= src && dest NOT src dest dest <= ~src RD*?? dest dest <= memory[add_r] WR* src?? memory[add_r] <= src BR*???? PC <= memory[add_r] BRZ*???? PC <= memory[add_r] HALT???? Halts execution until reset * Requires a second word of data;? denotes a don't care. 5-2

13 Controller Design Three phases of operation: fetch, decode, and execute. Fetching: Retrieves an instruction from memory (2 clock cycles) Decoding: Decodes the instruction, manipulates datapaths, and loads registers ( cycle) Execution: Generates the results of the instruction (,, or 2 cycles) 5-3

14 Controller States [] S_idle State entered after reset is asserted. No action. S_fet S_fet2 Load the Add_R with the contents of the PC Load the IR with the word addressed by the Add_R, Increment the PC S_dec Decode the IR Assert signals to control datapaths and register transfers. S_ex Execute the ALU operation for a single-byte instruction, Conditionally assert the zero flag, Load the destination register 5-4

15 Controller States [2] S_rd S_rd2 Load Add_R with the second byte of an RD instruction Increment the PC. Load the destination register with memory[add_r] S_wr S_wr2 Load Add_R with the second byte of a WR instruction, Increment the PC. Write memory[add_r] with the source register S_br S_br2 Load Add_R with the second byte of a BR instruction Increment the PC. Load the PC with the memory[add_r] S_halt Default state to trap failure to decode a valid instruction Which states are similar? 5-5

16 RISC-SPM controller : The machine has three phases of operation: fetch, decode and execute A total states S_idle: initial state S_fet: addr reg PC, S_fet2: load instruction mem[addr] S_dec: decode the instr and assert control signals to datapath S_ex: execute the ALU for single-byte instr and load dest reg S_rd: addr reg 2nd byte of a RD instruction and PC ++ S_rd2: dest mem [S_rd] S_wr: addr reg 2nd byte of a WR instruction and PC ++ S_wr2: mem [S_wr] source S_br: addr reg 2nd byte of a BR instruction and PC++ S_br2: PC mem [S_br] S_halt : trap failure to decode a valid instruction 5-6

17 Instruction Sequence Fetch instruction from memory Decode instruction and fetch operands Execute instruction ALU operations Update storage registers Update program counter (PC) Update the instruction register (IR) Update the address register (ADD_R) Update memory Control datapaths 5-7

18 Controller ASM: NOP/ADD/SUB/AND S_idle rst Instruction Fetch RISC_SPM S_fet / Sel_PC Sel_Bus_, Load_Add_R S_fet2 / Sel_Mem, Load_IR, Inc_PC 2 Controller Load_R Processor R PC Load_R R IR Instruction Decode Execute Load_R2 R2 S_dec 3 Load_R3 Load_PC Inc_PC R3 NOP src = R Sel_R Sel_Bus_ Load_Reg_Y S_ex 4 dest = R Sel_R Sel_ALU Load_R Load_Reg_Z instruction Sel_Bus Mux Load_IR Load_Add_Reg Load_Reg_Y Reg_Y Mux_ Bus_ ADD src = R Sel_R Sel_Bus_ Load_Reg_Y dest = R Sel_R Sel_ALU Load_R Load_Reg_Z opcode ALU Memory SUB AND src = R2 Sel_R2 Sel_Bus_ Load_Reg_Y Sel_R3 Sel_Bus_ Load_Reg_Y dest = R2 Sel_R2 Sel_ALU Load_R2 Load_Reg_Z Sel_R3 Sel_ALU Load_R3 Load_Reg_Z Load_Reg_Z zero Sel_Bus_2_Mux write alu_zero_flag Reg_Z Zflag Bus_2 2 Mux_2 mem_word Add_R ad dr es s

19 Controller ASM: NOT S_idle rst RISC_SPM Instruction Fetch Controller Processor S_fet / Sel_PC Sel_Bus_, Load_Add_R S_fet2 / Sel_Mem, Load_IR, Inc_PC 2 Load_R Load_R R R PC IR Load_R2 R2 Instruction Decode Execute Load_R3 Load_PC R3 S_dec 3 Inc_PC instruction Sel_Bus Mux Mux_ Load_IR Bus_ NOP src = R Sel_R Sel_Bus_ dest = R Load_R Sel_ALU Load_Reg_Z Load_Add_Reg Load_Reg_Y Reg_Y opcode ALU Memory... src = R Sel_R Sel_Bus_ dest = R Load_R Sel_ALU Load_Reg_Z Load_Reg_Z alu_zero_flag Reg_Z mem_word ad dr es s NOT src = R2 Sel_R2 Sel_Bus_ dest = R2 Load_R2 Sel_ALU Load_Reg_Z zero Sel_Bus_2_Mux write Zflag Bus_2 2 Mux_2 Add_R... Sel_R3 Sel_Bus_ Load_R3 Sel_ALU Load_Reg_Z 5-9

20 Controller ASM: RD S_idle rst Instruction Fetch RISC_SPM S_fet / Sel_PC Sel_Bus_, Load_Add_R S_fet2 / Sel_Mem, Load_IR, Inc_PC 2 Controller Load_R Processor R PC Load_R R IR Instruction Decode Load_R2 R2 S_dec 3 NOP Sel_PC Sel_Bus_ Load_Add_R 5 Execute S_rd / Sel_Mem Load_Add_R Inc_PC S_rd2 6 dest = R Sel_Mem Load_R Load_R3 Load_PC Inc_PC instruction Sel_Bus Mux Load_IR Load_Add_Reg Load_Reg_Y R3 Reg_Y Mux_ Bus_... dest = R Sel_Mem Load_R opcode ALU Memory Load_Reg_Z alu_zero_flag Reg_Z mem_word ad dr es s RD dest = R2 Sel_Mem Load_R2 Sel_Mem Load_R3 zero Sel_Bus_2_Mux write Zflag Bus_2 2 Mux_2 Add_R

21 Controller ASM: WR S_idle rst Instruction Fetch S_fet / Sel_PC Sel_Bus_, Load_Add_R S_fet2 / Sel_Mem, Load_IR, Inc_PC 2 Controller RISC_SPM Processor Load_R R PC Instruction Decode Load_R Load_R2 R R2 IR S_dec 3 NOP Sel_PC Sel_Bus_ Load_Add_R 7 Execute S_wr / Sel_Mem Load_Add_R Inc_PC S_wr2 8 src = R Sel_R write Load_R3 Load_PC Inc_PC instruction Sel_Bus Mux Load_IR Load_Add_Reg Load_Reg_Y R3 Reg_Y Mux_ Bus_... src= R Sel_R write opcode ALU Memory alu_zero_flag Load_Reg_Z Reg_Z mem_word ad dr es s WR src = R2 Sel_R2 write Sel_R3 write zero Sel_Bus_2_Mux write Zflag Bus_2 2 Mux_2 Add_R

22 Controller ASM: BR/BRZ S_idle rst Instruction Fetch S_fet / Sel_PC Sel_Bus_, Load_Add_R S_fet2 / Sel_Mem, Load_IR, Inc_PC 2 RISC_SPM Controller Processor Instruction Decode Load_R Load_R R R PC IR S_dec Load_R2 R2 3 Execute Load_R3 Load_PC R3 NOP Sel_PC Sel_Bus_ Load_Add_R 9 S_br / Sel_Mem Load_Add_R S_br2 Sel_Mem Load_PC Inc_PC instruction Sel_Bus Mux Load_IR Load_Add_Reg Mux_ Bus_ Load_Reg_Y Reg_Y... opcode ALU Memory BR zero Inc_PC Load_Reg_Z alu_zero_flag Reg_Z mem_word ad dr es s zero Sel_Bus_2_Mux Zflag 2 Mux_2 Add_R BRZ Bus_2 S_halt write 5-22

23 RISC Stored Program Machine (SPM) RISC_SPM Controller Processor Load_R Load_R Load_R2 Load_R3 Load_PC R R R2 R3 PC IR Inc_PC instruction Sel_Bus Mux Load_IR Load_Add_Reg Mux_ Bus_ Load_Reg_Y Reg_Y opcode ALU Memory alu_zero_flag Load_Reg_Z Reg_Z mem_word ad dr es s zero Zflag Sel_Bus_2_Mux 2 Mux_2 Add_R Bus_2 write 5-23

24 RISC-SPM [] module RISC_SPM (clk, rst); parameter word_size = 8; parameter Sel_size = 3; parameter Sel2_size = 2; wire [Sel_size-: ] Sel_Bus Mux; wire [Sel2_size-: ] Sel_Bus_2_Mux; input clk, rst; // Data Nets wire zero; wire [word_size-: ] instruction, address, Bus_, mem_word; // Control Nets wire Load_R, Load_R, Load_R2, Load_R3, Load_PC, Inc_PC, Load_IR; wire Load_Add_R, Load_Reg_Y, Load_Reg_Z; wire write; 5-24

25 RISC-SPM [2] Processing_Unit M_Processor (instruction, zero, address, Bus_, mem_word, Load_R, Load_R, Load_R2, Load_R3, Load_PC, Inc_PC, Sel_Bus Mux, Load_IR, Load_Add_R, Load_Reg_Y, Load_Reg_Z, Sel_Bus_2_Mux, clk, rst); Control_Unit M_Controller (Load_R, Load_R, Load_R2, Load_R3, Load_PC, Inc_PC, Sel_Bus Mux, Sel_Bus_2_Mux, Load_IR, Load_Add_R, Load_Reg_Y, Load_Reg_Z, write, instruction, zero, clk, rst); Memory_Unit M2_MEM (.data_out(mem_word),.data_in(bus_),.address(address),.clk(clk),.write(write) ); endmodule /* For parameters that occur in multiple modules, include them in a separate file (e.g., definitions.v) and then use `include definitions.v */ 5-25

26 5-26

27 Processing unit of the RISC SPM RISC_SPM Controller Processor Load_R Load_R Load_R2 Load_R3 Load_PC R R R2 R3 PC IR Inc_PC instruction Sel_Bus Mux Load_IR Mux_ Bus_ Load_Add_Reg Load_Reg_Y opcode Reg_Y ALU Memory 7 signals except rst and clk alu_zero_flag Load_Reg_Z Reg_Z mem_word ad dr es s zero Zflag Sel_Bus_2_Mux 2 Mux_2 Add_R Bus_2 write 5-27

28 Processing Unit [] module Processing_Unit (instruction, Zflag, address, Bus_, mem_word, Load_R, Load_R, Load_R2, Load_R3, Load_PC, Inc_PC, Sel_Bus Mux, Load_IR, Load_Add_R, Load_Reg_Y, Load_Reg_Z, Sel_Bus_2_Mux, clk, rst); parameter word_size = 8; parameter op_size = 4; parameter Sel_size = 3; parameter Sel2_size = 2; output [word_size-: ] output input [word_size-: ] input input [Sel_size-: ] input [Sel2_size-: ] input input instruction, address, Bus_; Zflag; mem_word; Load_R, Load_R, Load_R2, Load_R3, Load_PC, Inc_PC; Sel_Bus Mux; Sel_Bus_2_Mux; Load_IR, Load_Add_R, Load_Reg_Y, Load_Reg_Z; clk, rst; 5-28

29 Processing Unit [2] wire Load_R, Load_R, Load_R2, Load_R3; wire [word_size-: ] Bus_2; wire [word_size-: ] R_out, R_out, R2_out, R3_out; wire [word_size-: ] PC_count, Y_value, alu_out; wire alu_zero_flag; wire [op_size- : ] opcode = instruction [word_size-: word_size-op_size]; Register_Unit R (R_out, Bus_2, Load_R, clk, rst); Register_Unit R (R_out, Bus_2, Load_R, clk, rst); Register_Unit R2 (R2_out, Bus_2, Load_R2, clk, rst); Register_Unit R3 (R3_out, Bus_2, Load_R3, clk, rst); Register_Unit Reg_Y (Y_value, Bus_2, Load_Reg_Y, clk, rst); 5-29

30 Processing Unit [3] D_flop Reg_Z (Zflag, alu_zero_flag, Load_Reg_Z, clk, rst); Address_Register Add_R (address, Bus_2, Load_Add_R, clk, rst); Instruction_Register IR (instruction, Bus_2, Load_IR, clk, rst); Program_Counter PC (PC_count, Bus_2, Load_PC, Inc_PC, clk, rst); Multiplexer_5ch Mux_ (Bus_, R_out, R_out, R2_out, R3_out, PC_count, Sel_Bus Mux); Multiplexer_3ch Mux_2 (Bus_2, alu_out, Bus_, mem_word, Sel_Bus_2_Mux); Alu_RISC ALU (alu_zero_flag, alu_out, Y_value, Bus_, opcode); endmodule 5-3

31 Register unit, D_flop, and address register Chapter 5: Design Examples 5-3

32 Register unit, D_flop, and address register Chapter 5: Design Examples 5-32

33 Instruction register 5-33

34 Program Counter module Program_Counter (count, data_in, Load_PC, Inc_PC, clk, rst); parameter word_size = 8; output [word_size-: ] count; input [word_size-: ] data_in; input Load_PC, Inc_PC; input clk, rst; reg count; (posedge clk or negedge rst) if (rst == ) count <= ; else if (Load_PC) count <= data_in; else if (Inc_PC) count <= count +; endmodule 5-34

35 5-Input Multiplexor module Multiplexer_5ch (mux_out, data_a, data_b, data_c, data_d, data_e, sel); parameter word_size = 8; output [word_size-: ] mux_out; input [word_size-: ] data_a, data_b, data_c, data_d, data_e; input [2: ] sel; assign mux_out = endmodule (sel == )? data_a: (sel == )? data_b : (sel == 2)? data_c: (sel == 3)? data_d : (sel == 4)? data_e : 'bx; /* Implementation for Multiplexer_3ch is similar */ What would happen if we left out 'bx? 5-35

36 ALU Chapter 5: Design Examples module Alu_RISC (alu_zero_flag, alu_out, data_, data_2, sel); parameter word_size = 8, op_size = 4; // Opcodes parameter NOP = 4'b, ADD = 4'b, SUB = 4'b, AND = 4'b, NOT = 4'b, RD = 4'b, WR = 4'b, BR = 4'b, BRZ = 4'b; output alu_zero_flag; output [word_size-: ] alu_out; input [word_size-: ] data_, data_2; input [op_size-: ] sel; reg alu_out; assign alu_zero_flag = ~ alu_out; (sel or data_ or data_2) case (sel) NOP: alu_out = ; ADD: alu_out = data_ + data_2; SUB: alu_out = data_2 - data_; AND: alu_out = data_ & data_2; NOT: alu_out = ~ data_2; default: alu_out = ; endcase endmodule 5-36

37 Control unit of the RISC SPM RISC_SPM Controller Processor Load_R Load_R Load_R2 Load_R3 Load_PC R R R2 R3 PC IR Inc_PC instruction Sel_Bus Mux Load_IR Load_Add_Reg Mux_ Bus_ Load_Reg_Y Reg_Y opcode ALU Memory alu_zero_flag Load_Reg_Z Reg_Z mem_word ad dr es s zero Zflag Sel_Bus_2_Mux 2 Mux_2 Add_R Bus_2 write 5-37

38 Control Unit [] module Control_Unit (Load_R, Load_R, Load_R2, Load_R3, Load_PC, Inc_PC, Sel_Bus Mux, Sel_Bus_2_Mux, Load_IR, Load_Add_R, Load_Reg_Y, Load_Reg_Z, write, instruction, zero, clk, rst); parameter word_size = 8, op_size = 4, state_size = 4; parameter src_size = 2, dest_size = 2, Sel_size = 3, Sel2_size = 2; // State Codes parameter S_idle =, S_fet =, S_fet2 = 2, S_dec = 3; parameter S_ex = 4, S_rd = 5, S_rd2 = 6; parameter S_wr = 7, S_wr2 = 8, S_br = 9, S_br2 =, S_halt = ; // Opcodes parameter NOP =, ADD =, SUB = 2, AND = 3, NOT = 4; parameter RD = 5, WR = 6, BR = 7, BRZ = 8; // Source and Destination Register Codes parameter R =, R =, R2 = 2, R3 = 3; // See textbook for output, input, and reg declarations 5-38

39 Control Unit [2] 5-39

40 Control Unit [3] // Mux selectors assign Sel_Bus Mux[Sel_size-: ] = Sel_R? : Sel_R? : Sel_R2? 2: Sel_R3? 3: Sel_PC? 4: 3'bx; assign Sel_Bus_2_Mux[Sel2_size-: ] = Sel_ALU? : Sel_Bus_? : Sel_Mem? 2: 2'bx; (posedge clk or negedge rst) begin: State_transitions if (rst == ) state <= S_idle; else state <= next_state; end (state or opcode or src or dest or zero) begin: Output_and_next_state // set default values for control signals Sel_R = ; Sel_R = ; Sel_R2 = ; Sel_R3 = ; Sel_PC = ; Load_R = ; Load_R = ; Load_R2 = ; Load_R3 = ; Load_PC = ; Load_IR = ; Load_Add_R = ; Load_Reg_Y = ; Load_Reg_Z = ; Inc_PC = ; Sel_Bus_ = ; Sel_ALU = ; Sel_Mem = ; write = ; err_flag = ; // Used for de-bug in simulation next_state = state; 5-4

41 Control Unit [4] case (state) S_idle: next_state = S_fet; S_fet: begin next_state = S_fet2; Sel_PC = ; Sel_Bus_ = ; Load_Add_R = ; end // S_fet S_fet2: begin next_state = S_dec; Sel_Mem = ; Load_IR = ; Inc_PC = ; end // S_fet2 S_dec: case (opcode) NOP: next_state = S_fet; ADD, SUB, AND: begin next_state = S_ex; Sel_Bus_ = ; Load_Reg_Y = ; case (src) R: Sel_R = ; R: Sel_R = ; R2: Sel_R2 = ; R3: Sel_R3 = ; default : err_flag = ; endcase end // ADD, SUB, AND 5-4

42 Control Unit [5] NOT: begin next_state = S_fet; Load_Reg_Z = ; Sel_Bus_ = ; Sel_ALU = ; case (src) R: Sel_R = ; R: Sel_R = ; R2: Sel_R2 = ; R3: Sel_R3 = ; default : err_flag = ; endcase case (dest) R: Load_R = ; R: Load_R = ; R2: Load_R2 = ; R3: Load_R3 = ; default: err_flag = ; endcase end // NOT 5-42

43 Control Unit [6] RD: begin next_state = S_rd; Sel_PC = ; Sel_Bus_ = ; Load_Add_R = ; end // RD WR: begin next_state = S_wr; Sel_PC = ; Sel_Bus_ = ; Load_Add_R = ; end // WR BR: begin next_state = S_br; Sel_PC = ; Sel_Bus_ = ; Load_Add_R = ; end // BR BRZ: if (zero == ) begin next_state = S_br; Sel_PC = ; Sel_Bus_ = ; Load_Add_R = ; end else begin next_state = S_fet; Inc PC = ; end // BRZ default : next_state = S_halt; endcase // (opcode) S_ex: begin next_state = S_fet; Load_Reg_Z = Sel_ALU = ; case (dest) R: begin Sel_R = ; Load_R = ; end R: begin Sel_R = ; Load_R = ; end R2: begin Sel_R2 = ; Load_R2 = ; end R3: begin Sel_R3 = ; Load_R3 = ; end default : err_flag = ; endcase end // S_ex 5-43

44 Control Unit [7] S_rd: begin next_state = S_rd2; Sel_Mem = ; Load_Add_R = ; Inc_PC = ; end // S_rd S_wr: begin next_state = S_wr2; Sel_Mem = ; Load_Add_R = ; Inc_PC = ; end // S_wr S_rd2: begin next_state = S_fet; Sel_Mem = ; case (dest) R: Load_R = ; R: Load_R = ; R2: Load_R2 = ; R3: Load_R3 = ; default : err_flag = ; endcase end // S_rd2 S_wr2: begin next_state = S_fet; write = ; case (src) R: Sel_R = ; R: Sel_R = ; R2: Sel_R2 = ; R3: Sel_R3 = ; default : err_flag = ; endcase end // S_wr2 S_br: begin next_state = S_br2; Sel_Mem = ; Load_Add_R = ; end S_br2: begin next_state = S_fet; Sel_Mem = ; Load_PC = ; end S_halt: next_state = S_halt; default: next_state = S_idle; endcase end //state case and always block endmodule 5-44

45 Memory Unit module Memory_Unit (data_out, data_in, address, clk, write); parameter word_size = 8; parameter memory_size = 256; output [word_size-: ] data_out; input [word_size-: ] data_in; input [word_size-: ] address; input clk, write; reg [word_size-: ] memory [memory_size-: ]; assign data_out = memory[address]; (posedge clk) if (write) memory[address] = data_in; endmodule /* How would a more realistic memory differ? */ 5-45

46 Questions on RISC SPM Why not include memory as part of the processing unit? How could the design be simplified? 5-46

47 Testing RISC SPM Clear the memory Load the memory with a simple program and data Execute simple program Reads values from memory into registers Perform subtraction to decrement a loop counter Add register contents while executing the loop Branch to a halt when the loop index is Probe memory locations and control signals to ensure correct execution 5-47

48 Testing RISC SPM Verilog [] module test_risc_spm (); reg rst; wire clk; parameter word_size = 8; reg [8: ] k; Clock_Unit M (clk); RISC_SPM M2 (clk, rst); // define probes wire [word_size-: ] word, word,, word4; // instructions wire [word_size-: ] word28, word29,, word4; // data assign word = M2.M2_SRAM.memory[]; // words to 3 assign word4 = M2.M2_SRAM.memory[4]; assign word28 = M2.M2_SRAM.memory[28]; // words 29 to 39 assign word4 = M2.M2_SRAM.memory[4]; 5-48

49 Testing RISC SPM Verilog [2] initial #28 $finish; initial begin: Flush_Memory // set end point for simulation #2 rst = ; for (k=; k<=255; k=k+) M2.M2_SRAM.memory[k] = ; # rst = ; end // Flush_Memory initial begin: Load_program #5 // opcode_src_dest M2.M2_SRAM.memory[] = 8'b ; M2.M2_SRAM.memory[] = 8'b ; // NOP // Read Mem[3] to R2 M2.M2_SRAM.memory[2] = 3; // R2 = 2 M2.M2_SRAM.memory[3] = 8'b ; // Read Mem[3] to R3 M2.M2_SRAM.memory[4] = 3; // R3 = M2.M2_SRAM.memory[5] = 8'b ; // Read Mem[28] to R M2.M2_SRAM.memory[6] = 28; // R = 6 M2.M2_SRAM.memory[7] = 8'b ; // Read Mem[29] to R M2.M2_SRAM.memory[8] = 29; // R = 5-49

50 Testing RISC SPM Verilog [3] M2.M2_SRAM.memory[9] = 8'b ; // Sub R-R to R M2.M2_SRAM.memory[] = 8'b ; // BRZ M2.M2_SRAM.memory[] = 34; // Holds address for BRZ (39) M2.M2_SRAM.memory[2] = 8'b ; // Add R2+R3 to R3 M2.M2_SRAM.memory[3] = 8'b ; // BR M2.M2_SRAM.memory[4] = 4; // Holds address for BR (9) // Load data M2.M2_SRAM.memory[28] = 6; M2.M2_SRAM.memory[29] = ; M2.M2_SRAM.memory[3] = 2; M2.M2_SRAM.memory[3] = ; M2.M2_SRAM.memory[34] = 39; M2.M2_SRAM.memory[35] = ; M2.M2_SRAM.memory[39] = 8'b ; // HALT M2.M2_SRAM.memory[4] = 9; // Repeat Loop end endmodule 5-5