ECE 375 Computer Organization and Assembly Language Programming Winter 2018 Solution Set #2

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1 ECE 375 Computer Organization and Assembly Language Programming Winter 2018 Set #2 1- Consider the internal structure of the pseudo-cpu discussed in class augmented with a single-port register file (i.e., only one register value can be read in a cycle) containing 32 8-bit registers (R0-R31) and a carry bit (Cbit), which is set/reset after each arithmetic operation. Suppose the pseudo-cpu can be used to implement the AVR instruction ADIW ZH:ZL,32 (Add immediate to word). ADIW is a 16-bit instruction, where the upper byte represents the opcode and the lower byte represents an immediate value, i.e., 32 (do not worry about the fact that the actual format is slightly different). Give the sequence of microoperations required to Fetch and Execute the ADIW instruction. Your solutions should result in exactly 5 cycles for the fetch cycle and 6 cycles for the execute cycle. Assume the memory is organized into addressable bytes (i.e., each memory word is a byte), MDR, IR, and AC registers are 8-bit wide, and PC and MAR registers are 16-bit wide. Also, assume Internal Data Bus is 16-bit wide and thus can handle 8-bit or 16-bit (as well as portion of 8-bit or 16- bit) transfers in one microoperation and only PC and AC have the capability to increment itself. AC$ ALU$ C Internal Data Bus Register$File$ R31$ $R0$ IR$ +1$ PC$ MDR$ MAR$ CU$ External Control signals Internal control signals To/from memory and I/O devices Since ADIW ZH:ZL,32 is a 16-bit instruction and memory is organized into consecutive bytes, the instruction occupies two consecutive bytes. Thus, two memory accesses are needed to fetch the opcode into the IR and the immediate value into MDR. Fetch cycle Step 1: MAR PC; Step 2: MDR M(MAR), PC PC+1 ; Get the high byte of the instruction and increment PC Step 3: IR MDR ; At this point, CU knows this is ADIW Step 4: MAR PC; Step 5: MDR M(MAR), PC PC+1 ; Get the low byte of the instruction and increment PC Execute cycle Step 6: AC R30 Step 7: AC AC + MDR ; Add 32 to ZL

2 Step 8: R30 AC Step 9: AC R31 Step 10: If (C==1) then AC AC +1 Step 11: R31 AC ; Write back to register file ; Increment ZH if there was a carry ; Write it back to register file 2- Consider the internal structure of the pseudo-cpu discussed in class augmented with a single-port register file (i.e., only one register value can be read at a time) containing 32 8-bit registers (R31-R0) and a Stack Pointer (SP). Suppose the pseudo-cpu can be used to implement the AVR instruction ICALL (Indirect Call to Subroutine) with the format shown below: ICALL pushes the return address onto the stack and jumps to the 16-bit target address contained in the Z register. Give the sequence of microoperations required to Fetch and Execute AVR s ICALL instruction. Your solutions should result in exactly 6 cycles for the fetch cycle and 8 cycles for the execute cycle. Assume the memory is organized into addressable bytes (i.e., each memory word is a byte), MDR is 8 bits, and AC, SP, PC, IR, and MAR are 16 bits. Also, assume Internal Data Bus is 16-bit wide and thus can handle 8-bit or 16-bit (as well as portion of 8-bit or 16-bit) transfers in one microoperation and SP has the capability to increment/decrement itself. Clearly state any other assumptions made. ALU$ AC$ SP$ Register$File$ R31$ $R0$ Internal Data Bus IR$ +1$ PC$ MDR$ MAR$ CU$ External Control signals Internal control signals To/from memory and I/O devices SP SP (initially) After ICALL Return Address(H) Return Address(L) Low High

3 ; Fetch cycle Step 1: MAR PC; Step 2: MDR M(MAR), PC PC + 1 ; Get the high byte of the instruction and increment PC Step 3: IR(158) MDR Step 4: MAR PC; Step 5: MDR M(MAR), PC PC + 1 ; Get the low byte of the instruction and increment PC Step 6: IR(70) MDR ; At this point, CU knows this is an ICALL ; Execute cycle ; The return address is pushed onto the stack Step 7: MDR PC(70) Step 8: MAR SP Step 9: M(MAR) MDR, SP SP - 1 ; Push the lower byte of return address onto stack Step 10: MDR PC(158) Step 11: MAR SP Step 12: M(MAR) MDR, SP SP - 1 ; Push the higher byte of return address onto stack : Put H and L target addresses of the Z register to the PC Step 13: PC(158) R31 ; Put the H address of the target into PC Step 14: PC(70) R30 ; Put the L address of the target into PC Goto fetch and Execute cycle. 3- Suppose the following array of numbers are stored in the Data Memory (represented in hexadecimal): Address Content 0100: : BE 0102: : EC 0104: : 2D 0106: : 02 (a) Assuming these numbers are signed numbers, write a subroutine using AVR assembly that (1) determines the smallest number among the 8 numbers stored in memory and (2) stores that number in the memory location $0108. Clearly comment and explain your code. Use the skeleton code shown below to implement your subroutine: Initialize stack RCALL MIN ; Your code goes here ; RET.DSEG.ORG 0x0100 DATA:.BYTE 8 RESULT:.BYTE 1

4 (b) Suppose these numbers are unsigned numbers (i.e., they are positive numbers). Show and explain how the code developed in part (a) would have to be modified. : One possible code is shown below: LDI XH, low(data) ; Initialize the X register to point to LDI XL, high(data) ; the beginning of the array LD R18, X+ ; Load the first array value and post-increment X LDI R19, 7 ; initialize count (8-1) LOOP: LD R17, X+ ; Load the array value and post-increment X CP R17, R18 ; Compare loaded value with previous smallest value BRGE SKIP ; If greater than or equal to, then skip. MOV R18, R17 ; Else, move loaded value to temporary register SKIP: DEC R19 ; Decrement count BRNE LOOP ; Check if count has reached zero, if not jump to loop DONE: ST X, R18 ; When done, store the smallest value in location $0008 RET ; Return from subroutine Another interesting aspect of this code is that the numbers in the memory can be unsigned or signed. The BRGE instruction performs a signed comparison and treats the numbers with their MSB set as negative (2 scomplement) numbers. So this program would work if we meant to operate on signed numbers. If we meant to work with unsigned numbers, we would have to use BRMI (Branch if minus) instead of BRGE. 4- Determine the location (i.e., address) and binary code for each instruction in the code developed for Problem #3 part (a). Clearly explain your answers. Examples of addresses and machines codes for RCALL and RET are shown below. Address Binary RCALL MIN 0046: RET????: Address Binary RCALL MIN 0046: LDI XH, high(data) 0060: LDI XL, low(data) 0061: LD R18, X+ 0062: LDI R19, : LOOP: LD R17, X+ 0064: CP R17, R : BRGE SKIP 0066: MOV R18, R : SKIP: DEC R : BRNE LOOP 0069: DONE: ST X, R18 006A: RET 006B:

5 The displacement for RCALL is determined by subtracting the address of the instruction right after RCALL (i.e., return address) from the target address MIN, i.e., $0060 $0047 = $0019. Therefore, kkkk kkkk kkkk = The next two LDI instructions have the destination register and the immediate fields indicated in red and green, respectively. For example, LDI XH,low(DATA) has rrrr = 1011 (note that there is a hidden 1 ) and KKKK KKKK = The LD instruction has the 5-bit destination field indicated in red. The CP instruction has the destination and the source fields indicated in red and blue, respectively. The LDI instruction has the destination register and the immediate fields indicated in red and green, respectively. The displacement for BRGE SKIP is determined by subtracting the address of the instruction right after RCALL (i.e., return address) from the target address SKIP, i.e., $0068 $0067 = $0001. Therefore, kk kkkk k = The MOV instruction has the destination and the source fields indicated in red and blue, respectively. The DEC instruction has the destination/source field indicated in red. The displacement for BRNE LOOP is determined by subtracting the address of the instruction right after BRNE from the target address LOOP, i.e., $0064 $006A = -$0006 = 0b Therefore, kk kkkk k = The ST instruction has the 5-bit source field indicated in red. RET has no destination or source fields and pops the return address from the stack and jumps to it.

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