CPU MINI PROJECT. Gen Kazama David Kawrykow COMP 273 Professor Vybihal CPU Mini Project

Transcription

1 CPU MINI PROJECT Gen Kazama David Kawrykow COMP 273 Professor Vybihal CPU Mini Project

2 Table of Contents Overview of CPU Section CPU Diagram Section Page CPU Overview Diagram Section Page CPU Overview Diagram Section Overview of Functionality and Flow Section Detailed CPU Breakdown By Phase Section Instruction Circuit Diagrams Section Fetch Section Fetch Overview Section Fetch Hardware Description Section Fetch Hardware Circuit Diagrams Section Load Section Load Overview Section Load Hardware Description Section Load Hardware Circuit Diagrams Section A-Out Update Phase 1 Section A-Out Update Phase 1 Overview Section A-Out Update Phase 1 Hardware Description Section A-Out Update Phase 1 Circuit Diagrams Section Write Section Write Overview Section Write Hardware Description Section Write Hardware Circuit Diagrams Section STOP/HALT/ON Overview Section Assembly Language Section Assembly Instructions Section OP-CODE Binary Table Section Description of Execution Section ADD, MULT and SUB Section COMP Section STORE Section LOAD Section BIZ Section STOP/HALT Section Sample Program Section Appendix Section Appendix A Original HALT/STOP Section Appendix B Original ALU Section 4.2.0

3 1.2.0 Overview of Functionality and Flow Our pipeline CPU has four stages: FETCH, LOAD, A-OUT UPDATE PHASE 1 (ALU Execution Phase) and WRITE. The PC counter's address selects an instruction from RAM and sends it to the Instruction Register in the Fetch stage. The instruction register then sends the entire instruction to the Control Unit (CU), which uses it to determine its eleven control outputs. These outputs are released in three waves: some immediately in the Load phase, most in the A-Out Update Phase 1 Phase, and a few more in the final Write Phase. Our outputs are all 1-Bit True or False selection outputs and essentially all decide between two dichotomous branch states. We usually allow most forms of processing of binary information to occur and then choose the appropriate version of the data using the Control Unit's outputs. For instance, we allow bits 2,3 to read from the Register Memory Bank and to remain in raw address form. The appropriate form of these bits is then selected during the Load Phase and sent on. However, this form of selection is not always used: in certain cases we chose instead to simply block information from passing further through the use of keyed AND gates. This occurs for instance in the A-Out Update Phase 1 when deciding whether or not the Stb Register should be written to or not; it also occurs in the ALU. These AND gates are again directly controlled and keyed by single-bit output from the CU. To allow delayed outputs from the Control Unit, information is repeatedly stored in AND gated registers and then released at the next clock tick. Between any two phases there are usually two or three registers holding all remaining information and it is these which best show the differences between instructions within phases. For this reason we have included tables showing this in each phase. We have also tried to maximize the length of each phase to ensure that the Register Memory Bank is always written to in the Write stage. k The Four R-type instructions all avoid the Data Memory and travel directly to the A-Out register. BIZ also avoids the data memory and is the only instruction to make use of the izbiz Register and the iz circuit inside the ALU. Both the Load and Store instructions make it all the way to memory, but Load only reads from it. Finally, HALT and STOP do not use any of the conventional circuitry and simply kill the computer/program before the A-OUT Update Phase 1 even begins. This is achieved using two Continuous Stream Registers and is, in our opinion, the crowning achievement of this CPU. A few of the main features of this CPU are 1. The use of keyed AND gates to ensure total blockade of information. This is used especially near the Register Memory Bank and the Data Memory, and also near the Program Counter. The Control Unit usually controls two dichotomous information states using a single binary bit and two AND gates. Opposite values of the bit allow the other information to pass through the AND gate. This feature is not always present however; we retain the regular AND gates in all circuits possessing arithmetic-logical type functionality (ALU, CU) and, as an exception, in the MOXP circuit near the PC. Any other exceptions are noted in the hardware descriptions. 2. Concurrent reading and writing to memory, as well as dual reading in RAM. 3. Continuous Stream Registers which, given a certain state, prevent themselves from being updated again. 4. Direct external access to the PC via a simple push button. 5. Direct memory access without addressing in the case of the ALU-Reg to A-Out connection

4 2.1.0 FETCH FETCH OVERVIEW Brief descriptive outline This is the simplest stage of the pipeline. The PC counter sends out one four bit address to obtain the 8-Bit instruction from memory corresponding to that address, and the instruction is appropriately stored in the IR register. The same address is also used to update the PC counter by two nibbles using an adder. Only the MOX selector receives the appropriate input is this address sent through to re-set the PC register; otherwise whatever address is in the BZO wire now occupies the PC register. Step by Step 1. The PC 4-Bit register releases it's address into wire Wire 1. branches; its first branch provides a 4-Bit address to RAM in slot A and receives no alterations 3. the second branch (address) is incremented by one by passing through the UAA 4. and provides a second distinct address to be read from RAM. 5. Each 4-Bit memory instruction then flows into a distinct half (either 0-3 or 4-7) of the IR register at the next clock tick. 6. Simultaneous to Step 1, the PC 4-Bit register releases the same address into wire This address is incremented by two via the UAA(2) 8. The MOX selector determines whether this modified address or the one in the BZO wire continues on to step 9. (further details follow in the detailed follow-up) 9. The selected address modifies the PC register at the next clock tick. Implementation Details 1. The Uniform Adder (UAA) guarantees that the two addresses sent into RAM are always different. 2. Our CPU circuitry allows for simultaneous accessing of RAM. Both addresses are processed independently using two wholly independent Address Selection Devices (ASD). Each ASD has sixteen outputs, one output for each nibble in memory. When an address is processed by an ASD, the address is translated into a single '1' traveling down the appropriate wire, with remaining wires receiving '0'. This '1' then unlocks four keyed AND gates. These four AND gates lock in the information from that address in memory and so a '0' prevents -all- information from flowing out of the registers. (the registers themselves do not prevent data from escaping). Every register has two sets of four AND gates protecting two sets of four wires, both sets distinct. Since everything is wholly segregated, simultaneous reading of information easily follows. 3. The next phase in the cycle begins when the clock tick allow the information read from memory to flow into the appropriate IR registers. 4. The AND gate appearing outside MOX but in the MOXP diagram is not keyed by either of the two inputs. This ensures that MOX actually receives input.

5 2.1.2 FETCH HARDWARE DESCRIPTION Registers: This CPU uses the same bits as those presented in class. When we say information flows into some register, we mean that the information in each wire flows into the corresponding bit in the register at the next clock tick. When we say flow into at the next clock tick we actually mean that the clock-keyed AND gates before the actual flip-flop prevent the electricity from traveling further until the clock sends out another 1. Finally, we note that information stored in a register does not imply that the information is held in the register : no gates prevent the information from traveling beyond the register itself. We wish to emphasize that the continuous release of information from the register only and the blockade of information by the AND gates BEFORE the register allows simultaneous reading and writing from memory (like in the Register Memory Bank) without strangeness. Information can always be read and at every clock tick there is a chance that new information rushes into the registers. This then allows simultaneous reading and writing to memory without fear of superimposed information present within the same clock cycle (or at any time). This is again emphasized strongly in the description of the memory itself. The WAM register is a special exception to the above format. It does not serve as a barrier between pre- and post- AND gates because there are none. The register can be updated at any time and by a single signal. It also emits a continuous stream of whatever it currently holds. It is used in the implementation of the STOP instruction and in the HALT instruction. We note that this way the register can receive a single instantaneous 1 input and transmit that 1 to other circuits indefinitely (or until updated.) AND Gate Overview: Quite often this CPU makes use of keyed AND gates to allow perfectly dichotomous settings to occupy the same wiring (see for instance the fusion of Addition and Multiplication in the ALU or the simultaneous access of memory in RAM/Data Memory.) For any keyed AND gate it is always the Left-most input wire which acts as the key. Here Left-most is a relative term and requires the 'AND' text string to be upright to be correct. Certain circuitry however, does not make use of the KEYED PROPERTY Clock : Though the circuitry does not usually show it, the CLOCK is connected to every normal register The clock's regular output is ANDed with the continuous output from the WAM register. The AND gate is keyed with the WAM register acting as the key. The clock's output is thus regular as long as WAM sends '1'; it stops sending any information whatsoever once WAM turns the gate off. Also located in the clock is the technology to turn off the computer. The On/Off Register sends a continuous stream of 1 to be ANDed with the power supply. When this register sends a single 0 then the power supply stops powering the clock via AND gate technology and no further operations can be performed. Note that we did not erase all the information in the CPU but this was not requested by the assignment.

6 RAM: This circuit houses the data for 16 addresses. It accesses two addresses at a time (hence the two 4 bit address inputs). Using the ASDs, it converts the 4 bit address inputs to send a 1 to the correct address in memory (ie, an input of 0000 accesses the 0 address). Since we do not need to worry about how data is written to RAM, this circuit is only able to read the data from RAM. The data from the bits are only outputted when the ASD selects the particular address. Since the two ASDs are always two different addresses, there is no fear that memory will be accessed at the same time. In addition, only the data from one address will be sent that each output since all gates except the one opened by the ASDs will be open. Address Selection Device (ASD): This circuit has a 4 bit input and releases 16 outputs, with a 1 in the output corresponding to the 4 bits and a 0 in all other bits. For example, if the 4 bit input is 0010, a 1 is outputted from output 2 ( =2 10 ). This device is used in both RAM and Memory in this CPU.

7 2.2.0 LOAD LOAD OVERVIEW Brief Descriptive Outline Load does relatively little compared to later stages. It chooses whether bits 2,3 should be interpreted as a raw binary address or whether they turn into the contents of the register which they [potentially] reference. The same is done for bits 4,5 but the technology used to do this varies slightly (for some reason.) The raw binary is sent to the Right and Left registers. A table indicating the nature of the contents of these registers at the end of the LOAD cycle is shown below. Step by Step 1. The assembled instruction is released from the IR : one wire per bit. 2. All eight bits flow into the CU for OP CODE processing. 3. Bits 2,3 act as Address 1 for the register bank 4. Bits 2,3 travel down wire A. 5. Bits 4,5 act as Address 2 for the register bank 6. Bits 4-7 travel down wire B. 7. The CU processes the OP CODE and stores most outputs in registers which will require another clock tick to release their information. Certain outputs are instantly released however: 1. SEO: a single bit output. It determines whether bits 2,3 should be sent on as a (sign extended) four bit address or as the 4-Bit -contents- of the register referenced by 2,3. SEO's output chooses between two dichotomous situations. 2. AddrO: a single bit output. It determines whether bits 4-7 should be sent on as an address or whether they should be replaced by the contents of the register addressed by bits 4,5. It uses MOX to achieve this. Why SEO does not use MOX has confounded IBM's, MIT's and McGill's most brilliant engineers for decades. 3. From ALUCU: The C M S Register is updated with the binary values specifying the desired ALU operation in the next phase for the current information. When the instruction does not require ALU support, these registers are still filled, albeit with nonsensical instructions. Further CU instructions simply choose the un-processed bits over the mutilated ALU bits. 8. Whatever the output determined by the CU, it is stored in two separate four bit registers called Left and Right Registers. We note that Right Register will always contain either the contents of the 2,3 register or a sign extended address determined by 2,3 ; Left Register will always contain either an address determined by 4-7 or the contents of the register referenced by 4,5. 9. The three inputs from a later stage (R/W, Memory addr. and Stb. Reg (0)) are technically not part of this phase but operate in the same location. These three inputs update the register memory but the updates only take effect for the NEXT clock cycle (ie. the next time register memory is read.) and do not affect the read memory in any way within this cycle.

8 Register content after CU manipulation. Refer also to the OP-CODE details Refer also to Table 2 Refer also to the CU schematic for the exact binary outputs Table 1: Contents of the Right and Left Registers by Instruction Instruction Content of Right Reg Content of Left Reg ADD, MULT, SUB Contents of Register Addressed by 2,3 Contents of Register Addressed by 4,5 BIZ Contents of Register Addressed by 2,3 Unaltered 4-Bit Address (4-7) STOP, HALT N/A N/A COMP Sign Extended Address (always 1111) Contents of Register Addressed by 4,5 LOAD Sign Extended Address of 2,3 Unaltered 4-Bit Address (4-7) STORE Contents of Register Addressed by 2,3 Unaltered 4-Bit Address (4-7) Implementation and Miscellaneous Note that the Sign Extend Box is used only to satisfy the 4-Bit storage requirements of the registers. Otherwise this device is pointless. The rest of the circuitry is easy to follow. For a full fledged discussion of CPU output, refer to the CU under Section LOAD OVERVIEW HARDWARE DESCRIPTION Register Memory Bank (RMB) The Register Memory Bank is composed of two Register Selection Devices and two Register Data Retrievers. Register Selection Device (RSD): This device is used to select the proper register from among the three in the CPU (R0, R1 and A-out). It takes the two input bits and releases a 1 from the proper output and 0 from all other outputs. For example, the input 00 will release a 1 from output 0 (R0 in this CPU) and a 0 from the other two outputs. Register Data Retriever (RDR): This circuit is for reading and writing to the proper register in the CPU. It first uses the Register Selection Device mentioned earlier to choose the proper address from among the three (R0, R1, A-Out). For R0 and R1, the bit from the R/W Register must be 1 to write, 0 to read. If the R/W

9 Register provides a 1, the 4-bit data from Memory is placed into the 4 appropriate registers at the specific address. When data is being written, there is not output from this circuit. If the R/W Register sends a 0, the 4 bits from the register are sent to the output. Because the R/W Register must be either a 1 or 0, it cannot read and write to the 4 registers simultaneously; the circuitry prevents writing if R/W is 0 by blocking access using an AND gate and the same for reading. Since every operation, except for STORE, makes R/W 0, there is no chance of writing and reading at the same time. For A-Out, the circuitry is a little different. The information from the 4 registers is continuously traveling toward the AND gates but is stopped because the input from the RSD is 0 and the clock is 0. If the input from the RSD is 1 for A-Out (and the clock is at 1), it opens the gates, allowing the data to be outputted. To write to the registers, data is sent directly from the ALU to A- Out. Because the 4 registers in A-Out are clocked, there is no fear of overwriting the bits while Sign Extend (SE): This is a very complex circuit which took many years to develop. It extends a one bit signal into a four bit output. ALU and C M S Register: The key to understanding the ALU is the C M S status register. The CU sends a binary value into each of the bits (C, M, S). C stands for "Two's Complement", M stands for "Multiplication" and S for "Subtraction." When a register receives a "1" as input, the next clock cycle sees the release of that "1" and the subsequent activation of the corresponding AND gates and performance of that operation. Note that these AND gates are keyed in the appropriate fashion with the register input acting as key. This way we allow certain dichotomous states (like Multiplication and Addition) to meld into the same wiring without complications. Note also that SUB and COMP each use their own 2C Black box. We also refer the reader to the FA, MULT, 2C and iz boxes for further details. All results are then sent to the A-Out register which is not actually in the ALU but is represented here for easy viewing. Finally, the iz box determines whether or not the Left-most input (in the overall scheme of things this is the input from Right Register) is zero and then sends this to the is-zero Status Register (which is, as always, blocked by simple AND gate technology until the next clock cycle.) We have provided the Overflow (written as Ov in all circuitry) register to handle overflow from Add and Multiplication, or rather, to simply store whether or not an overflow occurred. This information is not handled further. Full Adder (FA): FA performs addition on two 4-Bit inputs. This is achieved using several HA circuits. Note that addition is performed bit by bit. It also sends the final remainder obtained by addition of the two most significant bits directly to the Overflow register in the ALU. Half Adder (HA): This circuit was presented in class. It adds two bits and returns the sum as two outputs with one

10 acting as the remainder for subsequent additions in the FA circuit. Multilication Circuit (MULT) MULT takes in two 4-Bit unsigned integers and multiplies them. This is achieved using the ABM black box (see below) which takes the first input and multiplies it with each of the bits of the second input separately. These four values are then added together using FA's. The wiring provides the appropriate digit shifts for each addition. Since Multiplication, when performed, is guaranteed to have a "1" in the M register of the C M S register in the ALU, we use this "1" as a zero placeholder in the first addition. A further processing. These four values are sent out as four 4-Bit values. Individual multiplications are achieved using an LBM black box (see below.) is-zero (iz) Determines whether or not the input is zero. Note that an alternative iz circuit could have used one OR gate and one NOT gate. In our version the AND gate is not keyed by any of the inputs. All Bit Multiplier (ABM): The ABM takes in two 4-Bit values, L and R. R is multiplied separately by each bit in L with no shifts or further processing. These four values are sent out as four 4-Bit values. Individual multiplications are achieved using an LBM black box (see below.) Left Bit Multiplier (LBM) Simply ANDs together each bit in the 4-Bit input with the 1-Bit input. The AND gates used are not keyed by either input and so always output a value.

11 2.3.0 A-OUT UPDATE PHASE A-OUT UPDATE PHASE 1 OVERVIEW Brief Descriptive Outline The three broad instruction types meet different fates in the A-Out Update Phase 1 Phase of the CPU. R-Type instructions are simply processed by the ALU and then written into the ALU Reg just outside the Register Data Bank. The LOAD and STORE instructions both by pass the ALU entirely (and ignore all of its outputs), going instead to the Data Memory to write there or to read from it. Any read information is stored in the Mem. Register and any writing happens in this phase. The BIZ instruction's information is also not processed by the ALU but BIZ will require the ALU's iszero result in the next phase. This result is stored in a register and used later. The CU's role in this part is that of a grand selection device: since the ALU processes ALL results regardless of op code, and ALL results also by pass the ALU entirely (through branching), the CU simply has to choose which of these two versions is appropriate for the current instruction. Further refinement is achieved using the R/W bit which decides whether or not memory is to be read from or written to (LOAD vs. STORE) and the BZO bit which determines whether the Branching address should head towards the PC counter or towards memory. The final tweaks of the branching mechanism occur in the last phase of the CPU. Step by Step 1. The clock ticks and information floods out from Right Reg and Left Reg. 2. The CU releases three 1-Bit ouputs: BZO, R/W and AUP1S from the isb, internal R/W and Math registers (respectively). 3. The C M S register inside the ALU releases three 1-Bit outputs: C, M and S 4. Information from Right Reg and Left Reg flows into the ALU regardless of command. 5. It it processed according to the combination provided by C, M and S 6. The ALU obtains three results: One 1-Bit is Zero result, One 4-Bit outcome, and One 1-Bit overflow result. 7. The overflow result is simply stored in the Ov register inside the ALU. 8. The is Zero result is sent out to the 5-Bit izbiz Register (0,1) 9. The 4-Bit outcome is sent towards the A-Out register in the Register Memory Bank but is blocked by an AND gate which awaits another signal. 10. The AND gate depends on another signal: the AUP1S signal sent out by the CU 11. AUP1S sends out a 1 if the current operation is ADD, SUB, MULT or COMP and 0 otherwise. 12. The AND gate is keyed by the AUP1S signal and so if 0 is sent no information passes on to the Register Memory Bank. 13. If a 1 is sent then the ALU result is written into the 4-Bit ALU Reg where it waits until the next phase to write to memory. 14. The information from Right Reg and Left Reg also bypasses the ALU regardless of command by branching around the ALU. 15. Information from Right Reg is blocked by an AND gate keyed by a NOTed AUP1S signal. 16. If AUP1S is 1 then the bypassed ALU result does not pass. Otherwise it passes the AND gate. 17. Content from Right Reg then branches into two possible circuits regardless of command.

12 18. The first travels on to Memory where it serves as the content to be written if and only if the R/W output from the CU is 1. If R/W is 1, then the contents are written at the address provided by other circuitry. If R/W is 0 then the contents of Right Reg are simply blocked inside Memory and there pass into oblivion at the next clock tick. 19. The second branch heads towards Stb Reg but is again blocked by an AND gate which is also keyed by the R/W output. Here the opposite as in 18 holds, the contents only pass through if R/W is 0 and are blocked if R/W is 1. The results pass into oblivion unless they are stored in the Stb Reg (Stable) register. 20. The information from Left Reg flows out and meets the same fate as Right Reg in points Otherwise it also by passes the ALU and is then also blocked by an AND gate waiting on AUP1S. This matches 15, Once by passed, Left Reg then flows into the SEL box which selects down which wire Left Reg flows next. 23. This selection depends entirely on the 1-Bit BZO signal sent out by the CU. If BZO is 1 then SEL sends Left Reg towards and into the 5-Bit izbiz Register (0, 1) where it is stored in 4 of its 5 bits. 24. Otherwise it is sent on to Memory where it serves as an address (see point 18). 25. If R/W is 1 then it serves as the address to be written to, otherwise it is the address to be read from. 26. If information is written to memory then we are done. Otherwise the read contents are sent to the 4-Bit Mem. Reg inside memory. 27. Finally, the R/W signal is stored inside the R/W Register for the final phase. 28. The BZO 1-Bit signal is also stored in the BZO Register for the final phase. Table 2: Contents of the Mem. Reg, Stb Reg., R/W Reg, Ov Reg., izbiz Reg., BZO Reg and ALU Reg at the end of the A-Out Update Phase 1 Phase by Instruction Instruction Mem.Reg Stb Reg (0) ADD, MULT, SUB Nothing Nothing Result of ALU Op ALU Reg. izbiz Ov R/W BZO N/A BIZ Nothing Nothing Nothing Addr. [4-7], result of iz black box in ALU Result of Alu Op N/A 0 N/A N/A 1 STOP, HALT N/A N/A N/A N/A N/A N/A N/A COMP Nothing Nothing Result of ALU Op LOAD Contents in Data Memory at Addr. [4-7] Sign Extended Addr. [2-3] N/A N/A N/A 0 Nothing N/A N/A 1 0 STORE Nothing Nothing Nothing N/A N/A N/A 0

13 2.3.2 A-OUT UPDATE PHASE 1 HARDWARE DESCRIPTION The following appears in the Control Unit: sstop (iss): The OP-CODE for STOP is 0111 (the last four bits aren't used). Therefore, the circuit only returns a 1 when it is STOP. isstore (isst): The OP-CODE for STORE is 01 followed by 00,01, or 10. Therefore, the circuit only returns a 1 when STORE is passed through. ishalt (ish): This circuit only returns 1 when the first four bits are 1111, therefore, it only returns 1 for HALT. isbiz(isb): isload (isl): This circuit returns 1 only for the OP-CODE for BIZ, which is 11 followed by 00, 01 or 10. Returns true if the OP-CODE is LOAD using the first 4 bits. From the OP-CODE Table, the first two bits are 10 and the next two are either 00,01 or 10. Therefore, the circuit only returns a 1 when the OP-CODE is LOAD. isload or Comp (islc): Returns 1 if the OP-CODE is LOAD or COMP. Since COMP and LOAD both start with 10, the circuit checks for this. AddrO Stream Chooser (AOS): Because our OP-CODE sometimes relegates the last four bits as an address in memory, this circuitry outputs a 1 when this is true, and a 0 when the last four bits are something else. This is tested by checking if the first four bits are the OP-CODE for Load, Store and BranchIfZero by using the isload, isstore and isbiz circuits, respectively. The output is sent to AddrO (Address Output). A-Out Update Phase 1 Selector (AUP1S): The naming of this is circuit is an inside joke and is completely irrelevant for what it does. This circuit takes the first 4 bits of the OP-CODE and releases a if and only if the OP-CODE is for 2's complement or one of the mathematical operations (ADD, SUB and MULT). The output of this circuit determines whether the output from the ALU are sent directly to A-Out or if the contents from Stable Register 0 are sent to deal with the memory (in the case of LOAD, STORE and BIZ; STOP stops the program before it reaches this step so it is irrelevant).

14 BIZ Selector (SEL): This circuit takes a selector bit, which chooses which output the 4 bit input goes to. It basically routes the 4 bit input depending on the value of the selector bit. This circuit is used in our CPU for the BranchIfZero operation. If the OP-CODE is BIZ, the 4 bit input is sent to izbiz Register, if not, it is sent to the Memory. ALU CU (ALUCU): This circuit is for setting the 3 registers in the ALU, C (2's Complement), M (Multiplication) and S (Subtraction). Each of these registers needs to be selected when its respective OP-CODE is operating. The circuitry is such that if the OP-CODE is MULT, a 1 is placed into the M Register and a 0 otherwise, if it is COMP, a 1 is placed in C, a 0 otherwise, and if the OP-CODE is SUB, a 1 is placed in S and a 0 otherwise. Control Unit (CU): Table 3: Output of CU based on Instruction OP-CODE NAME AUP1S (A-Wire) AOS (AddrO) iss ish C M S SEO R/W Register B Register ADD SUB MULT COMP LOAD STORE BIZ STOP HALT As can be seen from the table, the CU provides a unique output for every OP-CODE, whether it be the setting of a register (such as the R/W register) or the output of a bit down a wire (such as AddrO). This ensures that each operation has its own unique output to control other parts of the CPU. As input, the CU takes in bits 0,1,2,3,6 and 7 from the IR. Bits 4 and 5 are not needed because they are either representations of addresses or registers (or not used at all) and are therefore irrelevant for the CU to differentiate between operations. Bits 6 and 7 are only used in the CU for the mathematical operations to set the ALU's C, M and S registers. To aid the CU in releasing information down the Right pathways, we used the AUP1S (to set the MATH Register to 1), AOS (to send a 1 down the AddrO wire when an address operation LOAD, STORE or BIZ is used), isl (to initialize the Internal R/W Register to 1 when the OP- CODE is LOAD), isb (to set the B Register to 1 when the OP-CODE is BIZ) and iss (to set the WAM Register to 0 when the OP-CODE is STOP) boxes.

15 For the mathematical operations, AUP1S sets the MATH Register to 1 and the ALUCU circuit sets the C, M and S registers in the ALU according to the OP-CODE (MULT sets M to 1, COMP sets C to 1 and SUB sets S to 1). The MATH Register is used because the timing is off without a register; when ALUCU sets C, M and S, 1 clock tick expires, which means that the output from AUP1S must use 1 clock tick as well. For the operations which require access to Memory (LOAD, STORE and BIZ), the AOS circuitry outputs a 1 down the AddrO wire for all three OP-CODEs. This makes sure that the bits stored in Stable Register 0 are parsed as addresses, not data. For the STORE OP-CODE, the isl circuitry places a 0 in the Internal R/W Register which after 1 clock beat, is sent down the R/W wire to facilitate memory reading and writing. In the case of LOAD, Internal R/W Register is set to 1 by isl and this 1 is sent down the R/W wire. For BIZ, the B Register is set to 1, which is sent along two wires, one down the Biz wire which goes to the BZO Register and the other goes to BZO wire to be the selector for the SEL circuitry. For STORE and COMP, the islc returns a 1, which is streamed to SEO (Sign Extend Output). For both, the SEO makes sure that bits 2 and 3 of the OP-CODE are sign extended and put into Right Register. STORE needs this because it needs to keep the address of the register it is going to store the data to and COMP because we do not want the 11 in bits 2 and 3 to be parsed as an addressed prior to computing in the ALU. The circuitry for setting the WAM Register is very unique. This register is used to control the clock and is therefore used to completely stop the computer. When the computer is turned on, the ON/OFF button sends a single 1 to initialize the WAM Register. It passes through one OR gate (the other input for the OR gate is not present yet since the computer has just turned on) and sends the 1 to the WAM Register. The WAM Register is a Continuous Stream register, so as soon as it is set 1, it releases this 1 to the Clock which allows it to start running (see the Clock circuitry). Once the Clock starts, the CPU can start running. From here on, all OP-CODE except for STOP sends a 1 into the WAM Register (iss outputs a 0 which is NOTed into a 1 and is ORed with the 0 from the ON/OFF Button). In the case that the OP-CODE is STOP, a 1 is sent from iss, which is NOTed into a 0, then ORed with the 0 from the button and initializes the WAM Register to 0. Since the WAM Register is not clocked, it sends this 0 immediately (before the next OP-CODE can be loaded into iss) into the Clock, freezing it and subsequently the whole CPU itself. The circuitry for setting the ON/OFF Register is almost exactly the same as the WAM Register. The ON/OFF Register is another Continuous Stream Register and is initialized to 1 by the ON/OFF Button. Therefore, this register sends a continuous flow of 1's once it has been initialized. This stream of 1's is sent to the Clock via the Haltwire and allows the Power Supply to release its power to the computer (see Clock circuitry). From here on, all OP-CODE except HALT sends a 1 into the ON/OFF Register, thus maintaining the value of the register. When HALT is the OP-CODE, it sends a 0 into the ON/OFF Register (ish returns a 1, which is NOTed, then ORed with the stream of 0's from the ON/OFF Button, resulting in a 0), which then sends this 0 to the Clock through the Haltwire, thus closing the flow of the Power Supply to the Computer (see Clock circuitry). Data Memory: This is the memory used by the CPU (see Memory on the farthest Right in the CPU overview Diagram). It requires the 4 bit address (for the ASD to parse), the R/W bit and 4 bit Data (in the case of writing to the memory). The ASD outputs a 1 for the correct output and a 0 for all others. If the

16 R/W bit is a 0 (Read), the data from the appropriate address is read and outputted into the Mem Register. If the R/W bit is 1 (Write), the Data that is inputted is written into the appropriate address and nothing is outputted. Since the R/W bit is either a 0 or 1, there is never a case where reading and writing occur simultaneously. The bits are also clocked so there is even extra security in not reading and writing at the same time.

17 2.4.0 WRITE WRITE OVERVIEW Brief Descriptive Outline The Write phase does not include all instructions which write to memory (eg. STORE writes to data memory in A-Out Update Phase 1 Phase). It does however, include -only- write operations and so this name is the most fitting. In this phase the Register Bank Memory is written to by the LOAD instruction and the PC counter is updated with the Branching (BiZ) address if the iszero (iz) bit agrees. We could have grouped the PC update under the FETCH instruction but it seems more appropriate to do it this way. A simple Mux like MOX black box decides which address is put into the PC based on the 1-Bit iz and the 1-Bit BZO inputs. If there is no branching instruction currently present then BZO will cancel all iz results. Finally, the ALU Register sends its data directly to the Register Memory, or more specifically, the A-Out Register, without further assistance from the CU, unless of course it has not received any in the previous stage. Step by Step 1. Information is released from the Mem Reg., the R/W Reg., and the Stb Reg. 2. Since Stb Reg is a Sign extended 2-Bit address, the SS circuitry shrinks it back down to 2-Bits to allow Register Memory Bank addressing. 3. If R/W is 0 then nothing occurs in memory 4. If R/W is 0 and the selected register is A-Out then there may still be a write to memory. We have however, taken care of this situation by making sure that the memory wires don't contain 0 but rather -nothing- so that the free access to A-Out (which is unhampered by the R/W register) is stopped by the lack of information in the memory bank. 5. If R/W is 1 then a write to memory occurs 6. The second set of operations starts with the release of the iz status bit from the izbiz Register (0,1), with the BIZ address from the same register, and with the release of the BZO status bit from the BZO register. 7. The iz and BZO status bits allow the BIZ address to update the PC if and only if they are both 1 ie. only if the BIZ command was selected and there is, in fact, a zero in the specified register. Otherwise MOX selects the 2-Unit incremented PC address from the FETCH instruction which is executing another instruction. 8. We have shown certain parts of the FETCH circuitry to better situate the reader. These parts (like UAA and UAA(2) ) do not play any role in this stage. 9. The final and mostly trivial operation is the clocked release of the ALU Reg's information to the Register Memory Bank. The ALU Reg can write directly to the A-Out Register in memory because of the special wiring inside memory. We note also that the writing itself does not interfere with the current reading because it only comes into effect at the next clock tick due to keyed AND gates inside memory. We see then that memory writing occurs through the RDR addressing device, but that the ALU Reg writes directly to memory itself.

18 2.4.2 WRITE HARDWARE DESCRIPTION Sign Shrink (SS): Another in the class of extremely circuitous circuits, this changes a 4 bit input into a 2 bit output by ignoring the first two bits. Sign Extend 1 (SE1): This is a very complex circuit which took many years to develop. It extends a two bit signal into a four bit output. MOX : The MOX black box chooses between two 4-Bit Data based on a single 1-Bit 'selection' input. If the input is '1' then the first 4-Bit Data is chosen, if it is '0' then the second goes through. This is achieved by using keyed AND gates, with the 1-Bit input signal acting as the key. Hence a 0 input to any AND gate prevents ALL information from flowing through it, thus creating perfect dichotomy.

19 2.5.0 STOP/HALT/ON OVERVIEW We have not paid much attention to these three instructions within the context of individual phases because the main purpose here is to disrupt the flow of things, not to continue operating in harmony with further instructions, or to be the very first instruction to occur. We hope this can be forgiven in light of the beautiful descriptions which will follow hereafter. The Button The reader may have noticed a large red button near the PC. This button is used to 'start' the computer and initialize the PC to zero. Let us assume now the computer is off. The button is pushed and a single 1 is emitted into the hardware. This 1 travels to the CU and is stored in the ON/OFF register and continuously emitted thereafter (until changed.) The ON/OFF register then sends this 1 directly to the AND gate near the power supply. (without requiring any clock ticks: it is a CSR register). The 1 is ANDed with the Power Supply which now begins powering the clock and everything else. The ON/OFF register continues to emit 1 s until it is updated by some other information, so the power supply continues to power the clock and the rest of the CPU. The button, when pressed, also sends its 1 towards the PC counter but the signal is stopped at the PCI black box. Inside the PCI black box there is a keyed AND gate waiting for the first clock tick to allow the 1 to pass through. The key to the AND gate is not the clock we must note, it is the button's 1. The 1 is then NOTed and extended into four zeros which directly travel to the PC counter to update it. We note here that the only time these zeros are sent to the PC counter is at computer start up, otherwise the keyed AND gate in the PCI prevents any information from traveling through. This then justifies the structure of the PC counter. Finally, when not pressed, the button sends 0 to the keyed AND gate in the PCI black box, which prevents the PC counter from being modified. The 0 also travels towards the ON/OFF register but does not change the ON/OFF register unless the ish box also emits a 0. This way ON/OFF remains 1 unless the HALT instruction is sent (see below.) STOP STOP's intent is to mysteriously stop the program. This is achieved by suspending the clock ie. sending a 0 to be ANDed with the clock's 1 s. The STOP opcode makes use of the iss box inside the CU which only returns a 1 if the opcode matches x x x x. This 1 is then NOTed and sent directly to the clock where it suspends all further operations. We have not provided any circuitry to re-start the program but note that nothing is lost during the suspension. Finally we note that the circuitry for the STOP command still allows the computer to be started. Although we did not mention this earlier, the Button also sends its 1 to the WAM (STOP) register inside the CU. The structure of WAM then allows this 1 to be continuously emitted without any further inputs, thus allowing the CPU to function before any instructions uphold WAM's status. HALT HALT is meant to turn off the computer. This is achieved by negating the ON/OFF register used to turn on the computer (see above). HALT turns the ON/OFF register back into 0 and this 0 then negates the Power Supply. Since the Power Supply is now no longer powering anything, the computer shuts off. It can be turned on again using the button.

20 3.0.0 ASSEMBLY LANGUAGE ASSEMBLY INSTRUCTIONS Table 4: List of Assembly Commands NAME 1 st Parameter 2 nd Parameter ADD Rx Ry SUB Rx Ry MULT Rx Ry STORE Rx Address LOAD Ry Address BIZ Rx Address STOP N/A N/A COMP Rx N/A HALT N/A N/A OP-CODE BINARY TABLE Table 5: OP-CODE By Instruction Name NAME ADD 0 0 Rx Rx Ry Ry 0 0 SUB 0 0 Rx Rx Ry Ry 0 1 MULT 0 0 Rx Rx Ry Ry 1 X STORE 0 1 Rx Rx Addr Addr Addr Addr LOAD 1 0 Ry Ry Addr Addr Addr Addr BIZ 1 1 Rx Rx Addr Addr Addr Addr STOP X X X X COMP Rx Rx X X HALT X X X X

21 3.3.0 DESCRIPTION OF EXECUTION NAME Table 2 (From Section 2.2.2): Output of CU based on Instruction OP-CODE AUP1S (A-Wire) AOS (AddrO) iss ish C M S SEO R/W Register B Register ADD SUB MULT COMP LOAD STORE BIZ STOP HALT ADD, MULT, SUB LOAD Bits 0-7 travel into the CU (see Table 2 for the individual results) Bits 2,3 denote the address of a register in the Register Memory Bank. The contents of the register denoted by 2,3 is read. Bits 4,5 denote the address of a second register in the Register Memory Bank. The contents of the register denoted by 4,5 is read. The 4-Bit register contents triumph over the sign extended 2,3 address and the address denoted by 4-7 thanks to the SEO and AddrO signals. Essential: Two registers in the Register Memory Bank are read and stored in the Right and Left Registers. A-Out Update Phase 1 Both the Right and Left registers flow into the ALU The appropriate operation is performed by the ALU depending on the C M S register and the result is stored in the ALU Register (temporary) For SUB the Left Register is subtracted from the Right Register. The CU prevents anything else from happening. WRITE The contents from the ALU register are stored in A-OUT in the Register Memory Bank. The PC counter is not incremented in any abnormal fashion. No other memory writing occurs.

22 3.3.2 COMP LOAD Bits 0-7 travel into the CU (see Table 2 for the individual results) Bits 2,3 are always 1 1 and do not access the Register Memory Bank. Instead they are sign extended and selected to travel into the Right Register but this has no subsequent effects. Bits 4,5 denote the address of a register in the Register Memory Bank. The contents of the register denoted by 4,5 is read and ultimately travels into the Left Register. The sign extended 2,3 address triumphs over the [non-existent] register contents. The 4,5 register contents triumph over bits 4-7. Essential: Only the Left Register is of importance in subsequent phases. A-Out Update Phase 1 Both the Right and Left Registers flow into the ALU. The Left Register is Two's Complemented and stored in the ALU Register The sign extended contents in the Right Register do not contribute to the final result. The CU prevents anything else from reaching the data memory. WRITE The contents from the ALU Register are stored in A-OUT in the Register Memory Bank. The PC counter is not incremented in any abnormal fashion. No other memory writing occurs.

23 3.3.3 STORE LOAD Bits 0-7 travel into the CU (see Table 2 for the individual results) Bits 2,3 read the contents from the register at address 2,3. This interpretation triumphs over the sign extended address Bits 4-7 denote an address to be written to in memory. This address triumphs over the register read at address 4,5. The address of 2,3 flows into Right Register. The address 4-7 flows into the Left Register. A-Out Update Phase 1 Both the Right and Left Registers flow into the ALU but this result plays no part in subsequent processing Both Right and Left also bypass the ALU entirely and these bypassed binary version are chosen by AUP1S. Left is sent on to the Data Memory by the SEL (Biz Selector) where it serves as an address. Right is also sent on to the Data Memory where it is written in at the address denoted by Left. Right is not sent to the Stb Reg (0). After Right is written to memory, no further actions occur. WRITE No writing occurs because the Stb Reg (0) is empty. The PC is incremented normally.

24 3.3.4 LOAD LOAD Bits 0-7 travel into the CU (see Table 2 for the individual results) Bits 2,3 are an address. The sign extended version triumphs over the read contents. Bits 4-7 denote an address to be read from memory. This address triumphs over the register read at address 4,5. The contents of 2,3 flow into Right Register. The address 4-7 flows into the Left Register. A-Out Update Phase 1 Both the Right and Left Registers flow into the ALU but this result plays no part in subsequent processing Both Right and Left also bypass the ALU entirely and these bypassed binary version are chosen by AUP1S. Left is sent on to the Data Memory by the SEL (Biz Selector) where it serves as an address. The Data Memory is read at address denoted by the Left register (thanks also to the R/W signal) and the contents stored in the Mem. Reg inside the Data Memory. The Right Register contents are sent to the Stb Reg (0) WRITE The Mem. Reg now serves as the contents to be written into the Register Memory Bank. Stb Reg (0) is shrunk back down to its original 2-Bit address. The contents of Mem. Reg are written to the register at the address denoted by Stb Reg (0) The PC is incremented normally

25 3.3.5 BIZ (LOAD, A-OUT UPDATE PHASE 1, Write) LOAD Bits 0-7 travel into the CU (see Table 2 for the individual results) Bits 2,3 read the contents from the register at address 2,3. This interpretation triumphs over the sign extended address Bits 4-7 denote an address to be branched to [if possible]. This address triumphs over the register read at address 4,5. The address of 2,3 flows into Right Register. The address 4-7 flows into the Left Register. A-Out Update Phase 1 The Right Register flows into the ALU. The is-zero? Register is updated with an answer. The ALU also operates on Right in some arbitrary fashion but the result will not be written anywhere. The Left Register bypasses the ALU entirely. The SEL (Biz Selector) sends the Left contents to the izbiz Register. The is-zero? Register is also sent to the izbiz Register. SEL ensures that the Mem. Reg remains empty; this way there is no address specified for the RMB in the Write stage. WRITE Nothing is written to the RMB If the contents of the Right register were zero then the MOX selector chooses the Branch Address from the izbiz Register to go to the PC instead of the Uniformly Incremented Address from the simultaneously occurring Fetch cycle. We note here that for any other non-biz instruction, the BZO output from the BZO Register always makes MOX choose the uniformly incremented address.

26 3.3.6 STOP/HALT The hardware used to implement this instruction is discussed in section We give here only a brief overview of the goings in each phase STOP LOAD Bits [0-3] are sent to the CU. The CU sends a 0 into the WAM register. The WAM register blocks all further input into itself and also kills the clock. HALT LOAD Bits [0-3] are sent to the CU. The CU sends a 0 into the ON/OFF register. The ON/OFF register blocks all further input into itself and kills the Power Supply Sample Program Code Needed For CPU To Run LOAD R ADD R0 R0 MULT R0 A-OUT SUB A-OUT R0 STORE R BIZ A-OUT 1110 COMP R0 STOP